Analog Devices ADuCM320 Quick user guide
ADuCM320 Hardware Reference Manual
UG-498
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com
How to Set Up and Use the ADuCM320
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. C | Page 1 of 196
SCOPE
This reference manual provides a detailed description of the ADuCM320 functionality and features.
DISCLAIMER
Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
11176-001
MEMORY
2 × 128kB FLASH
32kB SRAM
ARM
CORTEX-M3
PROCESSOR
MUX
RESET
AIN0
AIN5
AIN6
AIN15
BUF_VREF2V5
VDAC7
IDAC0
ADuCM320
PVDDx
AGNDx
IOVDDx
IOGNDx
GENERAL
PURPOSE
I/O PORTS
SWDIO
SWCLK
GPIO PORTS
UART
2 × SPI
2×I
2
C
EXT IRQs
MDIO
PLA
INTERNAL
CHANNELS:
TEMPERATURE,
AV
DD
, IOV
DD
2.5V BAND GAP
DMA
NVIC
RESET SYSTEM
SERIAL WIRE
CLOCK SYSTEM
32.768kHz
16MHz OSC
80MHz PLL
3 × GENERAL
PURPOSE TIMER
WATCHDOG TIMER
WAKE-UP TIMER
PWM
VDAC
IDAC3
14-BIT
SAR ADC
IDAC
IDAC
COMPARATOR
X
TAL
O
X
TALI ECLKIN
PGND
AVDDx
DGNDx
PWM0 TO
PWM6
1.8 V LDO
VDAC0 VDAC
Figure 1.
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TABLE OF CONTENTS
Scope .................................................................................................. 1
Disclaimer.......................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 4
Using the ADuCM320 Hardware Reference Manual .................. 6
Number Notations........................................................................ 6
Register Access Conventions ...................................................... 6
Acronyms and Abbreviations ..................................................... 6
Introduction to the ADuCM320 .................................................... 7
Main Features of ADuCM320 .................................................... 7
Memory Organization ................................................................. 8
Clocking Architecture.................................................................... 10
Clocking Architecture Features................................................ 10
Clocking Architecture Block Diagram .................................... 11
Clocking Architecture Overview.............................................. 12
Register Summary: Clock Architecture................................... 12
Clocking Architecture Operation ............................................ 12
Register Details: Clock Architecture........................................ 13
Power Management Unit............................................................... 16
Power Management Unit Features ........................................... 16
Power Management Unit Overview......................................... 16
Power Management Unit Operation........................................ 16
Code Examples ........................................................................... 17
Register Summary: Power Management Unit ........................ 18
Register Details: Power Management Unit ............................. 18
ARM Cortex-M3 Processor .......................................................... 19
ARM Cortex-M3 Processor Features....................................... 19
ARM Cortex-M3 Processor Overview .................................... 19
ARM Cortex-M3 Processor Operation................................... 19
ARM Cortex-M3 Processor Related Documents................... 20
ADC Circuit .................................................................................... 21
ADC Circuit Features ................................................................ 21
ADC Circuit Block Diagram..................................................... 21
ADC Circuit Overview.............................................................. 22
ADC Circuit Operation............................................................. 22
ADC Transfer Function............................................................. 23
ADC Typical Setup Sequence ................................................... 24
ADC Input Buffer....................................................................... 24
ADC Internal Channels............................................................. 24
ADC Support Circuits ............................................................... 25
Register Summary: ADC Circuit ............................................. 28
Register Details: ADC Circuit .................................................. 29
Register Summary: Additional Registers ................................ 33
Register Details: Additional Registers ..................................... 33
Analog Comparator ....................................................................... 35
Analog Comparator Features.................................................... 35
Analog Comparator Overview ................................................. 35
Analog Comparator Operation ................................................ 35
Register Summary: Analog Comparator................................. 36
Register Details: Analog Comparator...................................... 36
IDACs............................................................................................... 37
IDAC Features ............................................................................ 37
IDAC Block Diagram................................................................. 37
IDAC Overview.......................................................................... 37
Register Summary: IDAC ......................................................... 40
Register Details: IDAC............................................................... 40
VDACs ............................................................................................. 43
VDAC Features........................................................................... 43
VDAC Block Diagram............................................................... 43
VDAC Overview ........................................................................ 43
VDAC Operation ....................................................................... 43
Register Summary: VDAC........................................................ 44
Register Details: VDAC............................................................. 44
System Exceptions and Peripheral Interrupts............................. 49
Cortex-M3 and Fault Management ......................................... 49
External Interrupt Configuration ............................................ 53
Register Summary: External Interrupts .................................. 53
Register Details: External Interrupts ....................................... 53
Low Voltage Analog Die Interrupt Configuration................. 56
Register Summary: Low Voltage Die Interrupts .................... 57
Register Details: Low Voltage Die Interrupts ......................... 57
Reset ................................................................................................. 59
Reset Features ............................................................................. 59
Reset Operation.......................................................................... 59
Register Summary: Reset .......................................................... 60
Register Details: Reset ............................................................... 60
DMA Controller ............................................................................. 61
DMA Features............................................................................. 61
DMA Overview .......................................................................... 61
DMA Operation ......................................................................... 61
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DMA Interrupts ..........................................................................61
DMA Priority...............................................................................62
Channel Control Data Structure...............................................62
Control Data Configuration ......................................................63
DMA Transfer Types (CHNL_CFG[2:0])................................64
Address Calculation....................................................................66
Aborting DMA Transfers...........................................................66
Register Summary: DMA...........................................................67
Register Details: DMA................................................................67
Flash Controller...............................................................................73
Flash Controller Features...........................................................73
Flash Controller Overview.........................................................73
Flash Controller Operation........................................................73
Flash Memory Operation...........................................................74
Flash Protection...........................................................................78
Register Summary: Flash Controller........................................82
Register Details: Flash Controller.............................................82
Silicon Identification.......................................................................90
Silicon Identification Memory Mapped Registers..................90
Digital Die ID Register...............................................................90
Low Voltage Die ID Register .....................................................90
Digital I/Os.......................................................................................91
Digital I/Os Features...................................................................91
Digital I/Os Block Diagram.......................................................91
Digital I/Os Overview ................................................................91
Digital I/Os Operation ...............................................................91
Digital Port Multiplex.................................................................94
Register Summary: Digital I/O .................................................96
Register Details: Digital I/O.......................................................97
I2C Serial Interface ....................................................................... 101
I2C Features ............................................................................... 101
I2C Overview............................................................................. 101
I2C Operation............................................................................ 101
I2C Operating Modes............................................................... 103
Register Summary: I2C0 ......................................................... 105
Register Details: I2C0 .............................................................. 105
Register Summary: I2C1 ......................................................... 114
Register Details: I2C1 .............................................................. 114
Serial Peripheral Interfaces ......................................................... 123
SPI Features............................................................................... 123
SPI Overview ............................................................................ 123
SPI Operation ............................................................................123
SPI Transfer Initiation ..............................................................124
SPI Interrupts ............................................................................126
SPI Wire-OR’ed Mode (WOM)...............................................127
SPI CSERR Condition ..............................................................127
SPI DMA ....................................................................................127
SPI and Power-Down Modes ..................................................128
Register Summary: SPI0 ..........................................................128
Register Details: SPI0................................................................128
Register Summary: SPI1 ..........................................................132
Register Details: SPI1................................................................132
UART Serial Interface...................................................................137
UART Features ..........................................................................137
UART Overview........................................................................137
UART Operation.......................................................................137
Register Summary: UART .......................................................141
Register Details: UART ............................................................141
PLA .................................................................................................146
PLA Features..............................................................................146
PLA Overview ...........................................................................146
PLA Operation ..........................................................................147
Register Summary: PLA...........................................................150
Register Details: PLA................................................................150
General-Purpose Timers..............................................................154
General-Purpose Timers Features..........................................154
General-Purpose Timers Block Diagram ..............................154
General-Purpose Timers Overview .......................................154
General-Purpose Timers Operation ......................................155
Register Summary: General-Purpose Timer 0 .....................157
Register Details: General-Purpose Timer 0 ..........................157
Register Summary: General-Purpose Timer 1 .....................160
Register Details: General-Purpose Timer 1 ..........................160
Register Summary: General-Purpose Timer 2 .....................163
Register Details: General-Purpose Timer 2 ..........................163
Watchdog Timer............................................................................166
Watchdog Timer Features........................................................166
Watchdog Timer Block Diagram............................................166
Watchdog Timer Overview .....................................................166
Watchdog Timer Operation ....................................................166
Register Summary: Watchdog Timer.....................................167
Register Details: Watchdog Timer..........................................167
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Wake-Up Timer ............................................................................ 169
Wake-Up Timer Features ........................................................ 169
Wake-Up Timer Block Diagram............................................. 169
Wake-Up Timer Overview...................................................... 169
Wake-Up Timer Operation..................................................... 169
Register Summary: Wake-Up Timer .....................................172
Register Details: Wake-Up Timer .......................................... 172
PWM .............................................................................................. 176
PWM Features .......................................................................... 176
PWM Overview........................................................................ 176
PWM Operation....................................................................... 176
PWM Interrupt Generation.................................................... 179
Register Summary: PWM .......................................................180
Register Details: PWM ............................................................ 180
MDIO............................................................................................. 184
MDIO Features......................................................................... 184
MDIO Overview....................................................................... 184
MDIO Operation...................................................................... 184
Block Switching ........................................................................ 186
Register Summary: MDIO Interface (MDIO)...................... 191
Register Details: MDIO........................................................... 191
Hardware Design Considerations .............................................. 194
Typical System Configuration ................................................ 194
Serial Wire Debug Interface.................................................... 196
REVISION HISTORY
1/2017—Rev. B to Rev. C
Changes to Clocking Architecture Operation Section.............. 12
Changes to ADC Circuit Features Section.................................. 21
Changes to ADC Circuit Overview Section ............................... 22
Changes to Single-Ended Mode Section and Differential
Section.............................................................................................. 23
Changes to ADC Voltage Reference Selection Section.............. 26
Changes to Table 23........................................................................ 34
Added IDAC Thermal Shutdown Section................................... 39
Changes to Writing to Flash Section............................................ 75
Changes to Table 121...................................................................... 94
Changes to Table 182.................................................................... 130
2/2016—Rev. A to Rev. B
Changes to Table 7.......................................................................... 14
Changes to Table 12........................................................................ 28
Changes to Protection, Integrity Section..................................... 72
Added ECC Error Handling Section, ECC Error During Read
Section, and ECC Error During Execution of Sign Command
Section.............................................................................................. 76
Changes to Table 95 and Table 96 ................................................ 80
Added ECC Enable/Disable, Error Response Register Section,
Flash 0 ECC Error Address Register Section, Flash 1 ECC Error
Address Register Section, and Table 112 to Table 114;
Renumbered Sequentially.............................................................. 86
Added MDIO Interrupt Power-Up Register Write Sequence
Section............................................................................................ 184
1/2015—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Register Access Conventions Section........................ 6
Changes to Introduction to the ADuCM320 Section.................. 7
Moved Register Summary: Clock Architecture Section............ 12
Changes to Table 4 and Clocking Architecture Operation
Section.............................................................................................. 12
Change to Table 5 ........................................................................... 13
Changes to Table 6 and Table 7 .................................................... 14
Added Clocking Status Register Section and Table 8;
Renumbered Sequentially ............................................................. 15
Changes to Debug Support Section ............................................. 19
Changes to ADC Voltage Reference Selection Section ............. 26
Added Figure 8; Renumbered Sequentially ................................ 27
Change to Table 14 ......................................................................... 30
Changes to Table 16 ....................................................................... 31
Changes to Table 17 ....................................................................... 32
Changes to Table 22 ....................................................................... 33
Changes to Table 25 ....................................................................... 36
Changes to Case 2—Turn On IDAC2 but to Set the Output to
0 mA with the Lowest Possible Offset Section ........................... 38
Changes to Table 74 ....................................................................... 62
Changes to Table 75 ....................................................................... 64
Changes to Table 76 ....................................................................... 65
Added Aborting DMA Transfers Section.................................... 65
Changed Top of Flash Blocks Section to Reserved Flash
Locations Section............................................................................ 73
Changes to Erasing Flash Section and Signature Section......... 74
Changes to CPU Execution Speed Section ................................. 76
Changes to Memory Cache Section............................................. 77
Changes to Table 95 and Table 96 ................................................ 79
Changes to Cache Status Register Section .................................. 84
Added Table 112 ............................................................................. 84
Changes to Cache Setup Register Section and Cache Key
Register Section .............................................................................. 85
Added Table 113 and Table 114.................................................... 85
Deleted Shared MDIO Pins Section ............................................ 85
Changes to Digital I/Os Features Section and Digital I/Os
Overview Section............................................................................ 86
Added Inaccessible Bits Section ................................................... 86
Changes to I/O Pull-Up Enable (GPxPUL) Section.................. 87
Changes to Open-Drain Enable (GPxODE) Section................. 88
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Changes to Table 119 ......................................................................91
Changes to Register Details: Digital I/O Section, GPIO Port
Configuration Registers Section, GPIO Port Output Enable
Registers Section, Table 120, and Table 121.................................92
Added GPIO Port Pull-Down Enable Registers Section and
Table 123...........................................................................................93
Changes to GPIO Port Pull-Up Enable Registers Section,
GPIO Port Input Path Enable Registers Section, GPIO Port
Registered Data Input Registers Section, Table 122, Table 124,
and Table 125 ...................................................................................93
Deleted GPIO Port 4 Configuration Register Section, GPIO
Port 4 Output Enable Register Section, GPIO Port 4 Pull-Down
Enable Register Section, GPIO Port 4 Input Path Enable
Register Section, GPIO Port 4 Registered Data Input Section,
and Table 126 to Table 130.............................................................94
Deleted GPIO Port 4 Data Output Register Section, GPIO Port
4 Data Out Set Register Section, GPIO Port 4 Data Out Clear
Register Section, GPIO Port 4 Pin Toggle Register Section,
GPIO Port 4 Open Drain Enable Register Section, and Table
131 to Table 135...............................................................................95
Deleted GPIO Port 5 Configuration Register Section, GPIO
Port 5 Output Enable Register Section, GPIO Port 5 Pull-Down
Enable Register Section, GPIO Port 5 Input Path Enable
Register Section, d3fGPIO Port 5 Registered Data Input
Section, and Table 136 to Table 140..............................................96
Deleted GPIO Port 5 Data Output Register Section, GPIO Port
5 Data Out Set Register Section, GPIO Port 5 Data Out Clear
Register Section, GPIO Port 5 Pin Toggle Register Section,
GPIO Port 5 Open Drain Enable Register Section, and Table
141 to Table 145...............................................................................97
Changes to GPIO Port Data Output Registers Section, GPIO
Port Data Out Set Registers, GPIO Port Data Out Clear
Registers, Table 126, Table 127, and Table 128............................94
Changes to GPIO Port Pin Toggle Registers Section, GPIO Port
Open-Drain Enable Registers, Table 129, and Table 130...........95
Changes to I2C Features Section ...................................................96
Added I2C Slave Mode Late Loading of I2CSTX Issue
Section ..............................................................................................99
Changes to Table 133 ....................................................................101
Changes to Table 142 ....................................................................104
Changes to Table 142 ....................................................................105
Changes to Table 154 ....................................................................110
Changes to Table 163 ....................................................................113
Changes to Table 164 ....................................................................114
Changes to PWM Overview Section and PWM Operation
Section ............................................................................................172
Changes to Figure 32 ....................................................................173
Changes to Table 263 ....................................................................174
Changes to H-Bridge Mode, Table 264, and PWM Interrupt
Generation Section .......................................................................175
Changes to Table 266 ....................................................................176
Change to Figure 37......................................................................183
Changes to Table 287 ....................................................................185
Changes to Figure 38 ....................................................................186
Changes to Table 294 and Table 296...........................................189
6/2014—Revision 0: Initial Version
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USING THE ADuCM320 HARDWARE REFERENCE MANUAL
NUMBER NOTATIONS
Table 1. Number Notations
Notation Description
Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0.
V[x:y] Bit field representation covering Bit x to Bit y of a value or a field (V).
0xNN Hexadecimal (Base 16) numbers are preceded by the prefix 0x.
0bNN Binary (Base 2) numbers are preceded by the prefix 0b.
NN Decimal (Base 10) numbers are represented using no additional prefixes or suffixes.
REGISTER ACCESS CONVENTIONS
Table 2. Register Access Conventions
Mode Description
RW Memory location has read and write access.
RC Memory location is cleared after reading it.
R Memory location is read access only. A read always returns 0, unless otherwise specified.
W Memory location is write access only.
MMR bits that are not documented are reserved. When writing to MMRs with reserved bits, the reserved bits should be written with the
value in the reset column of the relevant MMR description, unless otherwise noted.
ACRONYMS AND ABBREVIATIONS
Table 3. Acronyms and Abbreviations
Acronym/Abbreviation
Description
ADC Analog-to-digital converter
DMA Direct memory access
DDM Digital diagnostic monitoring
GPIO General-purpose input and output
LSB Least significant byte/bit
MDC Management data input/output clock
MDIO Management data input/output
MMD
MDIO manageable device (slave)
MMR Memory mapped register
MSB Most significant byte/bit
NMI Nonmaskable interrupt
NVIC Nested vectored interrupt controller
NVR
Nonvolatile registers
Rx Receive
SAR Successive approximation register
SOA Semiconductor optical amplifier
SPI Serial peripheral interface
STA Station management entity (host/master)
SWD Sync word detect/serial wire debug
Tx Transmit
UART Universal asynchronous transmitter
VR Volatile registers
WDT Watchdog timer
WUT Wake-up timer
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INTRODUCTION TO THE ADuCM320
The ADuCM320 is a fully integrated single-package device that incorporates high performance analog peripherals together with digital
peripherals controlled by an 80 MHz ARM Cortex™-M3 processor and integral flash for code and data.
The ADC on the ADuCM320 provides 14-bit, 1 MSPS data acquisition on up to 16 input pins that can be programmed to be single-ended
or differential. Additionally, chip temperature and supply voltages can be measured. The ADC input voltage is 0 V to VREF. A sequencer is
provided that allows a user selected set of ADC channels to be measured in sequence without software involvement during the sequence.
The sequence can optionally auto repeat at a user-selectable rate.
Up to eight voltage DACs are provided with output ranges programmable to one of two voltage ranges. The DAC outputs have an
enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. On the ADuCM320, four
current output DAC sources are provided. The output currents are programmable with ranges of 0 mA to 150 mA. A low drift band gap
reference and a voltage comparator complete the analog input peripheral set.
The microcontroller core is a low power ARM Cortex-M3 processor, a 32-bit RISC machine that offers up to 100 MIPS peak
performance. Also integrated on chip are two 128 kB Flash/EE memory and 32 kB of SRAM. The flash comprises two separate 128 kB
blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block.
The ADuCM320 operates from an on-chip oscillator or a 16 MHz external crystal and a PLL at 80 MHz. This clock can optionally be
divided down to reduce current consumption. Additional low power modes can be set via software. In the normal operating mode, the
ADuCM320 digital core consumes about 300 µA/MHz.
The device includes an MDIO interface capable of operating at up to 4 MHz. The capability to simultaneously execute from one flash
block and write/erase the other flash block makes the ADuCM320 ideal for 40 G/100 G optical applications. User programming is eased
by receiving interrupts after PHYADR, DEVADD, and end of frame and by having PHYADR and DEVADD hardware comparators. In
addition, the nonerasable kernel code plus flags in user flash can provide assistance to allow user code to robustly switch between the two
blocks of user flash code and data spaces as required for MDIO.
The ADuCM320 also integrates a range of on-chip peripherals that can be configured via software control as required in the application.
These peripherals include one UART, two I2Cs, two SPI serial I/O communication controllers, GPIO, 32-element programmable logic
array, three general-purpose timers, one wake-up timer, and one system watchdog timer. In addition, 16-bit PWMs with seven output
signals are provided.
GPIO pins on the device power up in input mode. In output mode, the software can choose between open-drain mode and push-pull
mode. The outputs can drive at least 4 mA. The pull-ups can be disabled and enabled in software. In GPIO mode, the inputs can always
be enabled to monitor the pins. The GPIO pins can also be programmed to handle digital or analog peripheral signals, in which case the
pin characteristics are matched to the specific requirement.
A large support ecosystem is available for the ARM Cortex-M3 processor, which eases product development of the ADuCM320. Access is
via the JTAG serial wire interface. On-chip factory firmware supports in-circuit serial download via MDIO. These features are incorporated in a
low cost QuickStart development system supporting this precision analog microcontroller family.
MAIN FEATURES OF ADuCM320
ADC
•Multichannel, 14-bit, 1 MSPS SAR ADC
•Low drift on-chip voltage reference
DACs
•Eight voltage output DACs
oVDACs are 12-bit monotonic
•Four current output DACs
oCurrent DACs are 12-bit monotonic
•Low drift, on-chip 2.5 V voltage reference source
oTwo buffered reference outputs
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Communication
•UART
oIndustry standard, 16450 UART peripheral
oSupport for DMA
•Two I2Cs
o2-byte transmit and receive FIFOs for the master and slave
oSupport for DMA
•Two SPIs
oMaster or slave mode with separate 4-byte Rx and Tx FIFOs
oRx and Tx DMA channels
•16-bit PWM with seven output channels
•Multiple GPIO pins
Processing
•ARM Cortex-M3 processor, operating from an internal 80 MHz system clock
•Two 128 kB Flash/EE memory, 32 kB SRAM
•In-circuit download and debug via serial wire
•On-chip MDIO download capability
On-Chip Peripherals
•Three general-purpose timers
•Wake-up timer
•Watchdog timer
•32-element programmable logic array (PLA)
Packages and Temperature Range
•6 mm × 6 mm, 96-ball BGA package, −40°C to +85°C
Tools
•Low cost development system
•Third-party compiler and emulator tool support
Applications
•Optical networking—10 G, 40 G, and 100 G modules
•Industrial control and automation systems
•Smart sensors, precision instrumentation
•Base station systems
MEMORY ORGANIZATION
The ADuCM320 memory organization is described in this section.
Features
•Cortex-M3 memory system features
oPredefined memory map.
oSupport for bit-band operation for atomic operations.
oUnaligned data access.
•ADuCM320 on-chip peripherals are accessed via memory mapped registers, situated in the bit-band region.
•User memory sizes options:
o32 kB SRAM
oTwo 128 kB Flash/EE memory
•On-chip kernel for manufacturer data and in-circuit download
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0xFFFF FFFF
VENDOR SPECIFIC
0xE010 0000
PRIVATE
PERIPHERAL
BUS—EXTERNAL
PRIVATE
PERIPHERAL
BUS—INTERNAL
0xE00F FFFF
0xE004 0000
0xE003 FFFF
0xE000 EF00
ADuCM320 MMRs
0xE000 0000 0xE000 E000
EXTERNAL DEVICE
1GB
(NOT AVAILABLE IN
ADuCM320)
EXTERNAL RAM
1GB
(NOT AVAILABLE IN
ADuCM320)
0xDFFF FFFF
0xA000 0000
0x9FFF FFFF
0x6000 0000
PERIPHERAL
0.5GB
0x5FFF FFFF
0x400A FFFF
ADuCM320 MMRs
0x4000 0000 0x4000 0000
SRAM 0.5GB
0x3FFF FFFF
0x2000 7FFF
ADuCM320 32kB SRAM
0x2000 0000 0x2000 0000
CODE 0.5GB
0x1FFF FFFF
0x0004 0FFF
ADuCM320 KERNEL SPACE
0x0000 0000 0x0004 0000
0x0003 FFFF
ADuCM320 256kB
FLASH/EE MEMORY
0x0000 0000
11176-002
Figure 2. Cortex-M3 Memory Map Diagram
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CLOCKING ARCHITECTURE
CLOCKING ARCHITECTURE FEATURES
The ADuCM320 integrates two on-chip oscillators and circuitry for an external crystal and external clock source:
•LFOSC is a 32 kHz low power internal oscillator that is used in low power modes.
•HFOSC is a 16 MHz internal oscillator that is used in active mode. This is the default input to the PLL.
•HFXTAL is a 16 MHz external crystal oscillator.
•External clock input (ECLKIN) via GPIO pin.
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CLOCKING ARCHITECTURE BLOCK DIAGRAM
HFOSC
16MHz OSC
WATCHDOG
TIMER
WAKE-UP
TIMER
TIMER0CLK
TIMER1CLK
LFOSC
(INTERNAL)
ECLKIN
P1.0
PCLK
PCLK
HCLK
PCLK
HCLK
I2C0
UART
D2D
SPI0
SPI1
CORE
PWM
TIMER2CLK
PCLK
HCLK
80MHZ SPLL
HFXTAL
16MHz OSC
CDPCLK
(CLKCON1[10:8]) I2C1
FLASH
ACLK
(TO LV DIE, ADC)
CDHCLK
(CLKCON1[2:0])
CLKCON5[3]
CLKCON5[4]
CLKCON5[5]
CLKCON5[6]
CLKCON5[0]
CLKCON5[1]
PCLK
UCLK
HCLK
PCLK
CDD2DCLK
(CLKCON1[11])
0
1
01
00
11
01
11
00
00
01
11
10
00
01
11
10
00
01
11
10
T4CON[9:10]
T0CON[5:6]
T1CON[5:6]
T2CON[5:6]
CLKCON0[11]
CLKCON0[1:0]
11176-003
Figure 3. Clocking Architecture Block Diagram
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CLOCKING ARCHITECTURE OVERVIEW
The system clock, UCLK, can be selected from a 16 MHz oscillator or from an 80 MHz PLL output (default). An external clock on P1.0
can also be used for test purposes.
Internally, the system clock is divided into separate clocks:
•UCLK system clock
•HCLK for the flash, SRAM, and DMA
•PCLK for most peripherals
•ACLK for the analog section of the chip; this is based on PCLK output and goes to the low voltage analog die
All ADC performance details are based on a 20 MHz ACLK (CLKCON1[10:8] = 0b010). Performance at other clock speeds is not
guaranteed; therefore, CLKCON1[10:8] should not be changed when the ADC is being used.
REGISTER SUMMARY: CLOCK ARCHITECTURE
Table 4. Clocking Register Summary
Address Name Description Reset RW
0x40028000 CLKCON0 Misc clock settings register 0x0041 RW
0x40028004 CLKCON1 Clock dividers register 0x0200 RW
0x40028014 CLKCON5 User clock gating control register 0x0040 RW
0x40028018 CLKSTAT0 Clocking status 0x0000 RW
CLOCKING ARCHITECTURE OPERATION
At power-up, the processor executes at 80 MHz, sourced from the 80 MHz PLL output. The clock source for the 80 MHz PLL is the
internal 16 MHz oscillator by default. User code can select the clock source for the system clock and can divide the clock by a factor of 1
to 128, where the clock divider bits are controlled by CLKCON1[2:0]. Slower code execution and reduced power consumption result.
Note that P1.0 must be configured as a clock input before the clock source is switched in the clock control register.
When changing from one clock source to a different clock source, the user code must ensure that both clock sources are kept active for a
minimum of five clock cycles to ensure that the clock switching is fully completed without any glitches.
If the clock source for the 80 MHz SPLL needs to be changed from the internal 16 MHz oscillator to the external HFXTAL, observe the
following procedure:
1. Check that HFXTAL is stable by reading CLKSTAT0[14:12].
2. Change the system clock to the internal 16 MHz oscillator using CLKCON0[1:0].
3. Wait 5 × 16 MHz clock cycles.
4. Switch the input to the SPLL using CLKCON0[11].
5. Wait until the SPLL has locked by monitoring CLKSTAT0[2:0].
6. Change the system clock back to the SPLL clock.
ADuCM320 Hardware Reference Manual UG-498
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REGISTER DETAILS: CLOCK ARCHITECTURE
Misc Clock Settings Register
Address: 0x40028000, Reset: 0x0041, Name: CLKCON0
Table 5. Bit Descriptions for CLKCON0
Bits Bit Name Description Reset Access
15 HFXTALIE High frequency crystal interrupt enable. 0x0 RW
0: an interrupt to the core is not generated on a HFXTAL ok or HFXTAL nok
1: an interrupt to the core is generated on a HFXTAL ok or HFXTAL nok
14 RESERVED Reserved. 0x0 RW
13 SPLLIE SPLL interrupt enable. 0x0 RW
0: SPLL interrupt is not generated
1: SPLL interrupt is generated
12 RESERVED Reserved. 0x0 R
11 PLLMUX PLL source selection. 0x0 RW
0: internal oscillator is selected (HFOSC)
1: external oscillator is selected (HFXTAL)
[10:8] RESERVED Reserved. 0x0 RW
[7:4] CLKOUT GPIO clock out selection. 0x4 RW
0000: UCLK
0001: LFOSC (32 kHz)
0010: HFOSC( 16 MHz)
0100: Core Clock
0101: PCLK
1011: General Purpose Timer0 clock
1100: Wake-up timer clock
1110: HFXTAL
All other combinations are reserved
[3:2] RESERVED Reserved. 0x0 R
[1:0] CLKMUX Clock Selection 0x1 RW
00: high frequency internal oscillator (HFOSC)
01: SPLL is selected (80 MHz)
10: reserved
11: external GPIO port is selected (ECLKIN)
UG-498 ADuCM320 Hardware Reference Manual
Rev. C | Page 14 of 196
Clock Dividers Register
Address: 0x40028004, Reset: 0x0200, Name: CLKCON1
Table 6. Bit Descriptions for CLKCON1
Bits Bit Name Description Reset Access
[15:12] RESERVED Reserved. 0x0 R
11 CDD2DCLK D2DCLK divide bits. 0x0 R
0: D2D_CLK frequency = HCLK frequency.
1: D2D_CLK frequency = half of HCLK frequency.
[10:8] CDPCLK PCLK divide bits. PCLK divide bits. 0x2 RW
000: reserved.
001: reserved.
010: DIV4. Divide by 4 (PCLK is quarter the frequency of root clock,
20 MHz). All ADC specifications are based on this setting. Using any other
setting may affect ADC performance.
011: DIV8. Divide by 8.
100: DIV16. Divide by 16.
101: DIV32. Divide by 32.
110: DIV64. Divide by 164.
111: DIV128. Divide by 128.
[7:3] RESERVED Reserved. Always returns 0 when read. 0x0 R
[2:0] CDHCLK HCLK divide bits. 0x0 RW
000: DIV1. Divide by 1 (HCLK is equal to root clock).
001: DIV2. Divide by 2 (HCLK is half the frequency of root clock).
010: DIV4. Divide by 4 (HCLK is quarter the frequency of root clock).
011: DIV8. Divide by 8.
100: DIV16.Divide by 16.
101: DIV32.Divide by 32.
110: DIV64.Divide by 64.
111: DIV128. Divide by 128.
User Clock Gating Control Register
Address: 0x40028014, Reset: 0x0040, Name: CLKCON5
The user clock gating control register (CLKCON5) is used to control the gates of the peripheral UCLKs.
Table 7. Bit Descriptions for CLKCON5
Bits Bit Name Description Reset Access
[15:7] RESERVED Reserved. Always returns 0 when read. 0x0 R
6
RESERVED
Reserved. Always set to 1.
0x1
RW
5 UCLKUARTOFF UART clock user control. This bit disables the UCLK_UART clock. It controls
the gate on UCLK_UART in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK_UART is always off and this bit has no effect.
0x0 RW
0: clock on
1: clock off
4 UCLKI2C1OFF I2C1 clock user control. This bit disables the PCLK_I2C1 clock. It controls
the gate on PCLK_I2C1 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the I2C1 PCLK is always off and this bit has no effect.
0x0 RW
0: clock on
1: clock off
3 UCLKI2C0OFF I2C0 clock user control. This bit disables the PCLK_I2C0 clock. It controls
the gate on PCLK_I2C0 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3 the PCLK_I2C0 is always off and this bit has no effect.
0x0 RW
0: clock on
1: clock off
2 RESERVED Reserved. 0x0 R
ADuCM320 Hardware Reference Manual UG-498
Rev. C | Page 15 of 196
Bits Bit Name Description Reset Access
1 UCLKSPI1OFF SPI1 clock user control. This bit disables the UCLK_SPI1 clock. It controls
the gate on UCLK_SPI1 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3 the UCLK_SPI1 is always off and this bit has no effect.
0x0 RW
0: clock on
1: clock off
0 UCLKSPI0OFF SPI0 clock user control. This bit disables the UCLK_SPI0 clock. It controls
the gate on UCLK_SPI0 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK_SPI0 is always off and this bit has no effect.
0x0 RW
0: clock on
1: clock off
Clocking Status Register
Address: 0x40028018, Reset: 0x0000, Name: CLKSTAT0
The clock status register is used to monitor PLL and oscillator status.
Table 8. Bit Descriptions for CLKSTAT0
Bits Bit Name Description Reset Access
15 RESERVED Reserved. Always returns 0 when read. 0x0 R
14 HFXTALNOK HF crystal not stable. This bit is sticky. It is used to interrupt the core when interrupts are enabled.
Write a 1 to this location to clear it.
0x0 RW
0: HF crystal stable signal has not been deasserted.
1: HF crystal stable signal has been deasserted.
13 HFXTALOK HF crystal stable. This bit is sticky. It is used to interrupt the core when interrupts are enabled.
Write a 1 to this location to clear it.
0x0 RW
0: HF crystal stable signal has not been asserted.
1: HF crystal stable signal has been asserted.
12 HFXTALSTATUS HF crystal status. 0x0 R
0: HF crystal is not stable or not enabled.
1: HF crystal is stable.
[11:3] RESERVED Reserved. 0x0 R
2 SPLLUNLOCK
System PLL unlock. This bit is sticky. SPLLUNLOCK is set when the PLL loses its lock.
SPLLUNLOCK is used as the interrupt source to signal the core that a lock was lost. Writing a 1
to this bit clears it. SPLLUNLOCK does not set again unless the system PLL gains a lock and
subsequently loses it again.
0x0 RW
0: no loss of PLL lock was detected.
1: a PLL loss of lock was detected.
1 SPLLLOCK System PLL lock. This bit is sticky. SPLLLOCK is set when the PLL locks. SPLLLOCK is used as the
interrupt source to signal the core that a lock was detected. Writing a 1 to this bit clears it.
SPLLLOCK does not set again unless the system PLL loses lock and subsequently locks again.
0x0 RW
0: no PLL lock event was detected.
1: a PLL lock event was detected.
0 SPLLSTATUS
System PLL status. Indicates the current status of the PLL. Initially the system PLL is unlocked.
After a stabilization period, the PLL locks and is ready for use as the system clock source. This is
a read only bit. A write has no effect.
0x0 R
0: the PLL is not locked or not properly configured. The PLL is not ready for use as the system
clock source.
1: the PLL is locked and is ready for use as the system clock source.
UG-498 ADuCM320 Hardware Reference Manual
Rev. C | Page 16 of 196
POWER MANAGEMENT UNIT
POWER MANAGEMENT UNIT FEATURES
The power management unit (PMU) controls the different power modes of the ADuCM320.
Four power modes are available:
•Active
•CORE_SLEEP
•SYS_SLEEP
•Hibernate
POWER MANAGEMENT UNIT OVERVIEW
The Cortex-M3 sleep modes are linked to the PMU modes and are described in this section. The PMU is in the always-on section. Each
mode gives a power reduction benefit with a corresponding reduction in functionality.
POWER MANAGEMENT UNIT OPERATION
The debug tools can prevent the Cortex-M3 from fully entering its power saving modes by setting bits in the debug logic. Only a power-on reset
resets the debug logic. Therefore, the device should be power cycled after using serial wire debug with application code containing the
WFI instruction.
Power Mode: Active Mode, Mode 0
The system is fully active. Memories and all user enabled peripherals are clocked, and the Cortex-M3 processor is executing instructions.
Note that the Cortex-M3 processor manages its internal clocks and can be in a partial clock gated state. This clock gating affects only the
internal Cortex-M3 processing core. Automatic clock gating is used on all blocks and is transparent to the user. User code can use a WFI
command to put the Cortex-M3 processor into sleep mode; it is independent of the power mode settings of the PMU.
When the ADuCM320 wakes up from any of the low power modes, the device return to Mode 0.
Power Mode: CORE_SLEEP Mode, Mode 1
In CORE_SLEEP mode, the system gates the clock to the Cortex-M3 core after the Cortex-M3 has entered SLEEP mode. The rest of the
system remains active. No instructions can be executed; however, DMA transfers can continue to occur between peripherals and
memories. The Cortex-M3 processor FCLK is active, and the device wakes up using the NVIC.
Power Mode: SYS_SLEEP Mode, Mode 2
In SYS_SLEEP mode, the system gates HCLK (system bus clock) and PCLK (peripheral bus clock) after the Cortex-M3 has entered sleep
mode. The gating of these clocks stops all AHB attached masters/slaves and all peripherals attached to APB. Peripheral clocks are all off,
and they are no longer user programmable. The NVIC (interrupt controller) clock (FCLK) remains active, and the NVIC processes wake-
up events.
Power Mode: Hibernate Mode, Mode 3
In hibernate mode, the system disables power to all combinational logic and places sequential logic in retain mode. Because FCLK is
stopped, the number of sources capable of waking up the system is restricted. The sources listed in Table 55 are the only sources able to
wake up the system.
Power Mode 1 to Power Mode 3 should be entered when the processor is not in an interrupt handler. If Power Mode 1 to Power Mode 3 is
entered when the processor is in an interrupt handler, the power-down mode can be exited only by a reset or a higher priority interrupt source.
ADuCM320 Hardware Reference Manual UG-498
Rev. C | Page 17 of 196
CODE EXAMPLES
Code Example to Enter Power Saving Modes
SCB->SCR = 0x04; // sleepdeep mode
pADI_PWRCTL->PWRKEY = 0x4859; // key1
pADI_PWRCTL->PWRKEY = 0xF27B; // key2
pADI_PWRCTL->PWRMOD = 0x3; // Hibernate
__DSB();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__WFI();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
Code Example to Achieve Further Power Savings
pADI_ADC->ADCCON = 0; // Power off the ADC
pADI_IDAC0->IDACCON = 0x1; // Turn off IDAC0
pADI_IDAC1->IDACCON = 0x1; // Turn off IDAC1
pADI_IDAC2->IDACCON = 0x1; // Turn off IDAC2
pADI_IDAC3->IDACCON = 0x1; // Turn off IDAC3
pADI_VDAC0->DACCON = 0x100; // Turn off VDAC0
pADI_VDAC1->DACCON = 0x100; // Turn off VDAC1
pADI_VDAC2->DACCON = 0x100; // Turn off VDAC2
pADI_VDAC3->DACCON = 0x100; // Turn off VDAC3
pADI_VDAC4->DACCON = 0x100; // Turn off VDAC4
pADI_VDAC5->DACCON = 0x100; // Turn off VDAC5
pADI_VDAC6->DACCON = 0x100; // Turn off VDAC6
pADI_VDAC7->DACCON = 0x100; // Turn off VDAC7
pADI_CLKCTL->CLKCON0 &= 0xFFFC; // Switch to 16MHz clock
pADI_CLKCTL->CLKCON1 = 0x505; // Slow down system clocks
pADI_CLKCTL->CLKCON5 = 0x7B; // Turn off clocks to peripherals
UG-498 ADuCM320 Hardware Reference Manual
Rev. C | Page 18 of 196
REGISTER SUMMARY: POWER MANAGEMENT UNIT
Table 9. Power Management Register Summary
Address Name Description Reset RW
0x40002400
PWRMOD
Power modes
0x0000
RW
0x40002404 PWRKEY Key protection for PWRMOD 0x0000 RW
REGISTER DETAILS: POWER MANAGEMENT UNIT
Power Modes Register
Address: 0x40002400, Reset: 0x0000, Name: PWRMOD
Table 10. Bit Descriptions for PWRMOD
Bits Bit Name Description Reset Access
[14:2] RESERVED Reserved. These bits should be written 0 by user code. 0x0 R
[1:0] PWRMOD Power modes control bits. When read, these bits contain the last power
mode value entered by user code.
0x0 RW
Note that, to place the Cortex in sleepdeep mode for hibernate, the
Cortex-M3 system control register (Address 0xE000ED10) must be
configured to 0x4 or 0x06.
00: active mode
01: CORE_SLEEP mode
10: SYS_SLEEP mode
11: hibernate mode
Key Protection for PWRMOD Register
Address: 0x40002404, Reset: 0x0000, Name: PWRKEY
Table 11. Bit Descriptions for PWRKEY
Bits Bit Name Description Reset Access
[15:0] PWRKEY Power control key register. The PWRMOD register is key-protected. Two
writes to the key are necessary to change the value in the PWRMOD
register: first 0x4859, then 0xF27B. The PWRMOD register should then be
written. A write to any other register before writing to PWRMOD returns
the protection to the lock state.
0x0 RW
ADuCM320 Hardware Reference Manual UG-498
Rev. C | Page 19 of 196
ARM CORTEX-M3 PROCESSOR
ARM CORTEX-M3 PROCESSOR FEATURES
High Performance
•1.25 DMIPS/MHz.
•Many instructions, including multiply, are single cycle.
•Separate data and instruction buses allow simultaneous data and instruction accesses to be performed.
•Optimized for single-cycle flash usage.
Low Power
•Low standby current.
•Core implemented using advanced clock gating so that only the actively used logic consumes dynamic power.
•Power-saving mode support (sleep and deep sleep modes). The design has separate clocks to allow unused parts of the processor to
be stopped.
Advanced Interrupt Handling
•The nested vectored interrupt controller (NVIC) supports up to 240 interrupts. The ADuCM320 supports 49 of these interrupts. The
vectored interrupt feature greatly reduces interrupt latency because there is no need for software to determine which interrupt handler
to serve. In addition, there is no need to have software to set up nested interrupt support.
•The ARM Cortex-M3 processor automatically pushes registers onto the stack at the entry interrupt and retrieves them at the exit
interrupt. This reduces interrupt handling latency and allows interrupt handlers to be normal C functions.
•Dynamic priority control for each interrupt.
•Latency reduction using late arrival interrupt acceptance and tail-chain interrupt entr y.
•Immediate execution of a nonmaskable interrupt request for safety critical applications.
System Features
•Support for bit-band operation and unaligned data access.
•Advanced fault handling features include various exception types and fault status registers.
Debug Support
•Serial wire debug interfaces (SW-DP).
•Flash patch and breakpoint (FPB) unit for implementing breakpoints. Limited to two hardware breakpoints.
•Data watchpoint and trigger (DWT) unit for implementing watchpoints trigger resources and system profiling. Limited to one
hardware watchpoint. The DWT does not support data matching for watchpoint generation because it only has one comparator.
ARM CORTEX-M3 PROCESSOR OVERVIEW
The ADuCM320 contains an embedded ARM Cortex-M3 processor, Revision r2p1. The ARM Cortex-M3 processor provides a high
performance, low cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low
power consumption while delivering outstanding computational performance and exceptional system response to interrupts.
ARM CORTEX-M3 PROCESSOR OPERATION
Several ARM Cortex-M3 processor components are flexible in their implementation. This section details the actual implementation of
these components in the ADuCM320.
Serial Wire Debug (SW/JTAG-DP)
The ADuCM320 only supports the serial wire interface via the SWCLK and SWDIO pins. It does not support the 5-wire JTAG interface.
ROM Table
The ADuCM320 implements the default ROM table.
UG-498 ADuCM320 Hardware Reference Manual
Rev. C | Page 20 of 196
Nested Vectored Interrupt Controller Interrupts (NVIC)
The ARM Cortex-M3 processor includes a nested vectored interrupt controller (NVIC), which offers several features:
•Nested interrupt support
•Vectored interrupt support
•Dynamic priority changes support
•Interrupt masking
In addition, the NVIC has a nonmaskable interrupt (NMI) input.
The NVIC is implemented on the ADuCM320, and more details are available in the System Exceptions and Peripheral Interrupts section.
Wake-Up Interrupt Controller (WIC)
The ADuCM320 has a modified WIC, which provides the lowest possible power-down current. This feature is transparent to the user and
more details are available in the Power Management Unit section. It is not recommended to enter a power saving mode while servicing an
interrupt. However, if the part does enter a power saving mode while servicing an interrupt, it can be woken up by only a higher priority
interrupt source.
μDMA
The ADuCM320 implements the ARM μDMA. More details are available in the DMA Controller section.
ARM CORTEX-M3 PROCESSOR RELATED DOCUMENTS
•Cortex-M3 Revision r2p1 Technical Reference Manual (DDI 0337)
•ARM Processor Cortex-M3 (AT420) and Cortex-M3 with ETM AT425): Errata Notice
•ARMv7-M Architecture Reference Manual (DDI 0403)
•ARMv7-M Architecture Reference Manual Errata Markup
•ARM Debug Interface v5 Architecture Specification (IHI 0031)
•PrimeCell µDMA Controller (PL230) Technical Reference Manual Revision r0p0 (DDI 0417)
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