Analog Devices AD9273 User manual

Octal LNA/VGA/AAF/ADC
and Crosspoint Switch
AD9273
Rev. B
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FEATURES
8 channels of LNA, VGA, AAF, and ADC
Low noise preamplifier (LNA)
Input-referred noise voltage = 1.26 nV/√Hz
(gain = 21.3 dB) @ 5 MHz typical
SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB
Single-ended input; VIN maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output = 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range = −42 dB to 0 dB
SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable 2nd-order low-pass filter (LPF) from
8 MHz to 18 MHz
Programmable high-pass filter (HPF)
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 50 MSPS
SNR = 70 dB
SFDR = 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
Includes an 8 × 8 differential crosspoint switch to support
continuous wave (CW) Doppler
Low power, 109 mW per channel at 12 bits/40 MSPS (TGC)
70 mW per channel in CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode, <2 μs
100-lead TQFP and 144-ball BGA
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
GENERAL DESCRIPTION
The AD9273 is designed for low cost, low power, small size, and
ease of use. It contains eight channels of a low noise preamplifier
(LNA) with a variable gain amplifier (VGA); an antialiasing
filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-
digital converter (ADC).
Each channel features a variable gain range of 42 dB, a fully
differential signal path, an active input preamplifier termination, a
maximum gain of up to 52 dB, and an ADC with a conversion
rate of up to 50 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
FUNCTIONAL BLOCK DIAGRAM
SERIAL
PORT
INTERFACE
REFERENCE
FCO+
FCO–
DCO+
DCO–
LNA
LO-H
LOSW-H
LI-H
LG-H 12-BIT
ADC SERIAL
LVDS DOUTH+
DOUTH–
LNA
LO-G
LOSW-G
LI-G
LG-G 12-BIT
ADC SERIAL
LVDS DOUTG+
DOUTG–
LNA
LO-F
LOSW-F
LI-F
LG-F 12-BIT
ADC SERIAL
LVDS DOUTF+
DOUTF–
LNA
LO-E
LOSW-E
LI-E
LG-E 12-BIT
ADC SERIAL
LVDS DOUTE+
DOUTE–
LNA
LO-D
LOSW-D
LI-D
LG-D 12-BIT
ADC SERIAL
LVDS DOUTD+
DOUTD–
LNA
LO-C
LOSW-C
LI-C
LG-C 12-BIT
ADC SERIAL
LVDS DOUTC+
DOUTC–
LNA
LO-B
LOSW-B
LI-B
LG-B 12-BIT
ADC SERIAL
LVDS DOUTB+
DOUTB–
LNA
LO-A
LOSW-A
LI-A
LG-A 12-BIT
ADC SERIAL
LVDS DOUTA+
DOUTA–
AVDD1 AVDD2 STBY DRVDD PDWN
CLK–
CLK+
SDIO
SCLK
CSB
RBIAS
VREF
GAIN+
GAIN–
CWD[7:0]+
AND
CWD[7:0]–
SWITCH
ARRAY
DATA
RATE
MULTIPLIER
AAF
AAF
AAF
AAF
AAF
AAF
AAF
AAF
AD9273
VGA
VGA
VGA
VGA
VGA
VGA
VGA
VGA
07030-001
Figure 1.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input-referred noise voltage is typically
1.26 nV/√Hz at a gain of 21.3 dB, and the combined input-referred
noise voltage of the entire channel is 1.42 nV/√Hz at typical
gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB
LNA gain, the input SNR is about 91 dB. In CW Doppler mode,
the LNA output drives a transconductance amp that is switched
through an 8 × 8 differential crosspoint switch. The switch is
programmable through the SPI.

AD9273* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
•AD9273 Evaluation Board
DOCUMENTATION
Application Notes
•AN-1142: Techniques for High Speed ADC PCB Layout
•AN-586: LVDS Outputs for High Speed A/D Converters
•AN-737: How ADIsimADC Models an ADC
•AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
•AN-835: Understanding High Speed ADC Testing and
Evaluation
•AN-877: Interfacing to High Speed ADCs via SPI
•AN-878: High Speed ADC SPI Control Software
•AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
•AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
•AD9273: Octal LNA/VGA/AAF/ADC and Crosspoint Switch
Data Sheet
SOFTWARE AND SYSTEMS REQUIREMENTS
•UG-001: Evaluation Board User Guide
TOOLS AND SIMULATIONS
•Visual Analog
•AD9273 IBIS Models
REFERENCE MATERIALS
Press
• Industry’s First Octal Ultrasound Receiver with Digital I/Q
Demodulator and Decimation Filter Reduces Processor
Overhead in Ultrasound Systems
•Low Cost, Octal Ultrasound Receiver with On-Chip RF
Decimator and JESD204B Serial Interface
Technical Articles
•MS-2210: Designing Power Supplies for High Speed ADC
•New Components Offer Fexibility in Ultrasound System
Design
•Processors for Ultrasound Improve Image Quality
DESIGN RESOURCES
•AD9273 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
View all AD9273 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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AD9273
Rev. B | Page 2 of 48
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications..................................................................................... 4
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 8
Switching Specifications .............................................................. 9
ADC Timing Diagrams ................................................................. 10
Absolute Maximum Ratings.......................................................... 11
Thermal Impedance................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 15
Equivalent Circuits......................................................................... 19
Theory of Operation ...................................................................... 21
Ultrasound .................................................................................. 21
Channel Overview ..................................................................... 22
Input Overdrive.......................................................................... 25
CW Doppler Operation............................................................. 25
TGC Operation........................................................................... 27
ADC ............................................................................................. 31
Clock Input Considerations...................................................... 31
Serial Port Interface (SPI).............................................................. 38
Hardware Interface..................................................................... 38
Memory Map .................................................................................. 40
Reading the Memory Map Table.............................................. 40
Reserved Locations .................................................................... 40
Default Values............................................................................. 40
Logic Levels................................................................................. 40
Outline Dimensions....................................................................... 44
Ordering Guide .......................................................................... 45
REVISION HISTORY
7/09—Rev. A to Rev. B
Added BGA Package ..........................................................Universal
Changes to Features and General Description Sections.............. 1
Changes to Product Highlights Section......................................... 3
Changes to Full-Channel (TGC) Characteristics Parameter,
Table 1 ............................................................................................ 4
Changes to Gain Control Interface Parameter and to CW
Doppler Mode Parameter, Table 1.............................................. 6
Change to Wake-Up Time (Standby), GAIN+ = 0.8 V
Parameter....................................................................................... 9
Changes to Figure 2 and Figure 3................................................. 10
Changes to Table 4.......................................................................... 11
Addded Figure 5; Renumbered Sequentially.............................. 12
Changes to Table 6.......................................................................... 13
Changes to Figure 34 and Figure 35............................................. 20
Changes to Ultrasound Section.................................................... 21
Changes to Low Noise Amplifier (LNA) Section....................... 22
Changes to Active Impedance Matching Section and
Figure 40...................................................................................... 23
Changes to LNA Noise Section .................................................... 24
Changes to Input Overload Protection Section and Figure 44.......25
Changes to Figure 48...................................................................... 28
Changes to Figure 49 and Figure 50............................................. 29
Changes to Clock Input Considerations Section and to
Figure 56 to Figure 59................................................................ 31
Changes to Digital Outputs and Timing Section....................... 33
Changes to CSB Pin Section ......................................................... 36
Changes to Reading the Memory Map Table Section ............... 40
Updated Outline Dimensions....................................................... 44
Changes to Ordering Guide.......................................................... 45
4/09—Revision A: Initial Version

AD9273
Rev. B | Page 3 of 48
The AD9273 requires a LVPECL-/CMOS-/LVDS-compatible
sample rate clock for full performance operation. No external
reference or driver components are required for many
applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO±) for
capturing data on the output and a frame clock (FCO±) trigger
for signaling a new output byte are provided.
Powering down individual channels is supported to increase
battery life for portable applications. There is also a standby
mode option that allows quick power-up for power cycling. In
CW Doppler operation, the VGA, AAF, and ADC are powered
down. The power of the time gain control (TGC) path scales
with selectable speed grades.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable clock, data
alignment, and programmable digital test pattern generation. The
digital test patterns include built-in fixed patterns, built-in
pseudorandom patterns, and custom user-defined test patterns
entered via the serial port interface.
Fabricated in an advanced CMOS process, the AD9273 is
available in a 16 mm × 16 mm, RoHS compliant, 100-lead
TQFP or a 144-ball BGA. It is specified over the industrial
temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight channels are contained in a small,
space-saving package. A full TGC path, ADC, and crosspoint
switch contained within a 100-lead, 16 mm × 16 mm TQFP or
a 144-ball BGA.
2. Low Power of 109 mW per Channel at 40 MSPS.
3. Integrated Crosspoint Switch. This switch allows numerous
multichannel configuration options to enable the CW
Doppler mode.
4. Ease of Use. A data clock output (DCO±) operates up to
300 MHz and supports double data rate (DDR) operation.
5. User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
6. Integrated Second-Order Antialiasing Filter. This filter is
placed between the VGA and the ADC and is programmable
from 8 MHz to 18 MHz.

AD9273
Rev. B | Page 4 of 48
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS= 50 Ω, LNA gain = 21.3 dB, LNA bias =mid-
high (default), PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = fSAMPLE/3 (default), HPF = LPF cutoff/20.7 (default), full temperature,
ANSI-644 LVDS mode, unless otherwise noted.
Table 1.
AD9273-25 AD9273-40 AD9273-50
Parameter1Conditions Min Typ Max Min Typ Max Min Typ Max Unit
LNA CHARACTERISTICS
Gain Single-ended
input to
differential
output
15.6/17.9/21.3 15.6/17.9/21.3 15.6/17.9/21.3 dB
Single-ended
input to
single-ended
output
9.6/11.9/15.3 9.6/11.9/15.3 9.6/11.9/15.3 dB
Input Voltage Range LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
LNA output
limited to
4.4 V p-p
differential
output
733/550/367 733/550/367 733/550/367 mV p-p
SE2
Input Common
Mode
0.9 0.9 0.9 V
Input Resistance RFB = 250 Ω 50 50 50 Ω
R
FB = 500 Ω 100 100 100 Ω
R
FB = ∞ 15 15 15 kΩ
Input Capacitance LI-x 22 22 22 pF
−3 dB Bandwidth 70 70 70 MHz
Input-Referred
Noise Voltage
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RS= 0 Ω,
RFB = ∞
1.6/1.42/1.26 1.6/1.42/1.26 1.6/1.42/1.26 nV/√Hz
Input Noise Current RFB = ∞ 1 1 1 pA/√Hz
1 dB Input Com-
pression Point
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
GAIN+ = 0 V
1.0/0.8/0.5 1.0/0.8/0.5 1.0/0.8/0.5 mV p-p
Noise Figure LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
Active Termina-
tion Matched
RS= 50 Ω,
RFB = 200 Ω/
250 Ω/350 Ω
5.8/5.1/4.3 5.8/5.1/4.3 5.8/5.1/4.3 dB
Unterminated RFB = ∞ 6.3/5.3/4.4 6.3/5.3/4.4 6.3/5.3/4.4 dB
FULL-CHANNEL (TGC)
CHARACTERISTICS
AAF Low-Pass Filter
Cutoff
In range, −3 dB,
programmable
8 to 18 8 to 18 8 to 18 MHz
Out of range,3
−3 dB, pro-
grammable,
>>AAF band-
width tolerance
5 to 8, 18 to 35 5 to 8, 18 to 35 5 to 8, 18 to 35 MHz

AD9273
Rev. B | Page 5 of 48
AD9273-25 AD9273-40 AD9273-50
Parameter1Conditions Min Typ Max Min Typ Max Min Typ Max Unit
AAF Bandwidth
Tolerance
In range ±10 ±10 ±10 %
Group Delay
Variation
f = 1 MHz to
18 MHz,
GAIN+ = 0 V to
1.6 V
±2 ±2 ±2 ns
Input-Referred
Noise Voltage
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RFB = ∞
1.94/1.64/1.38 1.94/1.64/1.38 1.94/1.64/1.38 nV/√Hz
Noise Figure LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
Active Termina-
tion Matched
RS= 50 Ω,
RFB = 200 Ω/
250 Ω/350 Ω
10.3/8.7/6.8 10.3/8.6/6.7 10.3/8.6/6.7 dB
Unterminated RFB = ∞ 7.1/6.0/4.8 7.1/5.9/4.8 7.1/5.9/4.8 dB
Correlated Noise
Ratio
No signal,
correlated/
uncorrelated
−30 −30 −30 dB
Output Offset −35 +35 −35 +35 −35 +35 LSB
Signal-to-Noise
Ratio (SNR)
fIN = 5 MHz at
−10 dBFS,
GAIN+ = 0 V
65.5 64 63.5 dBFS
f
IN = 5 MHz at
−1 dBFS,
GAIN+ = 1.6 V
58.5 57 56.5 dBFS
Harmonic Distortion
Second
Harmonic
fIN = 5 MHz at
−10 dBFS,
GAIN+ = 0 V
−55 −52 −52 dBc
f
IN = 5 MHz at
−1 dBFS,
GAIN+ = 1.6 V
−67 −62 −58 dBc
Third Harmonic fIN = 5 MHz at
−10 dBFS,
GAIN+ = 0 V
−56 −50 −47 dBc
f
IN = 5 MHz at
−1 dBFS,
GAIN+ = 1.6 V
−61 −56 −55 dBc
Two-Tone IMD3
(2 × F1 − F2)
Distortion
fIN1 = 5.0 MHz at
−1 dBFS,
fIN2 = 5.01 MHz
at −21 dBFS,
GAIN+ = 1.6 V,
LNA gain =
21.3 dB
−75 −75 −75 dBc
Channel-to-Channel
Crosstalk
fIN1 = 5.0 MHz at
−1 dBFS
−70 −70 −70 dB
Overrange
condition4−65 −65 −65 dB
Channel-to-Channel
Delay Variation
Full TGC path,
fIN = 5 MHz,
GAIN+ = 0 V to
1.6 V
0.3 0.3 0.3 Degrees
PGA GAIN Differential
input to
differential
output
21/24/27/30 21/24/27/30 21/24/27/30 dB

AD9273
Rev. B | Page 6 of 48
AD9273-25 AD9273-40 AD9273-50
Parameter1Conditions Min Typ Max Min Typ Max Min Typ Max Unit
GAIN ACCURACY 25°C
Gain Law Confor-
mance Error
0 V < GAIN+
< 0.16 V
1.5 1.5 1.5 dB
0.16 V < GAIN+
< 1.44 V
−1.6 +1.6 −1.6 +1.6 −1.7 +1.7 dB
1.44 V < GAIN+
< 1.6 V
−2.5 −2.5 −2.5 dB
Linear Gain Error GAIN+ = 0.8 V,
normalized for
ideal AAF loss
−1.6 +1.6 −1.6 +1.6 −1.7 +1.7 dB
Channel-to-Channel
Matching
0.16 V < GAIN+
< 1.44 V
0.1 0.1 0.1 dB
GAIN CONTROL
INTERFACE
Normal Operating
Range
0 1.6 0 1.6 0 1.6 V
Gain Range GAIN+ =
0 V to 1.6 V
42 42 42 dB
Scale Factor 28 28 28 dB/V
Response Time 42 dB change 750 750 750 ns
Gain+ Impedance Single ended 10 10 10 MΩ
Gain− Impedance Single ended 70 70 70 kΩ
CW DOPPLER MODE
Transconductance Differential,
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
5.4/7.3/10.9 5.4/7.3/10.9 5.4/7.3/10.9 mA/V
Output Level Range Differential,
CW Doppler
output pins
1.5 3.6 1.5 3.6 1.5 3.6 V
Input-Referred
Noise Voltage
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RS= 0 Ω,
RFB = ∞,
RL= 675 Ω
2.6/2.1/1.6 2.6/2.1/1.6 2.6/2.1/1.6 nV/√Hz
Input-Referred
Dynamic Range
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RS= 0 Ω,
RFB = ∞
160/159/158 160/159/158 160/159/158 dBFS/√Hz
Two-Tone IMD3
(2 × F1 − F2)
Distortion
fIN1 = 5.0 MHz at
−1 dBFS (FS at
LNA input), fIN2 =
5.01 MHz at
−21 dBFS (FS at
LNA input), LNA
gain = 21.3 dB
−70 −70 −70 dBc
Output DC Bias Single ended,
per channel
2.4 2.4 2.4 mA
Maximum Output
Swing
Single ended,
per channel
±2 ±2 ±2 mA p-p
POWER SUPPLY
AVDD1 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
AVDD2 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
IAVDD1 Full-channel
mode
158 186 223 mA
CW Doppler
mode with four
channels
enabled
32 32 32 mA

AD9273
Rev. B | Page 7 of 48
AD9273-25 AD9273-40 AD9273-50
Parameter1Conditions Min Typ Max Min Typ Max Min Typ Max Unit
IAVDD2 Full-channel
mode
150 150 150 mA
CW Doppler
mode with four
channels
enabled
70 70 70 mA
IDRVDD 47 49 50 mA
Total Power
Dissipation
Includes output
drivers, full-
channel mode,
no signal
819 940 873 996 943 1072 mW
CW Doppler
mode with four
channels
enabled
275 275 275 mW
Power-Down
Dissipation
5 5 5 mW
Standby Power
Dissipation
148 158 170 mW
Power Supply
Rejection Ratio
(PSRR)
1.6 1.6 1.6 mV/V
ADC RESOLUTION 12 12 12 Bits
ADC REFERENCE
Output Voltage Error VREF = 1 V ±20 ±20 ±20 mV
Load Regulation At 1.0 mA,
VREF = 1 V
2 2 2 mV
Input Resistance 6 6 6 kΩ
1See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2SE = single ended.
3AAF settings < 5 MHz are out of range and are not supported.
4The overrange condition is specified as being 6 dB more than the full-scale input range.

AD9273
Rev. B | Page 8 of 48
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 2.
Parameter1Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 1.5 pF
LOGIC INPUTS (PDWN, STBY, SCLK)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (SDIO)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 V
Logic 0 Voltage Full 0 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 A) Full 1.79 V
Logic 0 Voltage (IOL = 50 A) Full 0.05 V
DIGITAL OUTPUTS (DOUTx+, DOUTx−) IN ANSI-644 MODE1
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 V
Output Coding (Default) Offset binary
DIGITAL OUTPUTS (DOUTx+, DOUTx−) WITH
LOW POWER, REDUCED-SIGNAL OPTION1
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 150 250 mV
Output Offset Voltage (VOS) Full 1.10 1.30 V
Output Coding (Default) Offset binary
1See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2Specified for LVDS and LVPECL only.
3Specified for 13 SDIO pins sharing the same connection.

AD9273
Rev. B | Page 9 of 48
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 3.
Parameter1Temp Min Typ Max Unit
CLOCK2
Clock Rate Full 10 50 MSPS
Clock Pulse Width High (tEH) Full 10 ns
Clock Pulse Width Low (tEL) Full 10 ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD) Full (tSAMPLE/2) + 1.5 (tSAMPLE/2) + 2.3 (tSAMPLE/2) + 3.1 ns
Rise Time (tR) (20% to 80%) Full 300 ps
Fall Time (tF) (20% to 80%) Full 300 ps
FCO± Propagation Delay (tFCO) Full (tSAMPLE/2) + 1.5 (tSAMPLE/2) + 2.3 (tSAMPLE/2) + 3.1 ns
DCO± Propagation Delay (tCPD)4 Full tFCO + (tSAMPLE/24) ns
DCO± to Data Delay (tDATA)4 Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps
DCO± to FCO± Delay (tFRAME)4 Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps
Data-to-Data Skew
(tDATA-MAX − tDATA-MIN)
Full ±100 ±350
ps
Wake-Up Time (Standby), GAIN+ = 0.8 V 25°C <2 µs
Wake-Up Time (Power-Down) 25°C 1 ms
Pipeline Latency Full 8 Clock cycles
APERTURE
Aperture Uncertainty (Jitter) 25°C <1 ps rms
1See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2Can be adjusted via the SPI.
3Measurements were made using a part soldered to FR-4 material.
4tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

AD9273
Rev. B | Page 10 of 48
ADC TIMING DIAGRAMS
DCO–
DCO+
DOUTx–
DOUTx+
FCO–
FCO+
AIN
CLK–
CLK+
MSB
N – 8 D10 N – 8 D9 N – 8 D8 N – 8 D7 N – 8 D6 N – 8 D5 N – 8 D4 N – 8 D3 N – 8 D2 N – 8 D1 N – 8 D0 N – 8 D10 N – 7
MSB
N – 7
N – 1
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
EL
07030-002
Figure 2. 12-Bit Data Serial Stream (Default)
DCO–
DCO+
DOUTx–
DOUTx+
FCO–
FCO+
AIN
CLK–
CLK+
D0
(LSB) D1 N – 8 D2 N – 8 D3 N – 8 D4 N – 8 D5 N – 8 D6 N – 8 D7 N – 8 D8 N – 8 D9 N – 8 D10 N – 8 D11 (MSB)
N – 1
N
tDATA
tFRAME
tFCO
tPD
tCPD
tEH tEL
07030-004
Figure 3. 12-Bit Data Serial Stream, LSB First

AD9273
Rev. B | Page 11 of 48
ABSOLUTE MAXIMUM RATINGS
Table 4. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
With
Respect To Rating
Electrical
AVDD1 GND −0.3 V to +2.0 V
AVDD2 GND −0.3 V to +3.9 V
DRVDD GND −0.3 V to +2.0 V
GND GND −0.3 V to +0.3 V
AVDD2 AVDD1 −2.0 V to +3.9 V
AVDD2 DRVDD −2.0 V to +3.9 V
AVDD1 DRVDD −2.0 V to +2.0 V
Digital Outputs
(DOUTx+, DOUTx−,
DCO+, DCO−,
FCO+, FCO−)
GND −0.3 V to +2.0 V
CLK+, CLK−, GAIN+,
GAIN−
GND −0.3 V to +3.9 V
LI-x, LO-x, LOSW-x LG-x −0.3 V to +2.0 V
CWDx−, CWDx+ GND −0.3 V to +3.9 V
PDWN, STBY, SCLK, CSB GND −0.3 V to +3.9 V
RBIAS, VREF, SDIO GND −0.3 V to +2.0 V
Environmental
Operating Temperature
Range (Ambient)
−40°C to +85°C
Storage Temperature
Range (Ambient)
−65°C to +150°C
Maximum Junction
Temperature
150°C
Lead Temperature
(Soldering, 10 sec)
300°C
THERMAL IMPEDANCE
Table 5.
Airflow Velocity (m/sec) θJA1θ
JB θJC Unit
0.0 20.3 N/A N/A °C/W
1.0 14.4 7.6 4.7 °C/W
2.5 12.9 N/A N/A °C/W
1θJA is for a 4-layer PCB with a solid ground plane (simulated). The exposed
pad is soldered to the PCB.
ESD CAUTION

AD9273
Rev. B | Page 12 of 48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LI-F
LG-F
LO-F
LI-G
LG-G
LO-G
AVDD1
CLK–
NOTES
1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND.
CLK+
AVDD2
AVDD1
AVDD1
AVDD1
LI-E
LG-E
AVDD2
AVDD2
LI-H
LG-H
LO-H
AVDD2
AVDD1
LOSW-F
LOSW-G
LOSW-H
AD9273
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
AVDD1
74
75
PDWN
73
STBY
72
DRVDD
71
DOUTA+
70
DOUTA–
69
DOUTB+
68
DOUTB–
67
DOUTC+
66
DOUTC–
65
DOUTD+
64
DOUTD–
63
FCO+
62
FCO–
61
DCO+
60
DCO–
59
DOUTE+
58
DOUTE–
57
DOUTF+
56
DOUTF–
55
DOUTG+
54
DOUTG–
53
DOUTH+
52
DOUTH–
51
DRVDD
AVDD1
LI-A
LG-A
LOSW-A
LI-B
LG-B
LO-B
AVDD1
SDIO
SCLK
CSB
AVDD2
AVDD2
LI-C
LG-C
LO-C
AVDD1
AVDD2
LI-D
LG-D
AVDD1
AVDD2
LO-A
LOSW-B
LOSW-C
LOSW-
D
LO-D CWD0– CWD0+ CWD1– CWD1+ CWD2– CWD2+ CWD3– CWD3+ AVDD2 GAIN– GAIN+ VREF RBIAS CWD5– CWD5+ CWD4– CWD4+ CWD6– CWD6+ CWD7– CWD7+ LO-E LOSW-E
07030-005
Figure 4. TQFP Pin Configuration
07030-300
A
B
C
D
E
F
G
J
H
K
L
M
2610 12
48
1357 11
9
TOP VIEW
(Not to Scale)
Figure 5. BGA Pin Configuration

AD9273
Rev. B | Page 13 of 48
Table 6. Pin Function Descriptions
Pin No.
TQFP BGA Name Description
0 N/A GND Ground (the exposed paddle should be tied to a quiet analog ground)
N/A B5, B6, B8, C5,
C6, C7, C8, D5,
D6, D7, D8, E1,
E5, E6, E7, E8,
E12, F2, F4, F6,
F7, F9, F11, G1,
G3, G5, G6, G7,
G8, G10, G12,
H2, H3, H4, H5,
H6, H7, H8, H9,
H10, H11, J2,
K1, K2, M1, M12
GND Ground
4, 10, 16, 22,
25, 50, 54, 60,
66, 72
F1, F3, F5, F8,
F10, F12, G2,
G4, G9, G11
AVDD1 1.8 V Analog Supply
3, 9, 15, 21, 55,
61, 67, 73, 86
B7, E2, E3, E4,
E9, E10, E11
AVDD2 3.0 V Analog Supply
26, 47 L1, L12 DRVDD 1.8 V Digital Output Driver Supply
1 A1 LI-E LNA Analog Input for Channel E
2 B1 LG-E LNA Ground for Channel E
5 C2 LO-F LNA Analog Inverted Output for Channel F
6 D2 LOSW-F LNA Analog Switched Output for Channel F
7 A2 LI-F LNA Analog Input for Channel F
8 B2 LG-F LNA Ground for Channel F
11 C3 LO-G LNA Analog Inverted Output for Channel G
12 D3 LOSW-G LNA Analog Switched Output for Channel G
13 A3 LI-G LNA Analog Input for Channel G
14 B3 LG-G LNA Ground for Channel G
17 C4 LO-H LNA Analog Inverted Output for Channel H
18 D4 LOSW-H LNA Analog Switched Output for Channel H
19 A4 LI-H LNA Analog Input for Channel H
20 B4 LG-H LNA Ground for Channel H
23 H1 CLK− Clock Input Complement
24 J1 CLK+ Clock Input True
27 M2 DOUTH− ADC H Digital Output Complement
28 L2 DOUTH+ ADC H Digital Output True
29 M3 DOUTG− ADC G Digital Output Complement
30 L3 DOUTG+ ADC G Digital Output True
31 M4 DOUTF− ADC F Digital Output Complement
32 L4 DOUTF+ ADC F Digital Output True
33 M5 DOUTE− ADC E Digital Output Complement
34 L5 DOUTE+ ADC E Digital Output True
35 M6 DCO− Digital Clock Output Complement
36 L6 DCO+ Digital Clock Output True
37 M7 FCO− Frame Clock Digital Output Complement
38 L7 FCO+ Frame Clock Digital Output True
39 M8 DOUTD− ADC D Digital Output Complement
40 L8 DOUTD+ ADC D Digital Output True
41 M9 DOUTC− ADC C Digital Output Complement
42 L9 DOUTC+ ADC C Digital Output True
43 M10 DOUTB− ADC B Digital Output Complement
44 L10 DOUTB+ ADC B Digital Output True

AD9273
Rev. B | Page 14 of 48
Pin No.
TQFP BGA Name Description
45 M11 DOUTA− ADC A Digital Output Complement
46 L11 DOUTA+ ADC A Digital Output True
48 K11 STBY Standby Power-Down
49 J11 PDWN Full Power-Down
51 K12 SCLK Serial Clock
52 J12 SDIO Serial Data Input/Output
53 H12 CSB Chip Select Bar
56 B9 LG-A LNA Ground for Channel A
57 A9 LI-A LNA Analog Input for Channel A
58 D9 LOSW-A LNA Analog Switched Output for Channel A
59 C9 LO-A LNA Analog Inverted Output for Channel A
62 B10 LG-B LNA Ground for Channel B
63 A10 LI-B LNA Analog Input for Channel B
64 D10 LOSW-B LNA Analog Switched Output for Channel B
65 C10 LO-B LNA Analog Inverted Output for Channel B
68 B11 LG-C LNA Ground for Channel C
69 A11 LI-C LNA Analog Input for Channel C
70 D11 LOSW-C LNA Analog Switched Output for Channel C
71 C11 LO-C LNA Analog Inverted Output for Channel C
74 B12 LG-D LNA Ground for Channel D
75 A12 LI-D LNA Analog Input for Channel D
76 D12 LOSW-D LNA Analog Switched Output for Channel D
77 C12 LO-D LNA Analog Inverted Output for Channel D
78 K10 CWD0− CW Doppler Output Complement for Channel 0
79 J10 CWD0+ CW Doppler Output True for Channel 0
80 K9 CWD1− CW Doppler Output Complement for Channel 1
81 J9 CWD1+ CW Doppler Output True for Channel 1
82 K8 CWD2− CW Doppler Output Complement for Channel 2
83 J8 CWD2+ CW Doppler Output True for Channel 2
84 K7 CWD3− CW Doppler Output Complement for Channel 3
85 J7 CWD3+ CW Doppler Output True for Channel 3
87 A8 GAIN− Gain Control Voltage Input Complement
88 A7 GAIN+ Gain Control Voltage Input True
89 A6 RBIAS External Resistor to Set the Internal ADC Core Bias Current
90 A5 VREF Voltage Reference Input/Output
91 K6 CWD4− CW Doppler Output Complement for Channel 4
92 J6 CWD4+ CW Doppler Output True for Channel 4
93 K5 CWD5− CW Doppler Output Complement for Channel 5
94 J5 CWD5+ CW Doppler Output True for Channel 5
95 K4 CWD6− CW Doppler Output Complement for Channel 6
96 J4 CWD6+ CW Doppler Output True for Channel 6
97 K3 CWD7− CW Doppler Output Complement for Channel 7
98 J3 CWD7+ CW Doppler Output True for Channel 7
99 C1 LO-E LNA Analog Inverted Output for Channel E
100 D1 LOSW-E LNA Analog Switched Output for Channel E

AD9273
Rev. B | Page 15 of 48
TYPICAL PERFORMANCE CHARACTERISTICS
fSAMPLE = 40 MSPS, fIN = 5 MHz, RS= 50 Ω, LNA gain = 21.3 dB, LNA bias = mid-high, PGA gain = 24 dB, AAF LPF cutoff = fSAMPLE/3,
HPF = LPF cutoff/20.7 (default), GAIN− = 0.8 V
–2.0
–1.5
–0.5
–1.0
0
0.5
1.0
1.5
2.0
0 0.2 0.4 0.6 0.8 1.0
GAIN+ (V)
GAIN ERROR (dB)
1.2 1.4 1.6
+85°C
+25°C
–40°C
07030-114
Figure 6. Gain Error vs. GAIN+ at Three Temperatures
20
18
16
14
12
10
8
6
4
2
0
–1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
PERCENTAGE OF UNITS (%)
GAIN ERROR (dB)
07030-184
Figure 7. Gain Error Histogram, GAIN+ = 0.16 V
0
2
4
6
10
8
12
14
–1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
PERCENTAGE OF UNITS (%)
GAIN ERROR (dB)
07030-185
Figure 8. Gain Error Histogram, GAIN+ = 0.8 V
0
2
4
6
10
8
12
14
–1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
PERCENTAGE OF UNITS (%)
GAIN ERROR (dB)
07030-186
Figure 9. Gain Error Histogram, GAIN+ = 1.44 V
0
5
10
15
20
25
–1.25 –1.00 –0.75
PERCENTAGE OF UNITS (%)
–0.50 –0.25 0
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
0.25 0.50 0.75 1.00 1.25
07030-180
Figure 10. Gain Match Histogram, GAIN+ = 0.3 V
5
0
10
15
20
25
–1.25 –1.00 –0.75
PERCENTAGE OF UNITS (%)
–0.50 –0.25 0
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
0.25 0.50 0.75 1.00 1.25
07030-181
Figure 11. Gain Match Histogram, GAIN+ = 1.3 V

AD9273
Rev. B | Page 16 of 48
–7 –6 –5 –4
500k
450k
400k
350k
300k
250k
200k
150k
100k
50k
0–3–2–101234567
NUMBER OF HITS
CODES
07030-115
Figure 12. Output-Referred Noise Histogram, GAIN+ = 0.0 V
–7 –6 –5 –4
200k
180k
160k
140k
120k
100k
80k
60k
40k
20k
0–3–2–101234567
NUMBER OF HITS
CODES
07030-116
Figure 13. Output-Referred Noise Histogram, GAIN+ = 1.6 V
3.0
2.5
2.0
1.5
1.0
0.5
012345678910
INPUT-REFERRED NOISE (nV/
√
Hz)
FREQUENCY (MHz)
LNA GAIN = 21.3dB
LNA GAIN = 15.6dB
LNA GAIN = 17.9dB
07030-187
Figure 14. Short-Circuit, Input-Referred Noise vs. Frequency,
PGA Gain = 30 dB, GAIN+ = 1.6 V
–
128
–129
–130
–131
–132
–133
–134
–135
–136
–137
–138
–139 00.20.40.60.8
GAIN+ (V) 1.0 1.2 1.4 1.6
OUTPUT-REFERRED NOISE (dBFS/Hz)
LNA GAIN = 12×
LNA GAIN = 6×
07030-117
LNA GAIN = 8×
Figure 15. Short-Circuit, Output-Referred Noise vs. GAIN+
40
45
50
55
60
65
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
SNR/SIN
A
D(dBFS)
GAIN+ (V)
SINAD
SNR
07030-118
Figure 16. SNR/SINAD vs. GAIN+, AIN = −1.0 dBFS
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20 0 5 10 15 20 25
AMPLITUDE (dBFS)
FREQUENCY (MHz)
07030-120
25MSPS
40MSPS
50MSPS
Figure 17. Antialiasing Filter (AAF) Pass-Band Response,
LPF Cutoff = 1 × (1/3) × fSAMPLE

AD9273
Rev. B | Page 17 of 48
0
25
50
75
100
125
150
0 5 10 15 20 25 30 35 40
GROUP DELAY (ns)
FREQUENCY (MHz)
GAIN+ = 1.6V
GAIN+ = 0.8V
GAIN+ = 0V
07030-121
Figure 18. Antialiasing Filter (AAF) Group Delay Response
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 2 4 6 8 10 12 14 16
SECOND-ORDER H
A
RMONIC DISTORTION (dBFS)
INPUT FREQUENCY (MHz)
GAIN+ = 1.6V
GAIN+ = 1.0V
GAIN+ = 0.5V
07030-122
Figure 19. Second-Order Harmonic Distortion vs. Input Frequency,
AIN = −1.0 dBFS
–80
–70
–60
–50
–40
–30
–20
–10
0
0246810121416
THIRD-ORDER HARMONIC DISTORTION (dBFS)
INPUT FREQUENCY (MHz)
GAIN+ = 1.6V
GAIN+ = 1.0V
GAIN+ = 0.5V
07030-123
Figure 20. Third-Order Harmonic Distortion vs. Input Frequency,
AIN = −1.0 dBFS
–120
–100
–80
–60
–40
–20
0
–40 –35 –30 –25 –20 –15 –10 –5 0
SECOND-ORDER HARMONIC DISTORTION (dBFS)
ADC OUTPUT LEVEL (dBFS)
GAIN+ = 1.6V
GAIN+ = 0.8V
GAIN+ = 0V
07030-124
Figure 21. Second-Order Harmonic Distortion vs. ADC Output Level
–120
–100
–80
–60
–40
–20
0
–40 –35 –30 –25 –20 –15 –10 –5 0
THIRD-ORDER HARMONIC DISTORTION (dBFS)
ADC OUTPUT LEVEL (dBFS)
GAIN+ = 1.6V
GAIN+ = 0.8V
GAIN+ = 0V
07030-125
Figure 22. Third-Order Harmonic Distortion vs. ADC Output Level
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.5 0.6 0.7 0.9 1.1 1.3 1.50.8 1.0 1.2 1.4 1.6
IMD3 (dBFS)
GAIN+ (V)
f
IN1
= f
IN2
+0.01MHz
A
IN
1 = –1dBFS, A
IN
2 = –21dBFS
07030-126
8MHz
5MHz
2.3MHz
Figure 23. IMD3 vs. GAIN+

AD9273
Rev. B | Page 18 of 48
–120
–100
–80
–60
–40
–20
0
–40 –35 –30 –25 –20 –15 –10 –5 0
IMD3 (dBFS)
FUND1 LEVEL (dBFS)
GAIN+ = 1.6V
GAIN+ = 0.8V
GAIN+ = 0V
fIN1 = 5.00MHz, fIN2 = 5.01MHz
FUND2 LEVEL = FUND1 LEVEL – 20dB
0
7030-127
Figure 24. IMD3 vs. Fundamental 1 Amplitude (FUND1) Level

AD9273
Rev. B | Page 19 of 48
EQUIVALENT CIRCUITS
LI-x,
LG-x
AVDDx
15kΩ
V
CM
07030-073
Figure 25. Equivalent LNA Input Circuit
LO-x,
LOSW-x 10Ω
AVDDx
07030-075
Figure 26. Equivalent LNA Output Circuit
10Ω
10kΩ
10kΩ
CLK– 10Ω
1.25V
CLK+
07030-007
Figure 27. Equivalent Clock Input Circuit
S
DIO 350Ω
30kΩ
A
VDDx
07030-008
Figure 28. Equivalent SDIO Input Circuit
DR
V
DD
DRGND
DOUTx– DOUTx+
V
V
V
V
07030-009
Figure 29. Equivalent Digital Output Circuit
SCLK, PDWN,
OR STBY 30kΩ
1kΩ
07030-010
Figure 30. Equivalent SCLK, PDWN, or STBY Input Circuit