ARM Versatile Express Juno r2 Product manual

ARM® Versatile™ Express Juno r2
Development Platform (V2M-Juno r2)
Technical Reference Manual
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.
ARM 100114_0200_03_en

ARM® Versatile™ Express Juno r2 Development Platform (V2M-Juno r2)
Technical Reference Manual
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.
Release Information
Document History
Issue Date Confidentiality Change
0200-00 16 November 2015 Non-Confidential First issue of TRM
0200-01 15 July 2016 Non-Confidential Second issue of TRM
0200-02 10 January 2017 Non-Confidential Third issue of TRM
0200-03 10 April 2017 Non-Confidential Fourth issue of TRM
Non-Confidential Proprietary Notice
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Copyright © 2015–2017, ARM Limited or its affiliates. All rights reserved.
ARM Limited. Company 02557590 registered in England.
110 Fulbourn Road, Cambridge, England CB1 9NJ.
LES-PRE-20349
ARM® Versatile™ Express Juno r2 Development Platform (V2M-Juno r2)
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 2
Non-Confidential

Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in
accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.
Unrestricted Access is an ARM internal classification.
Product Status
The information in this document is Final, that is for a developed product.
Web Address
http://www.arm.com
Conformance Notices
Federal Communications Commission Notice
This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).
CE Declaration of Conformity
The system should be powered down when not in use.
It is recommended that ESD precautions be taken when handling Versatile™ Express boards.
The motherboard generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio
communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful
interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try
to correct the interference by one or more of the following measures:
• Ensure attached cables do not lie across the target board
• Reorient the receiving antenna
• Increase the distance between the equipment and the receiver
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected
• Consult the dealer or an experienced radio/TV technician for help
Note
It is recommended that wherever possible shielded interface cables be used.
ARM® Versatile™ Express Juno r2 Development Platform (V2M-Juno r2)
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 3
Non-Confidential

Contents
ARM® Versatile™ Express Juno r2 Development
Platform (V2M-Juno r2) Technical Reference Manual
Preface
About this book ...................................................... ...................................................... 7
Feedback .................................................................................................................... 10
Chapter 1 Introduction
1.1 Precautions .............................................................................................................. 1-12
1.2 About the Versatile™ Express Juno r2 Development Platform ................ ................ 1-13
1.3 Location of components on the V2M-Juno r2 motherboard .................. .................. 1-15
1.4 Connectors on front and rear panels ................................... ................................... 1-16
Chapter 2 Hardware Description
2.1 Overview of V2M-Juno r2 motherboard hardware ......................... ......................... 2-18
2.2 Juno r2 ARM Development Platform SoC ............................... ............................... 2-22
2.3 External power .................................................... .................................................... 2-25
2.4 Power management and temperature protection .................................................... 2-26
2.5 Clocks ...................................................................................................................... 2-28
2.6 Resets .......................................................... .......................................................... 2-35
2.7 Thin Links ................................................................................................................ 2-38
2.8 IOFPGA ......................................................... ......................................................... 2-42
2.9 HDLCD interface .................................................. .................................................. 2-45
2.10 Interrupts ........................................................ ........................................................ 2-47
2.11 USB 2.0 interface .................................................................................................... 2-50
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2.12 SMC 10/100 Ethernet interface ....................................... ....................................... 2-51
2.13 UART interface ........................................................................................................ 2-52
2.14 PCI Express system ................................................................................................ 2-54
2.15 Keyboard and mouse interface ................................................................................ 2-56
2.16 Additional user key entry ............................................ ............................................ 2-57
2.17 Debug and trace ...................................................................................................... 2-59
Chapter 3 Configuration
3.1 Overview of the V2M-Juno r2 motherboard configuration system ............. ............. 3-63
3.2 Configuration process and operating modes ............................. ............................. 3-65
3.3 Configuration files .................................................................................................... 3-70
3.4 Configuration switches .............................................. .............................................. 3-75
3.5 Use of reset push buttons ........................................................................................ 3-77
3.6 Command-line interface ............................................. ............................................. 3-78
Chapter 4 Programmers Model
4.1 About this programmers model ....................................... ....................................... 4-82
4.2 V2M-Juno r2 motherboard memory maps ............................... ............................... 4-83
4.3 APB system registers .............................................................................................. 4-89
4.4 APB system configuration registers ................................... ................................... 4-103
4.5 APB energy meter registers ......................................... ......................................... 4-107
Appendix A Signal Descriptions
A.1 Debug connectors ........................................................................................ Appx-A-122
A.2 Configuration 10Mbps Ethernet and dual-USB connector ............. ............. Appx-A-126
A.3 PCI Express Gigabit Ethernet and dual-USB connector .............................. Appx-A-127
A.4 SMC 10/100 Ethernet connector ................................ ................................ Appx-A-128
A.5 Configuration USB connector ...................................................................... Appx-A-129
A.6 Header connectors ...................................................................................... Appx-A-130
A.7 Keyboard and Mouse Interface (KMI) connector .................... .................... Appx-A-131
A.8 HDMI connectors ............................................ ............................................ Appx-A-132
A.9 PCI Express expansion slots ................................... ................................... Appx-A-133
A.10 SATA 2.0 connectors ......................................... ......................................... Appx-A-141
A.11 Dual-UART connector .................................................................................. Appx-A-143
A.12 Secure keyboard and user push buttons connector .................................... Appx-A-145
A.13 ATX power connector ......................................... ......................................... Appx-A-146
Appendix B Specifications
B.1 Electrical specification ........................................ ........................................ Appx-B-148
Appendix C Revisions
C.1 Revisions .................................................. .................................................. Appx-C-150
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 5
Non-Confidential

Preface
This preface introduces the ARM® Versatile™ Express Juno r2 Development Platform (V2M-Juno r2)
Technical Reference Manual.
It contains the following:
•About this book on page 7.
•Feedback on page 10.
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 6
Non-Confidential

About this book
This book describes the ARM® Versatile™ Express Juno r2 Development Platform, that is, the V2M-Juno
r2 motherboard. This development board contains the Juno r2 Development Platform SoC.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2,
where:
rmIdentifies the major revision of the product, for example, r1.
pnIdentifies the minor revision or modification status of the product, for example, p2.
Intended audience
This book is written for experienced hardware and software developers to aid ARMv8-A software and
tooling development in the Juno r2 ARM Development Platform SoC using the V2M-Juno r2
motherboard.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
This chapter introduces the Versatile™ Express V2M-Juno r2 motherboard.
Chapter 2 Hardware Description
This chapter describes the Versatile Express V2M-Juno r2 motherboard hardware.
Chapter 3 Configuration
This chapter describes the powerup and configuration process of the Versatile Express V2M-Juno
r2 motherboard.
Chapter 4 Programmers Model
This chapter describes the programmers model of the Versatile Express V2M-Juno r2
motherboard.
Appendix A Signal Descriptions
This appendix describes the signals present at the interface connectors of the Versatile Express
V2M-Juno r2 motherboard.
Appendix B Specifications
This appendix contains the electrical specifications of the Versatile Express V2M-Juno r2
motherboard.
Appendix C Revisions
This appendix describes the technical changes between released issues of this book.
Glossary
The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those
terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning
differs from the generally accepted meaning.
See the ARM Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
Preface
About this book
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 7
Non-Confidential

monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the
ARM Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded
area at that time. The actual level is unimportant and does not affect normal operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Figure 1 Key to timing diagram conventions
Signals
The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Lowercase n
At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This book contains information that is specific to this product. See the following documents for other
relevant information.
Preface
About this book
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 8
Non-Confidential

ARM publications
•Juno ARM® Development Platform SoC Technical Reference Manual (Revision r2p0) (ARM
DDI 0515).
•Juno ARM® Development Platform SoC Technical Overview (Revision r2p0) (ARM DTO
0038)
•AN415 Example Express 20MG design for a V2M-Juno Motherboard (ARM DAI 0415).
•ARM® LogicTile Express 3MG Technical Reference Manual (ARM DUI 0449).
•ARM® LogicTile Express 13MG Technical Reference Manual (ARM DUI 0556).
•ARM® LogicTile Express 20MG Technical Reference Manual (ARM DDI 0498).
•ARM® CoreLink™ TLX-400 Network Interconnect Thin Links Supplement to ARM® CoreLink™
NIC-400 Network Interconnect Technical Reference Manual (ARM DSU 0028).
•ARM® PrimeCell Technical Reference Manual Real Time Clock (PL031) (ARM DDI 0224).
•ARM® PrimeCell PS2 Keyboard/Mouse Interface (PL050) (ARM DDI 0143).
•ARM® PrimeCell General Purpose Input/Output (PLO61)Technical Reference Manual
(ARM DUI 0142).
•ARM® PrimeCell Multimedia Card Interface (PL180)Technical Reference Manual
(ARM DDI 0172).
•ARM® Dual-Timer Module (SP804) Technical Reference Manual (ARM DDI 0271).
•ARM® Watchdog Module (SP805) Technical Reference Manual (ARM DDI 0270).
•CoreLink SMC-35x Static Memory Controller Series Technical Reference Manual
(ARM DDI 0380).
•AMBA® 3 AHB-Lite Protocol Specification v1.0 (ARM IHI 0033).
•AMBA® 3 APB Protocol Specification v1.0 (ARM IHI 000024).
•ARM® DS-5 Setting up the ARM DSTREAM Hardware (ARM DUI 0481).
•ARM® DS-5 Using the Debug Hardware Configuration Utilities (ARM DUI 0498).
•CoreSight™ Components Technical Reference Manual (ARM DDI 0314).
•CoreSight™ Trace Memory Controller Technical Reference Manual (ARM DDI 0461).
Other publications
• See the Linaro website http://www.linaro.org/downloads/ for Linaro software.
Preface
About this book
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 9
Non-Confidential

Feedback
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
• The product name.
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms and diagnostic
procedures if appropriate.
Feedback on content
If you have comments on content then send an e-mail to [email protected]. Give:
• The title ARM Versatile Express Juno r2 Development Platform (V2M-Juno r2) Technical Reference
Manual.
• The number ARM 100114_0200_03_en.
• If applicable, the page number(s) to which your comments refer.
• A concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.
Note
ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the
represented document when used with any other PDF reader.
Preface
Feedback
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 10
Non-Confidential

Chapter 1
Introduction
This chapter introduces the Versatile™ Express V2M-Juno r2 motherboard.
It contains the following sections:
•1.1 Precautions on page 1-12.
•1.2 About the Versatile™ Express Juno r2 Development Platform on page 1-13.
•1.3 Location of components on the V2M-Juno r2 motherboard on page 1-15.
•1.4 Connectors on front and rear panels on page 1-16.
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 1-11
Non-Confidential

1.1 Precautions
You can take certain precautions to ensure safety and to prevent damage to your V2M-Juno r2
motherboard.
This section contains the following subsections:
•1.1.1 Ensuring safety on page 1-12.
•1.1.2 Preventing damage on page 1-12.
1.1.1 Ensuring safety
An on-board connector supplies 12V DC to the V2M-Juno r2 motherboard.
Warning
Do not use the V2M-Juno r2 motherboard near equipment that is sensistive to electromagnetic emissions,
for example, medical equipment.
1.1.2 Preventing damage
The V2M-Juno r2 motherboard is intended for use within a laboratory or engineering development
environment. It is supplied with an enclosure that leaves the board sensitive to electrostatic discharges
and permits electromagnetic emissions.
Caution
To avoid damage to the V2M-Juno r2 motherboard, observe the following precautions:
• Connect the external power supply to the board before powerup to prevent damage.
• Never subject the board to high electrostatic potentials. Observe Electrostatic discharge (ESD)
precautions when handling any board.
• Always wear a grounding strap when handling the board.
• Only hold the board by the edges.
• Avoid touching the component pins or any other metallic element.
• Do not use the board near a transmitter of electromagnetic emissions.
1 Introduction
1.1 Precautions
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1.2 About the Versatile™ Express Juno r2 Development Platform
The Juno r2 Development Platform, that is, the V2M-Juno r2 motherboard, is a development
motherboard that provides access to the Juno r2 ARM Development Platform SoC. This is a
development chip that supports ARMv8-A software tooling, evaluation, and development.
The V2M-Juno r2 motherboard provides the following:
Juno r2 ARM Development Platform SoC (Juno r2 SoC)
The Juno r2 SoC provides a fully coherent dual-core Cortex®-A72 cluster, a fully coherent
quad-core Cortex-A53 cluster, and an I/O-coherent Mali™-T624 quad-core GPU cluster.
Dual-core Cortex-A72 cluster:
2MB L2 cache.
NEON™ and FPU.
Underdrive: Maximum operating frequency: 600MHz.
Nominal drive: Maximum operating frequency: 1GHz.
Overdrive: Maximum operating frequency: 1.2GHz.
Quad-core Cortex-A53 cluster:
1MB L2 cache.
NEON and FPU.
Underdrive: Maximum operating frequency: 450MHz.
Nominal drive: Maximum operating frequency: 800MHz.
Overdrive: Maximum operating frequency: 950MHz.
Quad-core Mali-T624 cluster:
1MB L2 cache.
NEON and FPU.
Underdrive: Maximum operating frequency: 450MHz.
Nominal drive: Maximum operating frequency: 600MHz.
Overdrive: Not supported.
Separate power domains support power management through Dynamic Voltage and Frequency
Scaling (DVFS) of the Cortex-A72 and Cortex-A53 clusters, and the Mali-T624 GPU cluster.
Note
See the Juno ARM® Development Platform SoC Technical Reference Manual (Revision r2p0) for
more information on the Juno r2 SoC.
LogicTile site
The V2M-Juno r2 motherboard provides two headers that enable you to fit a Versatile Express
LogicTile daughterboard. A Thin Links TLX-400 Network Interconnect connects the
motherboard and daughterboard.
Powerup and configuration system
An on-board EEPROM stores board and file identification information and a microSD card
stores software images and configuration files. You can access the microSD card to perform
configuration file editing and to update software images.
Configuration of the V2M-Juno r2 motherboard and the LogicTile daughterboard, if fitted,
proceeds automatically under the control of the Motherboard Configuration Controller (MCC)
after powerup or reset.
You can customize the clock speeds and other configuration settings.
1 Introduction
1.2 About the Versatile™ Express Juno r2 Development Platform
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IOFPGA
The IOFPGA provides low-bandwidth peripherals that the Juno r2 SoC does not provide. The
IOFPGA connects to the Juno r2 SoC through a 32-bit Static Memory Bus (SMB) with
dedicated chip selects.
The IOPFGA also contains energy meters, consisting of dedicated registers, that form part of the
power control and DVFS system.
External user memory
8GB on-board DDR3L 800MHz connects to memory interfaces in the Juno r2 SoC. 64MB NOR
flash connects to the IOFPGA. The IOFPGA contains 256KB of user RAM.
Access ports
The V2M-Juno r2 motherboard provides access through a general-purpose dual-UART, Static
Memory Controller (SMC) 10/100 Ethernet port, four USB 2.0 ports, keyboard and mouse ports,
Gen 2 PCI Express with four expansion slots, a Gigabit Ethernet port, and two SATA ports. The
GbE port and SATA ports access the test chip through the PCI Express switch.
Video and audio output
The V2M-Juno r2 motherboard provides dual HDMI outputs. The Juno r2 SoC sends two
independent 24-bit RGB video channels to the HDMI transmitters. Both HDMI ports share the
same single I2S audio from the Juno r2 SoC.
Additional user key entry
The V2M-Juno r2 motherboard supports trusted keyboard entry and additional key entry to
simulate hand-held devices.
User LEDs
The V2M-Juno r2 motherboard provides eight user LEDs that connect to the IOFPGA. The
meaning of each LED depends on the software that you implement in the Juno r2 SoC.
System LEDs
The V2M-Juno r2 motherboard provides LEDs that denote the status of the board power
supplies. They also indicate the status of the read and write access to the configuration microSD
card through the configuration USB port or configuration Ethernet port.
Debug
The V2M-Juno r2 motherboard supports P-JTAG processor debug that enables connection of
DSTREAM, or a compatible third-party debugger. The board also supports 32-bit trace.
1 Introduction
1.2 About the Versatile™ Express Juno r2 Development Platform
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Non-Confidential

1.3 Location of components on the V2M-Juno r2 motherboard
The following figure shows the physical layout of the upper face of the V2M-Juno r2 motherboard.
PCIe
switch Juno r2 ARM
Development
Platform
SoC
J1 HDRX
J2 HDRY
IOFPGA
RL PW V+
NU HM V-
TRACEA-SINGLE
TRACEB DUAL
P-JTAG
Reserved
for ARM use
only
ATX
power
connector
DDR3L
User
microSD
card
Configuration
microSD
card
Reserved
for ARM use
only
MCC
Reserved
for ARM use
only
SATA 2.0 0
SATA 2.0 1
Hardware
Reset
ON/OFF/Soft
Reset
Configuration
USB
HDMI0
HDMI1
GbE +
dual-USB
Configuration
10Mbps
Ethernet +
dual-USB
Keyboard
and mouse
Secure
keyboard
and user push
button connector
Dual
UART
PCIe slots
Slot3
Slot2 Slot1
Slot0
User
LEDs
USER0
USER7
System
LEDS
ON1
ON2
DBG_USB
SB_5V
5V
3V3
Power
LEDs
3V
coin
battery
User
push
buttons
Configuration
switches
SW1 SW0
SMC
Ethernet
Figure 1-1 V2M-Juno r2 motherboard layout, upper face
1 Introduction
1.3 Location of components on the V2M-Juno r2 motherboard
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Non-Confidential

1.4 Connectors on front and rear panels
The following figure shows the front panel of the case.
SMC
10/100
Ethernet
Figure 1-2 Front panel
The following figure shows the rear panel of the case.
PS/2
mouse
PS/2
Keyboard
Port 1
Port 2
Configuration
Ethernet 10Mbps
Port 3
Port 4
USB 2.0 ports
Secure
keyboard and
user push
button connector
P-JTAG Gigabit
Ethernet
HDMI 1
HDMI 0
UART 0
SW0 SW1
Configuration
switches
Configuration
USB
Hardware
Reset
ON/OFF
Soft Reset
12V DC
UART 1
Figure 1-3 Rear panel
1 Introduction
1.4 Connectors on front and rear panels
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 1-16
Non-Confidential

Chapter 2
Hardware Description
This chapter describes the Versatile Express V2M-Juno r2 motherboard hardware.
It contains the following sections:
•2.1 Overview of V2M-Juno r2 motherboard hardware on page 2-18.
•2.2 Juno r2 ARM Development Platform SoC on page 2-22.
•2.3 External power on page 2-25.
•2.4 Power management and temperature protection on page 2-26.
•2.5 Clocks on page 2-28.
•2.6 Resets on page 2-35.
•2.7 Thin Links on page 2-38.
•2.8 IOFPGA on page 2-42.
•2.9 HDLCD interface on page 2-45.
•2.10 Interrupts on page 2-47.
•2.11 USB 2.0 interface on page 2-50.
•2.12 SMC 10/100 Ethernet interface on page 2-51.
•2.13 UART interface on page 2-52.
•2.14 PCI Express system on page 2-54.
•2.15 Keyboard and mouse interface on page 2-56.
•2.16 Additional user key entry on page 2-57.
•2.17 Debug and trace on page 2-59.
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2.1 Overview of V2M-Juno r2 motherboard hardware
The hardware infrastructure of the V2M-Juno r2 motherboard supports ARMv8-A software evaluation
and tooling development using the Juno r2 SoC.
The following figure shows the hardware infrastructure of the V2M-Juno r2 motherboard.
2 Hardware Description
2.1 Overview of V2M-Juno r2 motherboard hardware
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Non-Confidential

LogicTile Express
FPGA daughterboard
HDRX
Versatile Express
V2M-Juno r2 motherboard
HDRX
HDRY
Gen 2 PCIe
switch
FPGA
PCI
Express
slots
Configuration
USB
Juno r2 ARM
Development Platform SoC
Configuration
microSD
Motherboard
Configuration Controller
(MCC)
HDRY
Thin Links
Thin Links
Daughterboard
Configuration
Controller
CB
Configuartion
EEPROM
System
LEDs
User
switches
IOFPGA
SMC
x4x4
x8
x16
PCIe
SATA 0 SATA 1
SATA
x1
x1
x4
x4
x1
x4
GbE
controller
Ethernet
x1
DMC-400
DDR3L DDR3L
32-bit 32-bit
Clock
generators
USB 2.0
4-port hub
PHY
USB 2.0
USB 2.0 USB 2.0 USB 2.0 USB 2.0
UART 1
UART 0
UART
HDMI 0
HDLCD 0 HDMI PHY
HDMI 1
HDLCD 1 HDMI PHY
SCC
I2S
audio
P-JTAG
Trace
I2C
UART SEL I2C
PCIe
I2C
Configuration
Ethernet
Configuartion
EEPROM
Keyboard
Mouse
SPI
Secure
keyboard and
user push
buttons
User push
buttons
SPI
SB
UART
SEL
Reset
push
buttons I2C
I2C
User
microSD
NOR flash
User LEDs
Thin
Links
AXI
Thin
Links
AXI
10/100 Eth LAN
9118
Figure 2-1 V2M-Juno r2 motherboard system architecture with LogicTile FPGA daughterboard
2 Hardware Description
2.1 Overview of V2M-Juno r2 motherboard hardware
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-19
Non-Confidential

The V2M-Juno r2 motherboard contains the following components and interfaces:
• One Juno r2 SoC:
— Dual-core Cortex-A72.
— Quad-core Cortex-A53.
— Quad-core Mali-T624 GPU.
— Memory interfaces, HDLCD display controllers, PCIe root complex, and other on-chip
peripherals.
• Site for LogicTile Express daughterboard:
— Two headers, HDRX and HDRY, enable you to fit any Versatile Express LogicTile daughterboard
in this site.
— Thin Links AXI master and slave interfaces to LogicTile site.
• One Cortex-M3 Motherboard Configuration Controller (MCC) that supports configuration of the
Juno r2 SoC and V2M-Juno r2 motherboard at powerup or reset:
— Clock generator configuration.
— Loading of Real Time Clock (RTC) registers.
— Board configuration.
— Pre-loading of external memory.
• One microSD card that stores the following:
— Board configuration files.
— Software images.
• One EEPROM that stores board identification information and file names for the configuration
system.
• Configuration ports.
The following ports support Drag-and-Drop editing of configuration files in the configuration
microSD card:
— Configuration USB 2.0 port.
— Configuration 10Mbps Ethernet port.
• Two 32-bit 4GB DDR3L on-board memories:
— Low-power.
— 800MHz, 1600 million transfers per second (MTs).
• One PCI Express switch:
— Provides connectivity to the SATA, 1000Base-T (Gbe) Ethernet, and PCIe expansion slots.
— Four PCIe Gen 2 lanes to the Juno r2 SoC.
• Two SATA ports:
— Connects to a Silicon Image Sil3232 SATA controller with a x1 Gen 1 connection to the PCIe
switch.
— Serial ATA Generation 2 transfer rate of 3.0 Gbps.
• Two 4-lane and two 1-lane PCIe Gen 2 expansion slots that connect directly to the PCIe switch.
• One 1000Base-T Ethernet port through PCIe that connects to a Marvell 88E8057-A0-NNB2C000
Gigabit Ethernet controller with a x1 connection to the PCIe switch.
•Static Memory Controller (SMC) 10/100 Ethernet port that uses a LAN9118 Ethernet controller.
• Four USB 2.0 ports, USB 4-port hub and USB PHY.
• Two UARTs:
— UART 0 can connect to the Juno r2 SoC or to the MCC.
— UART 1 can connect to the Juno r2 SoC or to the Daughterboard Configuration Controller on the
LogicTile daughterboard fitted in the daughterboard site.
The board configuration files, that you can edit using the configuration ports, determine the
connectivity of the UART ports during runtime.
Note
The Daughterboard Configuration Controller is a microcontroller on the LogicTile that controls
the configuration of the daughterboard during powerup or reset.
2 Hardware Description
2.1 Overview of V2M-Juno r2 motherboard hardware
ARM 100114_0200_03_en Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-20
Non-Confidential