ARM Cortex-M3 DesignStart User manual

ARM® Cortex®-M3 DesignStart™ Eval
Revision: r0p0
FPGA User Guide
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
ARM 100896_0000_00_en

ARM® Cortex®-M3 DesignStart™ Eval
FPGA User Guide
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
Release Information
Document History
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Product Status
The information in this document is Final, that is for a developed product.
Web Address
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Contents
ARM® Cortex®-M3 DesignStart™ Eval FPGA User
Guide
Preface
About this book ...................................................... ...................................................... 7
Feedback .................................................................................................................... 10
Chapter 1 Introduction
1.1 About Cortex®-M3 DesignStart™ Eval ................................... ................................... 1-12
1.2 About the ARM Versatile Express Cortex-M Prototyping System (V2M-MPS2+) . . 1-14
1.3 Using the documentation ............................................ ............................................ 1-15
1.4 FPGA Evaluation Flow directory structure ............................... ............................... 1-17
1.5 Limitations ....................................................... ....................................................... 1-18
Chapter 2 Using the prebuilt FPGA image
2.1 Setting up the MPS2+ FPGA platform .................................. .................................. 2-20
2.2 Running the self-test program ........................................ ........................................ 2-21
2.3 Connecting to a debugger ........................................... ........................................... 2-23
Chapter 3 FPGA platform overview
3.1 System overview .................................................. .................................................. 3-25
3.2 Memory map ............................................................................................................ 3-26
3.3 Block RAM instances ............................................... ............................................... 3-27
3.4 External Zero Bus Turnaround SSRAM ................................. ................................. 3-28
3.5 External PSRAM ...................................................................................................... 3-29
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3.6 Arduino adapter board .............................................. .............................................. 3-30
3.7 Embedded Trace Macrocell interface ...................................................................... 3-31
3.8 CMSDK APB subsystem ............................................ ............................................ 3-32
3.9 AHB GPIO ....................................................... ....................................................... 3-33
3.10 Serial Peripheral Interface ........................................... ........................................... 3-34
3.11 Color LCD parallel interface .......................................... .......................................... 3-35
3.12 Ethernet ......................................................... ......................................................... 3-36
3.13 VGA ............................................................ ............................................................ 3-37
3.14 Audio I2S ........................................................ ........................................................ 3-38
3.15 Audio configuration .................................................................................................. 3-40
3.16 FPGA system control and I/O .................................................................................. 3-41
Chapter 4 Clocks
4.1 Source clocks .......................................................................................................... 4-43
4.2 Derived clocks .................................................... .................................................... 4-44
Chapter 5 Serial Communication Controller
5.1 SCC interface overview ............................................. ............................................. 5-46
5.2 SCC memory map ................................................. ................................................. 5-47
Chapter 6 FPGA build
6.1 Build flow ........................................................ ........................................................ 6-50
6.2 Build requirements ................................................. ................................................. 6-52
Chapter 7 Integrating with mbed™ OS
7.1 Compatibility with mbed™ OS ......................................... ......................................... 7-54
Chapter 8 Performance and utilization
8.1 Performance and clocks .......................................................................................... 8-56
8.2 Utilization of default system .......................................... .......................................... 8-57
Appendix A Revisions
A.1 Revisions - Cortex®-M3 DesignStart™ Eval .................................................... Appx-A-59
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Preface
This preface introduces the ARM® Cortex®-M3 DesignStart™ Eval FPGA User Guide.
It contains the following:
•About this book on page 7.
•Feedback on page 10.
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About this book
This book describes how to use the FPGA platform in the ARM Versatile™ Express Cortex®-M
Prototyping System to evaluate a design developed using Cortex-M3 DesignStart™ Eval.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2,
where:
rmIdentifies the major revision of the product, for example, r1.
pnIdentifies the minor revision or modification status of the product, for example, p2.
Intended audience
This book is written for hardware engineers, software engineers, system integrators, and system
designers, who might not have previous experience of ARM products, but want to run a complete
example of a working system.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
This chapter introduces Cortex-M3 DesignStart Eval and gives an overview of the FPGA
Evaluation Flow, its directory structure, and limitations.
Chapter 2 Using the prebuilt FPGA image
Cortex-M3 DesignStart Eval includes a prebuilt FPGA image file of the Cortex-M3 DesignStart
Eval example system. This chapter describes how to set up the MPS2+ platform to load the
prebuilt file and run a self-test program.
Chapter 3 FPGA platform overview
This section gives an overview of the FPGA components that are used in Cortex-M3 DesignStart
Eval.
Chapter 4 Clocks
This chapter describes the source and derived clocks for the FPGA design.
Chapter 5 Serial Communication Controller
This chapter describes the Serial Communication Controller (SCC) used in the Cortex-M3
DesignStart Eval FPGA image.
Chapter 6 FPGA build
This chapter describes the steps that are required to build an FPGA bit file from the supplied
source code.
Chapter 7 Integrating with mbed™ OS
This chapter describes the support available for integrating the FPGA system with mbed OS.
Chapter 8 Performance and utilization
This chapter describes the performance, resources, and utilization for the default system of the
FPGA design in Cortex-M3 DesignStart Eval.
Appendix A Revisions
This appendix describes the technical changes between released issues of this book.
Glossary
The ARM® Glossary is a list of terms used in ARM documentation, together with definitions for those
terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning
differs from the generally accepted meaning.
Preface
About this book
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See the ARM® Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the
ARM® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded
area at that time. The actual level is unimportant and does not affect normal operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Figure 1 Key to timing diagram conventions
Signals
The signal conventions are:
Preface
About this book
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Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Lowercase n
At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This book contains information that is specific to this product. See the following documents for other
relevant information.
ARM publications
• Cortex®-M3 DesignStart™ Eval publications:
— ARM® Cortex®-M3 DesignStart™ Eval RTL and Testbench User Guide (ARM 100894).
— ARM® Cortex®-M3 DesignStart™ Eval RTL and FPGA Quick Start Guide (ARM 100895).
— ARM® Cortex®-M3 DesignStart™ Eval Customization Guide (ARM 100897).
• Other ARM publications:
— ARM® Cortex®-M System Design Kit Technical Reference Manual (ARM DDI0479).
— ARM® TrustZone® TRNG True Random Number Generator Technical Reference Manual
(ARM 1009676).
— ARM® PrimeCell™ Real Time Clock (PL031) Technical Reference Manual (ARM DDI
0224).
— ARM® PrimeCell® Synchronous Serial Port (PL022) Technical Reference Manual (ARM
DDI 0194).
— ARM® Versatile™ Express Cortex®-M Prototyping System (V2M-MPS2 and V2M-MPS2+)
Technical Reference Manual (ARM 100112).
— Application Note AN531 uSDCARD SPI Adapter for the Cortex-M Prototyping System
(MPS2+) (ARM DAI 0531).
— Application Note AN502 Adapter for Arduino for the Cortex-M Prototyping System
(MPS2 and MPS2+) (ARM DAI 0502).
— ARM® AMBA® 3 AHB-Lite Protocol Specification (v1.0) (ARM IHI 0033).
— ARM® Architecture Reference Manual ARMv7, for ARMv7-M architecture profile (ARM
DDI0403).
— ARM® Cortex®-M3 Technical Reference Manual (ARM 100165).
— ARM® Cortex®-M3 Devices Generic User Guide (ARM DUI0552).
Other publications
None.
Preface
About this book
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Feedback
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
• The product name.
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms and diagnostic
procedures if appropriate.
Feedback on content
If you have comments on content then send an e-mail to [email protected]. Give:
• The title ARM Cortex-M3 DesignStart Eval FPGA User Guide.
• The number ARM 100896_0000_00_en.
• If applicable, the page number(s) to which your comments refer.
• A concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.
Note
ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the
represented document when used with any other PDF reader.
Preface
Feedback
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Chapter 1
Introduction
This chapter introduces Cortex-M3 DesignStart Eval and gives an overview of the FPGA Evaluation
Flow, its directory structure, and limitations.
It contains the following sections:
•1.1 About Cortex®-M3 DesignStart™ Eval on page 1-12.
•1.2 About the ARM Versatile Express Cortex-M Prototyping System (V2M-MPS2+) on page 1-14.
•1.3 Using the documentation on page 1-15.
•1.4 FPGA Evaluation Flow directory structure on page 1-17.
•1.5 Limitations on page 1-18.
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1.1 About Cortex®-M3 DesignStart™ Eval
Cortex-M3 DesignStart Eval provides developers an easy way to develop and simulate SoC designs
based on the ARM Cortex-M3 processor. It allows a system designer to design and test on a simulator
and then proceed with hardware prototyping using an FPGA.
The Cortex-M3 DesignStart Eval package is aimed at developers who are new to ARM or have limited
soft IP system design experience. The package includes the following:
•1.1.1 RTL on page 1-12.
•1.1.2 Execution Testbench on page 1-13.
•1.1.3 FPGA Evaluation Flow on page 1-13.
Cortex-M3 DesignStart Eval provides an easy entry into the ARM ecosystem, rather than a complete
solution for all Cortex-M processor design scenarios.
The hardware ecosystem in Cortex-M3 DesignStart Eval is built around the CoreLink™ SSE-050
Subsystem and includes the use of the Cortex-M System Design Kit (CMSDK) standard library of
Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) components. For more
information on the CMSDK, see the ARM® Cortex®-M System Design Kit Technical Reference Manual.
The software ecosystem in Cortex-M3 DesignStart Eval uses the ARM Cortex Microcontroller Software
Interface Standard (CMSIS) software standard library.
The use of CMSDK and CMSIS, coupled with a reprogrammable FPGA, allows for a fast turnaround
and prototyping of Cortex-M3 processor-based hardware and software.
Cortex-M3 DesignStart Eval does not support the implementation of the Cortex-M3 processor into
silicon. Any implementation of the Cortex-M3 processor into silicon requires you to obtain Cortex-M3
DesignStart Pro, or take a full Cortex-M3 processor license from ARM.
A Cortex-M3 DesignStart Pro license offers the following:
• The Cortex-M3 processor.
• The SDK-100 System Design Kit (SDK), which includes:
— The CoreLink SSE-050 Subsystem.
— The CMSDK components.
— A Real Time Clock (RTC).
— A stand-alone True Random Number Generation (TRNG).
An Embedded Trace Macrocell (ETM) is not included in Cortex-M3 DesignStart Pro, and requires a
separate license.
If you are working on ASIC implementation, then ARM recommends that you license Cortex-M3
DesignStart Pro as early as possible.
1.1.1 RTL
The RTL in Cortex-M3 DesignStart Eval includes the components and peripherals that are required to
implement a complete example system in an FPGA.
The example system is intended to provide a reference starting point for a typical IoT endpoint
application and is a supported ARM mbed™ platform when implemented on the ARM Versatile Express
Cortex-M Prototyping System (V2M-MPS2+) platform.
The Cortex-M3 DesignStart Eval RTL provides an example system that includes:
• A Cortex-M3 processor in a fixed configuration (obfuscated but synthesizable).
• A modified CoreLink SSE-050 subsystem supporting a single Cortex-M3 processor with support for
debug and trace.
• A memory subsystem supporting Execute In Place (XIP). The MPS2+ platform preloads a code file
at powerup.
• Two timers for Operating System use (privileged access only).
1 Introduction
1.1 About Cortex®-M3 DesignStart™ Eval
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• Peripherals for:
— Application use, including Timers, UART, Watchdog, Real Time Clock (RTC), True Random
Number Generator (TRNG).
— MPS2+ platform, including Color LCD, Audio, and Ethernet.
— Arduino Shield expansion using the adapter for the Arduino board.
• SPI interface supporting application persistent storage on microSD card.
• Reusable ARM Advanced Microcontroller Bus Architecture (AMBA) SoC interconnect components
for system level development.
You must not modify the obfuscated Cortex-M3 processor (cortexm3ds_logic.v).
You are only permitted to redistribute the following files (modified or original), with the original headers
unchanged, and any modifications clearly identified:
•fpga_top.v
•m3ds_user_partition.v
•m3ds_peripherals_wrapper.v
1.1.2 Execution Testbench
The Execution Testbench in Cortex-M3 DesignStart Eval is an RTL package that allows system design
and simulation with a suitable Verilog simulator.
The Cortex-M3 DesignStart Eval Execution Testbench includes:
• A simulation model of the processor that includes register visibility and instruction execution tracing.
• Memory models that match the FPGA target.
• ARM CoreSight™ debug test engine that is preconfigured for a single fixed debug and trace
implementation.
• Integration tests for memories and internal peripherals.
You are expected to modify the test code to support any modifications you make to your design. You
must not redistribute any test code or binaries from these deliverables unless it is developed using mbed
source code.
You are only permitted to redistribute the following files (modified or original), with the original headers
unchanged, and any modifications clearly identified:
•tb_fpga_shield.v
•cmsdk_uart_capture_ard.v
1.1.3 FPGA Evaluation Flow
The Cortex-M3 DesignStart Eval FPGA Evaluation Flow allows developers to build an image file of the
simulation system that can be used with the ARM Versatile Express Cortex-M Prototyping System
(V2M-MPS2+). The FPGA image can be customized to the user system requirements.
The Cortex-M3 DesignStart Eval FPGA Evaluation Flow requires the purchase of the MPS2+ FPGA
platform.
The MPS2+ FPGA platform includes a Motherboard Configuration Controller (MCC) on the baseboard,
which provides the following features that are necessary to emulate an ARM mbed compliant system:
• Target application code. The target has no flash memory. The SRAM is instead initialized at powerup
by the MCC using information stored on the configuration microSD card.
• DAPLink implementing CMSIS-DAP over USB for debug access.
• UART access is provided by a serial connector (and included serial to USB cable).
•Real Time Clock (RTC) initialization from baseboard processor on powerup.
For more information on how to use the MPS2+ FPGA platform, see the ARM® Versatile™ Express
Cortex®-M Prototyping System (V2M-MPS2 and V2M-MPS2+) Technical Reference Manual.
You must not redistribute any FPGA bit files or other representations of the design that are produced
from Cortex-M3 DesignStart Eval.
1 Introduction
1.1 About Cortex®-M3 DesignStart™ Eval
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1.2 About the ARM Versatile Express Cortex-M Prototyping System (V2M-MPS2+)
The MPS2+ platform is a small FPGA development board that contains:
• A Motherboard Configuration Controller (MCC).
• An Altera Cyclone V FPGA.
• Various memories and debug connectors.
• A color LCD touch screen.
• Connectors for Ethernet, VGA, Audio, and serial interfaces.
• User switches and LEDs.
• An SPI to microSD card adapter.
You can program the FPGA with the FPGA image built using ARM Cortex-M3 DesignStart Eval.
The MPS2+ platform enables hardware and software developers to rapidly design and test hardware and
software components as part of a Cortex-M3 processor ecosystem.
For more information on the MPS2+ platform specification, see the ARM® Versatile™ Express Cortex®-M
Prototyping System (V2M-MPS2 and V2M-MPS2+) Technical Reference Manual.
This section contains the following subsection:
•1.2.1 Decryption Key on page 1-14.
1.2.1 Decryption Key
ARM supplies the MPS2+ platform with a decryption key that is programmed into the FPGA.
The decryption key is required to enable loading of the prebuilt images, which are encrypted.
User images do not require the decryption key.
Note
A battery supplies power to the key storage area of the FPGA. Any keys stored in the FPGA are lost
when battery power is lost. If battery power is lost, you must return the board to ARM for
reprogramming of the key.
1 Introduction
1.2 About the ARM Versatile Express Cortex-M Prototyping System (V2M-MPS2+)
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1.3 Using the documentation
There are several documents provided with Cortex-M3 DesignStart Eval.
Scope of this document
The ARM® Cortex®-M3 DesignStart™ Eval FPGA User Guide describes how to build an FPGA image and
evaluate software running on the Versatile Express Cortex-M Prototyping System (V2M-MPS2+)
platform.
Other documents
The following table shows the documents that relate to the design flow processes for Cortex-M3
DesignStart Eval:
Table 1-1 Other Cortex-M3 DesignStart Eval documents
Document name Purpose
ARM® Cortex®-M3 DesignStart™ Eval RTL and Testbench User
Guide
Describes information required for system design and RTL
simulation.
Note
This is the main document for Cortex-M3 DesignStart Eval.
ARM® Cortex®-M3 DesignStart™ Eval RTL and FPGA Quick Start
Guide
Describes how to run basic tests using an RTL simulator and an
FPGA platform.
Note
This is a procedural user-level document that gives a complete
example of a working system. This document is highly
recommended for users who do not have previous experience of
ARM products.
ARM® Cortex®-M3 DesignStart™ Eval Customization Guide Describes the high-level steps to integrate your own peripherals,
and make other modifications to the Cortex-M3 DesignStart Eval
system.
For more information about:
• Programming the Cortex-M3 processor, see the ARM® Cortex®-M3 Technical Reference Manual.
• Software development on a Cortex-M3 device, see the ARM® Cortex®-M3 Devices Generic User
Guide. This is a generic device user-level reference document.
• The ARM architecture that the Cortex-M3 processor complies with, and the instruction set and
exception model it uses, see the ARM® Architecture Reference Manual ARMv7, for ARMv7-M
architecture profile.
• The AHB-Lite master interface that the Cortex-M3 processor implements, see the ARM® AMBA® 3
AHB-Lite Protocol Specification (v1.0).
• Peripherals and interconnect components, see the ARM® Cortex®-M System Design Kit Technical
Reference Manual.
• The Real Time Clock (RTC), see the ARM® PrimeCell™ Real Time Clock (PL031) Technical Reference
Manual.
• The Serial Peripheral Interface (SPI), see the ARM® PrimeCell® Synchronous Serial Port (PL022)
Technical Reference Manual.
1 Introduction
1.3 Using the documentation
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• The MPS2+ platform, see the ARM® Versatile™ Express Cortex®-M Prototyping System (V2M-MPS2
and V2M-MPS2+) Technical Reference Manual.
• The True Random Number Generator (TRNG), see the ARM® TrustZone® TRNG True Random
Number Generator Technical Reference Manual.
1 Introduction
1.3 Using the documentation
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1.4 FPGA Evaluation Flow directory structure
The following diagram and table describe the main directories of the Cortex-M3 DesignStart Eval FPGA
Evaluation Flow:
<install_directory>/
docs/
cmsdk/
m3designstart/
fpga/
software/
m3designstart_iot/
rtc_pl031/
smm/
trng/
logical/
boards/
Recovery/
Figure 1-1 FPGA Evaluation Flow main directories
Table 1-2 Directory descriptions
Directory Description
docs/ Contains documentation for Cortex-M3 DesignStart Eval.
cmsdk/ Contains the RTL for:
• ARM Cortex-M System Design Kit (CMSDK) components. Some CMSDK components are
used in the example system in Cortex-M3 DesignStart Eval.
m3designstart/ Contains the following:
• Scripts for building an FPGA image.
• Example DesignStart system.
• Testbench in testbench/execution_tb/.
• Integration tests in testbench/testcodes/.
• ARM Cortex Microcontroller Software Interface Standard (CMSIS) support files for the
Cortex-M3 DesignStart Eval.
m3designstart_iot/ Cortex-M3 DesignStart Eval version of ARM CoreLink SSE-050 subsystem.
rtc_pl031/ Real Time Clock peripheral.
smm/ Peripherals and support code for the MPS2+ FPGA platform.
trng/ Stand-alone True Random Number Generator.
boards/Recovery/ Contains the files required to be loaded onto the microSD card of the MPS2+ platform, in order
to program and run the prebuilt FPGA image and software.
1 Introduction
1.4 FPGA Evaluation Flow directory structure
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1.5 Limitations
This section describes the limitations of the Cortex-M3 DesignStart Eval FPGA Evaluation Flow.
You should not use the processor technology or the supporting deliverables as an indicator of what is
received under a full technology license of the ARM Cortex-M3 processor.
This section contains the following subsections:
•1.5.1 Deliverables on page 1-18.
•1.5.2 Processor support on page 1-18.
1.5.1 Deliverables
Cortex-M3 DesignStart Eval does not contain the EDA tools used for simulation or compilation.
You must obtain the software tools separately.
The following table shows the supported software tools for Cortex-M3 DesignStart Eval:
Table 1-3 Software tools
Tool Supported software
Compile test code The recommended minimum versions are:
• ARM Keil Microcontroller Development Kit (MDK) version
5.22.
• ARM Development Studio 5 (DS-5) version 5.06.409.
•GNU Tools for ARM Embedded Processors (ARM GCC)
version 5-2016q2.
Compile RTL and FPGA build software The recommended minimum version is:
• Intel Quartus version 16.1.
Note
The Cyclone device on the ARM MPS2+ platform is also
supported by the free Lite Edition of Quartus Prime. No Quartus
license is required to build the Cortex-M3 DesignStart Eval FPGA
Evaluation Flow.
For more information on how to compile and simulate the RTL, see the ARM® Cortex®-M3 DesignStart™
Eval RTL and Testbench User Guide.
1.5.2 Processor support
The FPGA Evaluation Flow supports the Cortex-M3 processor from Cortex-M3 DesignStart Eval.
For more information, see the ARM® Cortex®-M3 DesignStart™ Eval RTL and Testbench User Guide.
1 Introduction
1.5 Limitations
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Chapter 2
Using the prebuilt FPGA image
Cortex-M3 DesignStart Eval includes a prebuilt FPGA image file of the Cortex-M3 DesignStart Eval
example system. This chapter describes how to set up the MPS2+ platform to load the prebuilt file and
run a self-test program.
It contains the following sections:
•2.1 Setting up the MPS2+ FPGA platform on page 2-20.
•2.2 Running the self-test program on page 2-21.
•2.3 Connecting to a debugger on page 2-23.
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2.1 Setting up the MPS2+ FPGA platform
To set up the MPS2+ platform with the provided prebuilt FPGA image file of the Cortex-M3 DesignStart
Eval example system, follow these steps:
1. Connect a USB lead from your computer to the USB-B connector on the MPS2+ platform.
2. Connect the 12V power adapter to the power input connector on the MPS2+ platform. Your computer
should recognize the MPS2+ platform as an external USB drive, named V2M_MPS2.
3. Load an Application Note by locating the boards/Recovery directory in the Cortex-M3 DesignStart
Eval bundle. Copy the following files to the MPS2+ platform directory, which has a similar directory
structure:
/MB/HBI0263C/AN511/
Copy the complete directory.
/MB/HBI0263C/board.txt
Copy the following two lines in the board.txt file:
[MCCS]
MBBIOS: mbb_v221.ebf ; MB BIOS IMAGE. Supports RTC with time updates via
MCC
APPFILE: AN511\an511_v1.txt ; - Cortex-M3 DesignStart
Note
Ensure that the APPFILE:an511_v1.txt line is uncommented, and that all other APPFILE
lines are commented. Only one APPFILE line may be enabled.
/MB/HBI0263C/mbb_v221.ebf
Copy the file.
/SOFTWARE/iot_test.axf
Copy the file.
/config.txt
Copy the file.
Note
In this file, RTC = TRUE. This setting is different from other Application Notes. The Real
Time Clock (RTC) is enabled because Cortex-M3 DesignStart Eval supports RTC, which is
updated at boot-up by the Motherboard Configuration Controller (MCC).
If you are starting with a blank microSD card in the MPS2+ motherboard card slot, you can copy the
entire contents of the boards/Recovery directory (not including the Recovery part of the path) into
the root of the microSD card.
4. Power up the MPS2+ platform.
When the platform is first powered up with a new BIOS file mbb_v221.ebf, the BIOS file is copied
internally. This is indicated by the rapid flashing of LED[0]. After the new BIOS has been successfully
copied, the platform resumes with its standard FPGA loading process, which is indicated by a count
sequence on LED[7:0]. After the FPGA is fully loaded, then the color LCD screen displays a self-test
splash screen.
If the MPS2+ platform does not boot correctly, then refer to the log.txt in the root directory of the
MPS2+ platform, which provides a log of the files loaded at bootup.
For more information on the instructions to set up the platform, see the ARM® Versatile™ Express
Cortex®-M Prototyping System (V2M-MPS2 and V2M-MPS2+) Technical Reference Manual.
2 Using the prebuilt FPGA image
2.1 Setting up the MPS2+ FPGA platform
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