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DECA User Manual
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May 22, 2015

DECA User Manual
1
www.terasic.com
May 22, 2015
CONTENTS
Chapter 1 DECA Development Kit.............................................................. 3
1.1 Package Contents .......................................................................................................................3
1.2 DECA System CD......................................................................................................................4
1.3 Getting Help...............................................................................................................................4
Chapter 2 Introduction of the DECA Board.................................................... 5
2.1 Layout and Components.............................................................................................................5
2.2 Block Diagram of the DECA Board...........................................................................................7
Chapter 3 Using the DECA Board............................................................... 10
3.1 Configuration of MAX 10 FPGAon DECA............................................................................10
3.2 Board Status Elements..............................................................................................................16
3.3 Clock Circuitry.........................................................................................................................17
3.4 Peripherals Connected to the FPGA.........................................................................................18
Chapter 4 DECA System Builder ................................................................ 44
4.1 Introduction..............................................................................................................................44
4.2 General Design Flow................................................................................................................44
4.3 Using DECA System Builder...................................................................................................45
Chapter 5 RTL Example Codes .................................................................. 51
5.1 Breathing LED .........................................................................................................................51
5.2 User IO and CLOCK................................................................................................................53
5.3 Humidity and Temperature Measure........................................................................................56
5.4 Power Monitor..........................................................................................................................58
5.5 Proximity/Ambient Light Sensor .............................................................................................61
5.6 G-Sensor...................................................................................................................................63

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5.7 Line-In ADC.............................................................................................................................65
5.8 HDMI TX.................................................................................................................................68
Chapter 6 NIOS Based Example Codes ..................................................... 73
6.1 CapSense Button......................................................................................................................73
6.2 Temperature Sensor..................................................................................................................76
6.3 Power Monitor..........................................................................................................................78
6.4 Humidity/Temperature Sensor .................................................................................................80
6.5 G-Sensor...................................................................................................................................82
6.6 SMAADC................................................................................................................................84
6.7 DDR3 SDRAM Test by Nios II................................................................................................87
Chapter 7 Advanced NIOS Based Example Codes ..................................... 91
7.1 HDMI Video/Audio TX ...........................................................................................................91
7.2 Gesture Light Sensor................................................................................................................96
7.3 Ethernet Socket server............................................................................................................100
7.4 Micro SD Card file system read.............................................................................................108
7.5 Audio......................................................................................................................................112
7.6 USB Port Interface.................................................................................................................114
Chapter 8 Programming the Configuration Flash Memory........................... 120
8.1 Internal Configuration............................................................................................................120
8.2 Factory Default Dual Boot Image..........................................................................................122
8.3 Using Dual Compressed Images ............................................................................................122
Chapter 9 Appendix ................................................................................... 133
9.1 Revision History.....................................................................................................................133
9.2 Copyright Statement...............................................................................................................133

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Chapter 1
DECA Development Kit
The DECA Development Kit presents a robust hardware design platform built around the Altera
MAX 10 FPGA, which is the industry’s first single chip, non-volatile programmable logic devices
(PLDs) to integrate the optimal set of system components. Users can now leverage the power of
tremendous re-configurability paired with a high-performance, low-power FPGA system. Providing
internally stored dual images with self-configuration, comprehensive design protection features,
integrated ADCs and hardware to implement the Nios II 32-bit microcontroller IP, MAX10 devices
are ideal solution for system management, I/O expansion, communication control planes, industrial,
automotive and consumer applications. The DECA development board is equipped with high-speed
DDR3 memory, video and audio capabilities, Ethernet networking, and much more that promise
many exciting applications.
The DECA Development Kit contains all the tools needed to use the board in conjunction with a
computer that runs the Microsoft Windows XP or later.
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1. .1 1 P Pa ac ck ka ag ge e C Co on nt te en nt ts s
Figure 1-1 shows a photograph of the DECA package.
Figure 1-1 The DECA package contents

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The DECA package includes:
The DECA development board
DECA Quick Start Guide
Two USB cables (Type A to Mini-B) for USB control and FPGA programming and control
Wifi-ble Module
AR0833 8.0M Camera Module
5V DC power adapter
1
1. .2 2 D DE EC CA A S Sy ys st te em m C CD D
The DECA System CD contains all the documents and supporting materials associated with DECA,
including the user manual, system builder, reference designs, and device datasheets. Users can
download this system CD from the link: http://cd-deca.terasic.com.
1
1. .3 3 G Ge et tt ti in ng g H He el lp p
Here are the addresses where you can get help if you encounter any problems:
Altera Corporation
101 Innovation Drive San Jose, California, 95134 USA
Email: [email protected]
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: [email protected]
Tel.: [phone]
Website: deca.terasic.com

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Chapter 2
Introduction of the DECA Board
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2. .1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s
Figure 2-1 shows a photograph of the board. It depicts the layout of the board and indicates the
location of the connectors and key components.
Figure 2-1 DECA development board (top view)

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Figure 2-2 DECA development board (bottom view)
The DECA board has many features that allow users to implement a wide range of designed circuits,
from simple circuits to various multimedia projects.
The following hardware is provided on the board:
Altera MAX® 10 10M50DAF484C6G device
USB-Blaster II onboard for programming; JTAG Mode
512MB DDR3 SDRAM (16-bit data bus)
64MB QSPI Flash
Micro SD card socket
Two CapSense buttons
Two push-buttons
Two slide switches
Eight blue user LEDs
Three 50MHz clock sources from the clock generator
24-bit CD-quality audio CODEC with line-in, line-out jacks
HDMI TX, incorporates HDM v1.4 features, including 3D video supporting
One 10/100 Mbps Ethernet PHY with RJ45 connector
One USB 2.0 PHY with mini-USB type AB connector
One MIPI connector interface supports camera module application
One proximity/ambient lighter sensor
One humidity and temperature sensor
One temperature sensor
One accelerometer
Two MAX 10 FPGAADC SMA inputs

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Two 46-pin BBB expansion headers with 7 analog inputs connected to MAX10 ADC and 69
digital IOs
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2. .2 2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e D DE EC CA A B Bo oa ar rd d
Figure 2-3 is the block diagram of the board. All the connections are established through the MAX
10 FPGA device to provide maximum flexibility for users. Users can configure the FPGA to
implement any system design.
Figure 2-3 Block diagram of DECA

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F
FP PG GA A D De ev vi ic ce e
MAX 10 10M50DAF484C6G Device
Integrated dual ADCs, eachADC supports 1 dedicated analog input and 8 dual function pins
50K programmable logic elements
1,638 Kbits embedded memory
5,888 Kbits user flash memory
4 fractional PLLs
C
Co on nf fi ig gu ur ra at ti io on n a an nd d D De eb bu ug g
Onboard USB-Blaster II (mini USB type B connector)
M
Me em mo or ry y D De ev vi ic ce e
512MB DDR3 SDRAM (16-bit data bus)
64MB QSPI Flash
Micro SD card socket
C
Co om mm mu un ni ic ca at ti io on n
10/100 Mbps Ethernet PHY with RJ45 connector
USB 2.0 PHY with mini-USB type AB connector
C
Co on nn ne ec ct to or rs s
Two 46-pin BBB expansion headers
Two MAX 10 FPGAADC SMA inputs
D
Di is sp pl la ay y
HDMI TX, incorporates HDM v1.4 features, including 3D video supporting
A
Au ud di io o
24-bit CD-quality audio CODEC with line-in, line-out jacks
V
Vi id de eo o I In np pu ut t
MIPI connector interface supports camera module application
A
An na al lo og g

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Two MAX 10 FPGAADC SMA inputs
Seven MAX 10 FPGAADC inputs from one 46-pin BBB expansion header
S
Sw wi it tc ch he es s, , B Bu ut tt to on ns s, , a an nd d I In nd di ic ca at to or rs s
2 push-buttons
2 slide switches
8 blue user LEDs
S
Se en ns so or rs s
One proximity/ambient lighter sensor
One humidity and temperature sensor
One temperature sensor
One accelerometer
P
Po ow we er r
5V DC input

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Chapter 3
Using the DECA Board
This chapter provides an instruction to use the board and describes the peripherals.
3
3. .1 1 C Co on nf fi ig gu ur ra at ti io on n o of f M MA AX X 1 10 0 F FP PG GA A o on n D DE EC CA A
There are two types of configuration method supported by DECA:
1. JTAG configuration: configuration using JTAG ports.
JTAG configuration scheme allows you to directly configure the device core through JTAG pins -
TDI, TDO, TMS, and TCK pins. The Quartus II software automatically generates .sof that are used
for JTAG configuration with a download cable in the Quartus II software programmer..
2. Internal configuration: configuration using internal flash.
Before internal configuration, you need to program the configuration data into the configuration
flash memory (CFM) which provides non-volatile storage for the bit stream. The information is
retained within CFM even if the DECA board is turned off. When the board is powered on, the
configuration data in the CFM is automatically loaded into the MAX 10 FPGA.
JTAG Chain on DECA Board
The FPGA device can be configured through JTAG interface on DECA board, but the JTAG chain
must form a closed loop, which allows Quartus II programmer to the detect FPGA device. Figure
3-1 illustrates the JTAG chain on DECA board.

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Figure 3-1 Path of the JTAG chain
Configure the FPGA in JTAG Mode
The following shows how the FPGA is programmed in JTAG mode step by step.
1. Open the Quartus II programmer and click “Auto Detect”, as circled in Figure 3-2
Figure 3-2 Detect FPGA device in JTAG mode

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2. Select detected device associated with the board, as circled in Figure 3-3.
Figure 3-3 Select 10M50DAES device
3. FPGA is detected, as shown in Figure 3-4.
Figure 3-4 FPGA detected in Quartus programmer
4. Right click on the FPGA device and open the .sof file to be programmed, as highlighted in

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Figure 3-5.
Figure 3-5 Open the .sof file to be programmed into the FPGA device
5. Select the .sof file to be programmed, as shown in Figure 3-6.

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Figure 3-6 Select the .sof file to be programmed into the FPGA device
6. Click “Program/Configure” check box and then click “Start” button to download the .sof file
into the FPGA device, as shown in Figure 3-7.

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Figure 3-7 Program .sof file into the FPGA device
Internal Configuration
The configuration data to be written to CFM will be part of the programmer object file (.pof).
This configuration data is automatically loaded from the CFM into the MAX 10 devices when
the board is powered up.
Please refer to Chapter 8: Programming the Configuration Flash Memory (CFM) for the basic
programming instruction on the configuration flash memory (CFM).

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Figure 3-8 High-Level Overview of Internal Configuration for MAX 10 Devices
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3. .2 2 B Bo oa ar rd d S St ta at tu us s E El le em me en nt ts s
In addition to the 8 LEDs that FPGA device can control, there are 4 indicators which can indicate
the board status (See Figure 3-9), please refer the details in Table 3-1
Figure 3-9 LED Indicators on DECA
Table 3-1 LED Indicators
Board Reference
LED Name
Description
D6
3.3V Power
Illuminate when 3.3V power is active.
D8
CONF_DONE
Illuminate when configuration data is loaded into MAX 10
device without error.
D5
JTAG_RX
Illuminate during data is uploaded from MAX 10 device to PC
through UB2.

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D7
JTAG_TX
Illuminate during configuration data is loaded into MAX 10
device from UB2.
3
3. .3 3 C Cl lo oc ck k C Ci ir rc cu ui it tr ry y
Figure 3-10 shows the default frequency of all external clocks to the MAX 10 FPGA. A clock
generator is used to distribute clock signals with low jitter. The three 50MHz clock signals
connected to the FPGA are used as clock sources for user logic. One 25MHz clock signal is
connected to the clock input of Gigabit Ethernet Transceiver. One 24MHz clock signal is connected
to the clock inputs of USB microcontroller of USB Blaster II. One 19.2MHz clock signal is
connected to the reference clock input of USB2.0 PHY transceiver chip. The other 50MHz clock
signal is connected to MAX CPLD of USB Blaster II. One 10MHz clock signal is connected to the
PLL1 and PLL3 of FPGA, the outputs of these two PLLs can drive ADC clock. The associated pin
assignment for clock inputs to FPGA I/O pins is listed in Table 3-2.

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Figure 3-10 Block diagram of the clock distribution on DECA
Table 3-2 Pin Assignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
MAX10_CLK1_50
PIN_M8
50 MHz clock input
2.5V
MAX10_CLK2_50
PIN_P11
50 MHz clock input
3.3V
DDR3_CLK_50
PIN_N15
50 MHz clock input
1.5V
ADC_CLK_10
PIN_M9
10 MHz clock input
2.5V
3
3. .4 4 P Pe er ri ip ph he er ra al ls s C Co on nn ne ec ct te ed d t to o t th he e F FP PG GA A
This section describes the interfaces connected to the FPGA. User can control or monitor different
interfaces with user logic from the FPGA.

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3
3. .4 4. .1 1 U Us se er r P Pu us sh h- -b bu ut tt to on ns s, , C Ca ap pS Se en ns se e- -b bu ut tt to on ns s, , S Sw wi it tc ch he es s a an nd d
L
LE ED Ds s
The board has two push-buttons connected to the FPGA, as shown in Figure 3-11.MAX 10 devices
support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate and act as
switch debounce in Figure 3-12 for the push-buttons connected.
Figure 3-11 Connections between the push-buttons and the MAX 10 FPGA
Pushbutton releasedPushbutton depressed
Before
Debouncing
Schmitt Trigger
Debounced
Figure 3-12 Switch debouncing
There are two CapSense buttons connected to the FPGA, as shown in Figure 3-13. Through the