Arrow BeMicro CV A9 Operating and maintenance manual

BeMicro CV A9
FPGA Development Board
Hardware Reference Guide
Altera's 28nm Low Cost FPGA Solution
v1.2
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Table of Contents
1. Overview.................................................................................................................................. 3
General Description .................................................................................................................... 3
Board Component Features ........................................................................................................ 4
Development Board Block Diagram............................................................................................ 5
Handling the Board ..................................................................................................................... 7
2. Board Components.................................................................................................................. 7
Cyclone V E FPGA ........................................................................................................................ 9
Configuration Options................................................................................................................. 9
Clock Circuitry ........................................................................................................................... 10
General User Input / Output..................................................................................................... 10
DDR3 Memory........................................................................................................................... 12
Ethernet Interface ..................................................................................................................... 14
EEPROM .................................................................................................................................... 15
Micro SD Card ........................................................................................................................... 15
40 Pin Prototyping Headers ...................................................................................................... 16
80 Pin Card Edge Connector...................................................................................................... 19
Power Supply ............................................................................................................................ 22
3. Additional Information .......................................................................................................... 23
Board Revision History.............................................................................................................. 23
Document Revision History....................................................................................................... 24
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1. Overview
This document describes the hardware features of the BeMicro CV A9 Cyclone V E FPGA
Development Board, including component references and detailed pin-out information.
General Description
The Arrow Electronics BeMicro CV A9 is an enhanced BeMicro CV development board that
utilizes Altera’s 28-nm low-cost Cyclone V FPGA. It retains all the main features of the original
BeMicro CV predecessor while providing a higher logic density and additional features. The
5CEFA9F23C8N on the BeMicro CV A9 includes a hardened memory controller (HMC) connected
to a single 16-bit wide, 1Gb DDR3 SDRAM device. FPGA user I/O are routed to the two 40-pin
I/O headers and 80-pin MEC-style edge connector. The BeMicro CV A9 also includes an on
board USB Blaster programmer, Micro-SD card slot, and a 10/100/1000 Ethernet PHY.
The BeMicro CV A9 is well suited for DSP and logic-intensive applications such as Software
Defined Radio (SDR), data acquisition, and video processing. BeMicro CV A9 is compatible
with the Arrow BeScope digital oscilloscope, SDRstickTM SDR front-end boards, and the Terasic
MTL LCD module. For a complete list of products compatible with BeMicro CV A9 board, see
the BeMicro CV A9 Partner Pack at http://www.arrow.com/bemicro.
Users can easily migrate existing designs from BeMicro SDK or BeMicro CV to BeMicro CV A9.
Table 1-1 provides a brief feature comparison of the Cyclone-based BeMicro development
boards.
Table 1-1: BeMicro Feature Comparison
BeMicro SDK BeMicro CV BeMicro CV A9
FPGA EP4CE22F17C7 5CEFA2F23C8N 5CEFA9F23C8N
External Memory Mobile DDR DDR3 DDR3
Memory Controller Soft (Microtronix) Hard Hard
Expansion I/O 80 pin edge connector 2 x 40 pin I/O +
80 pin edge connector
2 x 40 pin I/O +
80 pin edge connector
Ethernet Yes No Yes
USB Blaster Integrated Integrated Integrated
Micro-SD card slot Yes Yes Yes
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Board Component Features
The BeMicro CV A9 board features the following major component blocks:
Cyclone V E FPGA (5CEFA9F23C8N) in a 484-pin FineLine BGA (FBGA)
•113,560 adaptive logic modules (ALMs) equivalent to 301,000 LEs
•12,200 Kbit (Kb) M10K and 1,717 Kb MLAB memory
•8 fractional phase locked loops (PLLs)
•684 18 x 18-bit multipliers
•2 Hard Memory Controllers
•up to 480 general purpose input/output (GPIO)
•1.1 V core voltage
FPGA configuration circuitry
•256Mb QSPI Active Serial (AS) x4 configuration
•Embedded USB-BlasterTM II for use with the Quartus®II Programmer
•Separate JTAG configuration header
High Speed Networking
•Gigabit Ethernet PHY (Micrel KSZ9021)
•RJ-45 Ethernet connector
Clocking circuitry
•50 MHz 1.8V oscillator
•24 MHz 2.5V/3.3V oscillator
Memory
•1Gbit DDR3 SDRAM (64M x 16)
•1Kbit (128 x 8) two-wire Serial EEPROM
•Micro-SD card slot
General user input / output
•8 user LEDs
•2 user pushbuttons
•4 user DIP switches
Prototyping
•2 Terasic 40 pin prototyping headers (45 user I/O)
•BeMicro SDK 80-pin MEC card edge connector (57 user I/O)
Power via external 5V supply, or via USB for limited functions
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Development Board Block Diagram
Figure 1-1 shows a block diagram of the BeMicro CV A9 FPGA development board.
Figure 1-1: BeMicro CV A9 Block Diagram
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Figure 1-2 shows a top view of the BeMicro CV A9 FPGA development board.
Figure 1-2: Top View of BeMicro CV A9 Development Board.
Figure 1-3 shows a bottom view of the BeMicro CV A9 FPGA development board.
Figure 1-3: Bottom View BeMicro CV A9 Development Board
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Handling the Board
When handling the board, it is important to observe the following static discharge precaution:
Without proper anti-static handling, the board can be damaged. Therefore, use anti-static
handling precautions when touching the board.
2. Board Components
This chapter introduces the major components on the Be Micro CV A9 FPGA development
board. Figure 2-1 and Figure 2-2 illustrate the component locations.
Figure 2-1: Major component locations, Top View
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Figure 2-2: Major component locations, Bottom View
This chapter includes the following sections:
•Cyclone V E FPGA
•Configuration Options
•Clock Circuitry
•General User Input / Output
•DDR3 Memory
•Ethernet Interface
•EEPROM
•Micro SD Card
•40 Pin Prototyping Headers
•80 Pin Card Edge Connector
•Power Supply
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Cyclone V E FPGA
The BeMicro CV A9 FPGA development board features a Cyclone V E FPGA device
(5CEFA9F23C8N) in a 484-pin FBGA package. Table 2–1 describes the features of the Cyclone
V E FPGA 5CEFA9F23C8N device.
Table 2-1: Features of the Cyclone V E 5CEFA9F23C8N
ALMs Equivalent
LE’s
M10K RAM
(Kbits)
MLAB RAM
(Kbits)
18-bit x 18-bit
Multipliers PLLs Package Type
113,560 301K 12,200 1,717 684 8 484 pin FBGA
Configuration Options
The BeMicro CV A9 FPGA development board supports the following configuration methods:
■Embedded USB-Blaster is the default method for configuring the FPGA using the
Quartus II Programmer in JTAG mode with the supplied USB cable.
■Active Serial Configuration via the on-board N25Q256A13EF8 configuration device.
FPGA Programming over Embedded USB-Blaster II
This configuration method combines a USB mini-B connector (J10), a USB 2.0 PHY device (U9),
and an Altera MAX V 5M80ZE64 CPLD (U10) to allow FPGA configuration using a USB cable.
This USB cable connects directly between the USB mini-B connector on the board and a USB
port on a PC running the Quartus II software. The embedded USB-Blaster in the MAX V
EPM80ZE64 CPLD normally masters the JTAG chain.
FPGA Programming using EPCQ Compatible Configuration PROM
The low-cost N25Q256A13EF8 non-volatile configuration PROM features a simple six-pin
interface and a small form factor. The PROM supports the AS x4 configuration mode. By
default, the BeMicro CV A9 board is set up to configure via AS x 4 configuration mode.
Resistors R97 and R98 allow selection between AS Fast and AS Standard modes.Figure 2–3
shows the connection between the EPCQ configuration device and the Cyclone V E FPGA.
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Figure 2-3: Active Serial x4 Configuration Interface
Clock Circuitry
The development board includes two oscillators with frequencies of 24 MHz and 50 MHz.
Table 2–2 lists the oscillators, their I/O standard, and voltages required for the development
board.
Table 2-2: BeMico CV On-board oscillators
Board
Reference
Schematic Signal
Name
Frequency I/O
Standard
FPGA Pin
Number
Application
Y1 DDR3_CLK_50MHZ 50 MHz 1.8V H13 DDR3 HMC Clock Input
Y2 CLK_24MHZ 24 MHz 2.5V or
3.3V 1
M9 General Purpose Clock
Input, also used by
on-board USB Blaster II
Note 1: I/O voltage for this interface is selectable using the VCCIO_SEL jumper
General User Input / Output
The development board includes switches for user input and LEDs for status output. This
section describes these elements.
LED Outputs
There are multiple LED indicators on the board, but only LED1-LED8 are available for use
through FPGA I/O. Driving the FPGA output to a logic 0 will illuminate the LED. Driving a
logic 1 turns it off. Table 2–3 lists the LED board references, schematic signal names, and
functional descriptions.
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