Asahi KASEI AK5704 User manual

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GENERAL DESCRIPTION
The AKD5704-C is an evaluation board for the AK5704, 4 channel 32-bit ADC with built-in PLL and
microphone amplifier. The AKD5704-C also has the digital audio interface and can achieve the interface
with digital audio systems via optical connector or I2S interface.
◼Ordering Guide
AKD5704-C --- AK5704 Evaluation Board
(Control software is included in this package.)
FUNCTION
•Mini jack for analog input
•Digital audio interface
- Optical output connector for S/PDIF
- Header pin for external interface
•USB port for serial control interface
[Main Board]
5V
[+3.3V]
[+1.8V]
PIC18F4550
(USB Serial IF)
AK5704
VDD5V
REG
REG
0V
GND
Mini
Jack
AIN1A+/DMDAT1
J104
AIN1A
AIN1A-
Mini
Jack
AIN1B+/DMCLK1
J103
AIN1B
AIN1B-
AIN2A+/DMDAT2
J102
AIN2A
AIN2A-
Mini
Jack
AIN2B+/DMCLK2
J101
AIN2B
AIN2B-
I2C
AK4118A
(S/PDIF)
TOS
LINK
PORT201
OPT-OUT
USB
Type-C
USB401
MCKI
BCLK
LRCK
SDTO1
SDTO2
J401
J402
Mini
Jack
VSS1/2
AVDD
TVDD
Level
Shifter
Level
Shifter
Level
Shifter
[+3.3V]
REG
U301
U201
U101
10-pin
Header
PORT202
AUDIO-IF
U302
U202
U203
MCKO
X’tal
T402
T401
T403
Figure 1. AKD5704-C Block Diagram
AK5704 Evaluation Board Rev.0
AKD5704-C

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◼Power Supply Setting
(1) In case of supplying the power from USB <default>
Jumper pins setting
→Shorted by jumper pin
When using
3.3 V
When using
1.8 V
JP402
AVDD-SEL
3.3V
1.8V
AVDD-SEL
3.3V
1.8V
JP401
VDD-SEL
VDD5V
USB5V
Power supply connection
Table 1. Power Supply Setting
Part No.
Color
Name
Supply Voltage
Used By
J401
Red
VDD5V
Open
Regulator
J402
Black
GND
Open
Ground
(2) In case of using each power supply connectors (J401, J402)
Jumper pins setting
→Shorted by jumper pin
When using
3.3 V
When using
1.8 V
JP402
AVDD-SEL
3.3V
1.8V
AVDD-SEL
3.3V
1.8V
JP401
VDD-SEL
VDD5V
USB5V
Power supply connection
Table 2. Power Supply Setting
Part No.
Color
Name
Supply Voltage
Used By
J401
Red
VDD5V
+5 V
Regulator
J402
Black
GND
0 V
Ground

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◼Evaluation Mode
1. Input Setting
(1) Analog input setting <default>
(1-1) When using mini jack (Single-ended input) <default>
Input single-ended analog signals to the Lch side of the mini-jack. The Rch side should be 0 V or open.
→Shorted by jumper pin
J104
AIN1A
JP104
1AGND
1ASEL
SE
DIFF
JP108
J103
AIN1B
JP103
1BGND
1BSEL
SE
DIFF
JP107
J102
AIN2A
JP102
2AGND
2ASEL
SE
DIFF
JP106
J101
AIN2B
JP101
2BGND
2BSEL
SE
DIFF
JP105
(1-2) When using mini jack (Full-differential input)
Input the differential positive signal to the Lch side of the mini-jack and the differential negative signal the Rch side.
→Shorted by jumper pin
J104
AIN1A
JP104
1AGND
1ASEL
SE
DIFF
JP108
J103
AIN1B
JP103
1BGND
1BSEL
SE
DIFF
JP107
J102
AIN2A
JP102
2AGND
2ASEL
SE
DIFF
JP106
J101
AIN2B
JP101
2BGND
2BSEL
SE
DIFF
JP105
(2) Digital microphone input setting
Do not connect anything to J101, J102, J103 and J104. Connect a digital microphone to the following test pins.
→Shorted by jumper pin
J104
AIN1A
JP104
1AGND
1ASEL
SE
DIFF
JP108
J103
AIN1B
JP103
1BGND
1BSEL
SE
DIFF
JP107
J102
AIN2A
JP102
2AGND
2ASEL
SE
DIFF
JP106
J101
AIN2B
JP101
2BGND
2BSEL
SE
DIFF
JP105
Table 3. Connection Pin for the Digital Microphone
Test Pin
AK5704 Pin Name
Corresponding ADC
TP104 DMDAT1
AIN1A+/DMDAT1
ADC1
TP103 DMCLK1
AIN1B+/DMCLK1
ADC1
TP102 DMDAT2
AIN2A+/DMDAT2
ADC2
TP101 DMCLK2
AIN2B+/DMCLK2
ADC2

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2. Output Settings
(1) When using S/PDIF optical output (OPT-OUT [PORT201]) <default>
Connect an optical digital cable to PORT201. System clock of the AK5704 should be set to external slave mode and
BCLK = 64fs. A crystal of 24.576 MHz is mounted on X201.
(1-1) In case of fs = 48 kHz and MCLK = 256fs <default>
JP203 is set to MCKO2 side. OCKS1 of SW201 is set to “H” side and OCKS0 of SW201 is set to “L” side.
→Shorted by jumper pin
JP201
MASTER
JP205
XTO-SEL
XTL
MCKO
JP204
BCLK-SEL
JP206
SDTO-SEL
SDTO1
SDTO2
JP202
LRCK-SEL
JP203
MCLK-SEL
MCKO2
MCKO1
* When inputting SDTO2 signals to the AK4118A,
set JP206 to the SDTO2 side.
DIF1
DIF0
OCKS1
OCKS0
SW201
L
H
1
2
3
4
ON
(1-2) In case of fs = 96 kHz and MCLK = 256fs
JP203 is set to MCKO2 side. OCKS1 and OCKS0 of SW201 are set to “L” side.
→Shorted by jumper pin
JP201
MASTER
JP205
XTO-SEL
XTL
MCKO
JP204
BCLK-SEL
JP206
SDTO-SEL
SDTO1
SDTO2
JP202
LRCK-SEL
JP203
MCLK-SEL
MCKO2
MCKO1
* When inputting SDTO2 signals to the AK4118A,
set JP206 to the SDTO2 side.
DIF1
DIF0
OCKS1
OCKS0
SW201
L
H
1
2
3
4
ON
(1-3) In case of fs = 192 kHz and MCLK = 128fs
JP203 is set to MCKO1 side. OCKS1 and OCKS0 of SW201 are set to “H” side.
→Shorted by jumper pin
JP201
MASTER
JP205
XTO-SEL
XTL
MCKO
JP204
BCLK-SEL
JP206
SDTO-SEL
SDTO1
SDTO2
JP202
LRCK-SEL
JP203
MCLK-SEL
MCKO2
MCKO1
* When inputting SDTO2 signals to the AK4118A,
set JP206 to the SDTO2 side.
DIF1
DIF0
OCKS1
OCKS0
SW201
L
H
1
2
3
4
ON

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(2) When using the 10-pin header I2S audio output (AUDIO-IF [PORT202])
By connecting an external controller to PORT202, I2S audio data is output. Set clock settings of the AK5704 according
to each mode and match the input/output settings with the external controller.
(2-1) In case of PLL Master Mode
When the master clock is input to the MCLK pin of PORT202, BCLK and LRCK are generated by PLL of the AK5704,
and then SDTO1 and SDTO2 are output.
PORT202
10-pin Header
10-pin
Connector
10-pin
Flat cable
Connect
3.BCLK
9.NC
1.MCLK
7.SDTO1
5.LRCK
10.SDTO2
2.MCKO
4.GND
6.GND
8.GND
1.MCLK
3.BCLK
5.LRLK
7.SDTO1
10.SDTO2
2.MCKO
Figure 2. PORT202 (10-pin Header) Connection Example [PLL Master Mode]
→Shorted by jumper pin
JP201
MASTER
JP205
XTO-SEL
XTL
MCKO
JP204
BCLK-SEL
JP206
SDTO-SEL
SDTO1
SDTO2
JP202
LRCK-SEL
JP203
MCLK-SEL
MCKO2
MCKO1
(2-2) In case of PLL Slave Mode (Reference Clock: BCLK)
When the BCLK and LRCK are input from PORT202, the master clock is generated by PLL of the AK5704, and then
SDTO1 and SDTO2 are output. (Input “L” to MCLK.)
PORT202
10-pin Header
10-pin
Connector
10-pin
Flat cable
Connect
3.BCLK
10.SDTO2
2.MCKO
9.NC
1.MCLK
7.SDTO1
5.LRCK
4.GND
6.GND
8.GND
1.MCLK (“L”)
3.BCLK
5.LRLK
7.SDTO1
10.SDTO2
Figure 3. PORT202 (10-pin Header) Connection Example [PLL Slave Mode]
→Shorted by jumper pin
JP201
MASTER
JP205
XTO-SEL
XTL
MCKO
JP204
BCLK-SEL
JP206
SDTO-SEL
SDTO1
SDTO2
JP202
LRCK-SEL
JP203
MCLK-SEL
MCKO2
MCKO1

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(2-3) In case of External Master Mode
When the master clock is input to the MCLK pin of PORT202, the divided BCLK and LRCK are output from the
AK5704, and then SDTO1 and SDTO2 are output.
PORT202
10-pin Header
10-pin
Connector
10-pin
Flat cable
Connect
3.BCLK
10.SDTO2
2.MCKO
9.NC
1.MCLK
7.SDTO1
5.LRCK
4.GND
6.GND
8.GND
1.MCLK
3.BCLK
5.LRLK
7.SDTO1
10.SDTO2
Figure 4. PORT202 (10-pin Header) Connection Example [External Master Mode]
→Shorted by jumper pin
JP201
MASTER
JP205
XTO-SEL
XTL
MCKO
JP204
BCLK-SEL
JP206
SDTO-SEL
SDTO1
SDTO2
JP202
LRCK-SEL
JP203
MCLK-SEL
MCKO2
MCKO1
(2-4) In case of External Slave Mode
When the MCLK, BCLK and LRCK are input from PORT202, SDTO1 and SDTO2 are output.
PORT202
10-pin Header
10-pin
Connector
10-pin
Flat cable
Connect
3.BCLK
10.SDTO2
2.MCKO
9.NC
1.MCLK
7.SDTO1
5.LRCK
4.GND
6.GND
8.GND
1.MCLK
3.BCLK
5.LRLK
7.SDTO1
10.SDTO2
Figure 5. PORT202 (10-pin Header) Connection Example [External Slave Mode]
→Shorted by jumper pin
JP201
MASTER
JP205
XTO-SEL
XTL
MCKO
JP204
BCLK-SEL
JP206
SDTO-SEL
SDTO1
SDTO2
JP202
LRCK-SEL
JP203
MCLK-SEL
MCKO2
MCKO1

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(3) Other setting
SW301 : Reset for the AK5704 and the AK4118A
CL101 (CAD) : Setting of the AK5704 CAD pin
Open: I2C Chip Address = 0 <default>
Short: I2C Chip Address = 1

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CONTROL SOFTWARE MANUAL
◼Evaluation Board and Control Software Settings
1. Set the evaluation board according to each evaluation mode and turn on the power supply.
2. Connect the evaluation board USB401 to the PC with a USB cable.
3. The USB controller is recognized as HID (Human Interface Device) on the PC.
4. Please launch the control software (AK5704.exe). If “AKDUSBIF-B”is not displayed in the lower left and “No Port”
is displayed, close the control software once and reconnect the PC ang the USB cable. After that restart the control
software.
5. Press the [PDN: L] button and confirm that the display changes to [PDN: H]. The reset of the AK5704 and the
AK4118A is released.
Figure 6. Window of Control Software

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◼Operation Overview
Function and register map are controlled by this control software. These controls may be selected by the upper tabs.
Frequently used Buttons, such as the register initializing button “Write Default”, are located outside of the switching
window.
Figure 7. Register Initial Setting Button
1. [InitPort] : Initializes the USB port on the main board.
If the USB port is not initialized correctly after starting the software or if the USB cable is
unplugged or plugged in, click this button to initialize the USB port again.
2. [CAD0/CAD1] : Select the chip address of I2C-bus.
3. [Write Default] : AK5704 register initialization.
4. [All Read] : Execute read commands for all registers of the AK5704 and display in RegMap.
5. [All Write] : Execute write commands for all AK5704 registers displayed.
6. [Script Save] : Save the script with the current setting.
7. [Read] : It reads the current register and displays “Address: Read value”in the display field at the bottom
of “Address: Data”.
Unlike the [All Read] button, only hexadecimal display is performed and it is not reflected in the
register map.
8. [Init Board] : This function is not used.
9. [PDN:H] : Control the PDN pin of the AK5704 and the AK4118A.
([PDN:H] →PDN pin = “H”, [PDN:L] →PDN pin = “L”)
10. [Close] : Exit the control software.
7
1
2
4
10
9
3
5
6
8

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◼Tab Functions
(1) [MainFunc] Tab: Function Control
Clicking on each block in the window opens the settings window for that block. The displayed selector can be selected
directly. With the three function buttons at the top of the window, execute the sequence processing of the function
described on the button.
Figure 8. [MainFunc] Window
1. AVDD operation mode setting
2. Analog input/Digital microphone input select (AIN1, AIN2)
3. Single-ended input/Full-differential input select (AIN1A, AIN1B, AIN2A, AIN2B)
4. Stereo/Mono mode select
5. SDTO2 output, TDMIN input select
6. Slave/Master mode select
7. PLL clock source (MCKI/BCLK) select
8. MCKI frequency select
9. BCLK output frequency select (Only master mode)
10. Sampling Frequency select
11. Master clock rate select
12. Master clock output select
13. Pull-down resistance of each pin enable/disable (BCLK, LRCK, TDMIN/SDTO2, MCKO, SDTO1)
14. Power management of each block
(PMAD1A, PMAD1B, PMAD2A, PMAD2B, PMPFIL1, PMPFIL2, PMVAD, PMPLL)
1
2
3
3
4
2
5
7
6
8
9
10
13
13
12
11
14
14
14
14
14
(1-1)
(1-3)
(1-3)
(1-2)
(1-4)
(1-4)
(1-5)
(1-6)
(1-1)

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(1-1) ADC, MIC Gain Setting
Clicking the MicGain block on the [MainFunc] window opens the [ADC, MIC Gain Setting] window. Power-up/down
of MIC-Amp, ADC, Digital MIC and related settings are controlled.
AVDD internal operation mode on the [MainFunc] window should be set before power-up of the ADC.
Figure 9. [ADC, MIC Gain Setting] Window

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(1-2) Digital Function Setting
Clicking the Delay, HPF, MIC Sensitivity Correction block on the [MainFunc] window opens the [Digital Function
Setting] window. Delay, HPF and MIC Sensitivity settings are controlled.
Figure 10. [Digital Function Setting] Window

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(1-3) Mixer, HPF, LPF Setting
Clicking the MIX1, MIX2, HPF1/LPF1 or HPF2/LPF2 block on the [MainFunc] window opens the [Mixer, HPF, LPF
Setting] window. Power-up/down of Programmable Filter (HPF, LPF), Mixer and related settings are controlled.
Figure 11. [Mixer, HPF, LPF Setting] Window
PFTHR1/2 bits and PFSDO1/2 bits can be switched directly from the [MainFunc] window.

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(1-4) ALC Setting
Clicking the ALC1 or ALC2 block on the [MainFunc] window opens the [ALC Setting] window. Power-up/down of
Programmable Filter (HPF, LPF) and ALC settings are controlled.
Figure 12. [ALC Setting] Window

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(1-5) VAD Setting
Clicking the VAD or VAD Delay block on the [MainFunc] window opens the [VAD Setting] window. Power-up/down
of VAD and related settings are controlled.
Figure 13. [VAD Setting] Window
VADSEL bit, VAS[2:0] bits, VBS[2:0] bits and VADOE bit can be switched directly from the [MainFunc] window.

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(1-6) Audio I/F Setting
Clicking the Audio I/F block on the [MainFunc] window opens the [Audio I/F Setting] window. Audio I/F setting are
controlled.
Figure 14. [Audio I/F Setting] Window

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(2) [Script] Tab: Script Function
This is the tab for executing the script file. If the [Refer] button is clicked, and the script file is selected, the program is
executed automatically. By clicking the [Repeat] button, the selected script file will be executed again.
Figure 15. [Script] Window
Table 4. Command of Script
Command
Notation
Description
[SCRIPT]
-
Header of script file. A data error will be detected without this header.
; Comment
-
The line following to “;” is recognized as comment and ignored.
RI:H or RI:L
H or L
Control the PDN pin.
RI:H: Reset release (PDN pin = “H”)
RI:L: Reset (PDN pin = “L”)
T, <wait>
ex) T, 50ms
base 10
(DN)
Set a waiting time.
ex) 50 msec wait.
W: <address>, <data>
base 16
(HEX)
Register write is executed.
Address: 1 byte
Data: 1 byte

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(3) [RegMap] Tab: Register Map
This tab is for register read and write.
Each bit of the register map is a push button, and the register is updated at the click timing.
“1”: Indicate in red letters.
“0”: Indicate in blue letters.
The register which are not defined in the datasheet are indicated “---”.
Figure 16. [RegMap] Window
Address Tab: Move to the address map in the displayed range.
Write: Click the [Write] button located on the right of each corresponding address when changing two or more bits on
the same address simultaneously.
Read: Click the [Read] button located on the right of each corresponding address to execute a register read. The current
register value will be displayed in the register map.
Register Setting
Address Tab

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MEASUREMENT RESULTS
[Conditions]
- Measurement Unit : Audio Precision APX555 audio analyzer
- Master Clock : 256fs (12.288 MHz@48 kHz, 24.576 MHz@96 kHz),
128fs (24.576 MHz@192 kHz)
- Sampling Frequency : 48 kHz, 96 kHz, 192 kHz
- Resolution : 24 bit
- Measurement Mode : External slave mode
- Power Supply : AVDD = 3.3 V (Regulator), TVDD = 1.8 V (Regulator)
- Input Signal : 1 kHz (Sine wave)
- Measurement Frequency : 20 to 20 kHz@48 kHz, 20 to 40 kHz@96 kHz/192 kHz
- Temperature : Room
[Results]
Parameter
MGAIN
Result
Unit
AIN1A
AIN1B
AIN2A
AIN2B
ADC1/2 Analog Input Characteristics:
AIN1A+, AIN1B+, AIN2A+, AIN2B+ pins (Single-ended input) →ADC1/2 →SDTO1/2
THD+N
−1 dBFS
fs = 48 kHz,
BW = 20 kHz
0 dB
−97.6
−97.1
−97.5
−96.5
dB
+18 dB
−90.2
−90.0
−90.5
−90.0
dB
fs = 96 kHz,
BW = 40 kHz
0 dB
−95.6
−95.4
−95.9
−96.6
dB
+18 dB
−88.4
−88.3
−88.4
−88.6
dB
fs = 192 kHz,
BW = 40 kHz
0 dB
−95.7
−95.4
−96.2
−96.8
dB
+18 dB
−88.4
−88.3
−88.4
−88.6
dB
Dynamic Range
(−60 dBFS, A-Weighted)
fs = 48 kHz,
BW = 20 kHz
0 dB
104.4
104.5
104.4
104.1
dB
+18 dB
95.4
95.5
95.4
95.5
dB
S/N (A-weighted)
fs = 48 kHz,
BW = 20 kHz
0 dB
104.5
104.5
104.4
104.2
dB
+18 dB
95.4
95.5
95.5
95.6
dB

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REVISION HISTORY
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of AKM or any third party with respect to the information
in this document. You are fully responsible for use of such information contained in this document in
your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES
INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION
IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including but
not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical
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Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible
for complying with safety standards and for providing adequate designs and safeguards for your
hardware, software and systems which minimize risk and avoid situations in which a malfunction or
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6. Resale of the Product with provisions different from the statement and/or technical features set forth in
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written consent of AKM.
Date
(yy/mm/dd)
Manual
Revision
Board
Revision
Reason
Page
Contents
23/11/30
KM137900
0
First Edition
-