Asahi KASEI AKD5538-B User manual

[AKD5538-B]
<KM131000> 2018/10
GENERAL DESCRIPTION
The AKD5538-B is an evaluation board for AK5538VN, which is 32bit, 8k –768kHz, 8ch ADC.
The AKD5538-B is includes the analog input circuit and also has a digital interface transmitter .
Further, the AKD5538-B can achieve the interface with digital audio systems via BNC-Connector.
Ordering guide
AKD5538-B -- Evaluation board for AK5538VN
FUNCTION
•DIT with BNC or Optical digital output.
•ADC 8ch input is possible.
•BNC Connector for an external clock input.
AK4118A
(DIT)
AIN1
AIN2
Clock
Generator
+VOP
Input
Buffer
AK5538
-VOP
TVDD
Regulators
+3.3V
+15V
-15V
AVDD
+3.3V
BNC_TX
(OUT)
DSP Data
10pin Header
AIN3
AIN4
Input
Buffer
AIN5
AIN6
Input
Buffer
AIN7
AIN8
Input
Buffer
INPUT
OPT_TX
(OUT)
+1.8V
VDD18
Figure 1. AKD5538-B Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
AKD5538-B
AK5538 Evaluation Board Rev.0
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[AKD5538-B]
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Evaluation Board Diagram
Board Diagram
J1001
J1002
J1000
SW803
SW800
U6
J300
J301
SW804
SW801
PORT801
PORT700
T1001
T1002
J1005
J1004
T1003
J1006
J1007
J1008
J1003
J1009
J201
J200
J400
J401
J500
J501
T1004
T1005
SW802
J600
PORT600
PORT803
PORT802
PORT800
J800
SW600
U100
AKD5538-B
AK5538
Figure 2. AKD5538-B Board Diagram
*AKD5538-B Evaluation Board
Description
(1) U100 ( AK5538 )
32bit,8k - 768kHz,8ch A/D Converter.
(2) J200,J201,J300,J301,J400,J401,J500,J501 ( Analog data )
Cannon Connector : Differential Analog Input
(3) J600 / PORT600 ( Digital data )
BNC Connector / Optical Connector: Digital Output.
(4) J1000, J1001, J1002,J1003,J1004,J1005,J1006,J1007,J1008,J1009 ( Power supply )
Power Supply Connector.
(5) PORT800,PORT801 ( pin header )
Pin header for evaluation (MCLK, BICK, LRCK, SDTO1, SDTO2, SDTO3, SDTO4, TDMIN).
(6) PORT802,PORT803 ( pin header )
Pin header for evaluation (DCLK, DSDOL1/R1, DSDOL2/R2, DSDOL3/R3, DSDOL4/R4).
(7) U200 ( AK4118A )
AK4118A has DIT. Transports output data from AK5538.
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(8) SW800 ( Toggle switch )
Toggle type-switch PDN for AK5538.
“H” : PDN = High
“L” : PDN = Low
(9) SW801 ( Toggle switch )
Toggle type-switch PDN for AK4118A.
“H” : PDN = High
“L” : PDN = Low
(10)SW802,SW803,SW804 ( Dip switch)
DIP type-switch for AK5538.
“H” : Digital signal = High
“L” : Digital Signal = Low
(11)SW600 ( Dip switch (Dual In-line Package switch)
DIP type-switch for AK4118A.
“H” : Digital signal = High
“L” : Digital Signal = Low
(12)J800 ( MCLK external input )
BNC Connector : External Clock Input (MCLK).
(13)T1001, T1002, T1003, T1004, T1005
Regulator for AK5538, AK4118A, Logic Circuit.
T1001 : Regulated AVDD, VBIAS (+3.3V) from +15V.
T1002 : Regulated VCC1, VCC2 (+5.0V) from +15V.
T1003 : Regulated TVDD (+3.3V) from +5V.
T1004 : Regulated TVDD, VDD18 (+1.8V) from +5V
T1005 : Regulated D33V (+3.3V) from +5V.
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[AKD5538-B]
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Evaluation Board Manual
Operation sequence
[1] Power supply line settings
[2] Jumped pins settings
[3] DIP switches settings
[4] Toggle switches settings
[5] Register control (Serial control)
[6] Evaluation modes
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[1] Power supply line settings
(1-1) Power supply settings : Used the regulator (T1001,T1002,T1003,T1004,T1005) <Default>
Set up the power supplied lines :
* Each supply line should be distributed from the power supply unit.
Name
Color
Setting (Typ)
Function
Comments
Default Settings
J1000
+15V
Green
+15V
Regulator and Op-amp
power supply
Should always be connected
+15V
J1001
-15V
Blue
-15V
Regulator and Op-amp
power supply
Should always be connected
-15V
J1004
AVDD
Red
+3.3V
AK5538 AVDD
+3.3V regulator is used,
R1007=short by default.
When jack is used,
R1008=short.
REG :
(R1007 = short)
J1005
VBIAS
Red
+3.3V
Referential Voltage
source for Op-amp
+3.3V regulator is used,
R1009=short by default.
When jack is used,
R1010=short.
REG :
(R1009 = short)
J1009
VCC
Red
+5.0V
+5.0V Regulator power
supply
+5.0V regulator is used,
R1011=short by default.
When jack is used,
R1012=short.
REG :
(R1011 = short)
J1006
TVDD
Orange
+1.8V / +3.3V
AK5538 TVDD,
Logic IC power supply
+3.3V regulator is used,
JP1000=3.3V and
JP1001=REG by default.
When +1.8V regulator is
used, JP1000=1.8V and
JP1001=REG.
When jack is used,
JP1012=JACK short.
REG (+3.3V) :
(JP1000=3.3V and
JP1001=REG)
J1007
VDD18
Orange
+1.8V
AK5538 VDD18
LDO of AK5538 is used,
JP1002=open by default.
When +1.8V regulator is
used, JP1002=REG.
When jack is used,
JP1002=JACK.
Open :
(JP1002=open)
J1008
D3.3V
Orange
+3.3V
AK4118A +3.3V VDD,
Logic IC power supply
+3.3V regulator is used,
JP1003=REG by default.
When jack is used,
JP1003=JACK.
REG :
(JP1003=REG)
J1002
AVSS
Black
0V
Analog ground
Should always be connected
0V
J1003
DVSS
Black
0V
Digital ground
Should always be connected
0V
Table 1-1. Power supply line setting ( default : used the regulator )
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(1-2) About jumper for power supply :
The roles of the jumper or the short resistance for each power supply supplied from the regulator are as follows.
Connection of the jumper for power supply :
Name
Function
Comments
Default Settings
R1007
R1008
AVDD1
Select regulator power supply
or jack for AVDD1
AVDD for AK5538:
R1007=short : +3.3V regulator is used. (default)
R1008=short : Jack is used.
REG :
R1007=short
R1008=open
R1009
R1010
VBIAS
Select regulator power supply
or jack for VBIAS
VBIAS for Op-amp Referential Voltage source:
R1009=short : +3.3V regulator is used. (default)
R1010=short : Jack is used.
REG :
R1009=short
R1010=open
R1011
R1012
VCC1,
VCC2
Select regulator power supply
or jack for +5.0V Regulator
power supply
VCC1, VCC2 for +5.0V Regulator power supply:
R1011=short : +5.0V regulator is used. (default)
R1012=short : Jack is used.
REG :
R1011=short
R1012=open
JP1000
TVDD-VSEL
Select regulator power supply
+3.3V or +1.8V for TVDD
TVDD for AK5538 and Logic IC:
JP1000=3.3V : +3.3V regulator is used. (default)
JP1000=1.8V : +1.8V regulator is used.
3.3V :
JP1000=3.3V
JP1001
TVDD-SEL
Select regulator power supply
or jack for TVDD
TVDD for AK5538 and Logic IC:
JP1001=REG : Regulator is used. (default)
JP1001=JACK: Jack is used.
REG :
JP1001=REG
JP1002
VDD18-SEL
Select External power supply or
LDO power supply of AK5538
for VDD18
VDD18 selector for AK5538:
JP1002=REG : External Power supply of +1.8V regulator
is used.
JP1002=JACK : External Power supply of Jack is used.
JP1002=open : LDO of AK5538 is used. (default)
LDO of AK5538 :
JP1002=open
JP1003
D33V-SEL
Select regulator power supply
or jack for D33V
D33V for AK4118A and Logic IC:
JP1003=REG : +3.3V regulator is used. (default)
JP1003=JACK : Jack is used.
REG :
JP1003=REG
JP1004
VSS-SEL
Select connection / separation
between analog ground and
digital ground.
Analog ground / digital ground short or open:
JP1004=open: Separate analog ground AVSS from digital
ground DVSS.
JP1004=short: Connect analog ground AVSS to digital
ground DVSS. (default)
Short :
JP1004=short
Table 1-2. Jumper for power supply
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[2] Jumped pins settings
No
Names
Default
Functions
1
JP600
TXDATA-SEL
COAX
Select COAX / Optical Connector for TX data of AK4118A.
COAX: COAX for TX data of AK4118A. (default)
OPT: Optical for TX data of AK4118A.
2
JP801
BICK-SEL
DIT
Select input / output to AK5538 (U100) BICK
DIT: BICK-AK4118A-T (default)
PORT: Pin Header PORT800-BICK
GND: Connected to DVSS
Open: No signal
3
JP802
LRCK-SEL
DIT
Select input / output to AK5538 (U100) LRCK
DIT: LRCK-AK4118A-T (default)
PORT: Pin Header PORT800-LRCK
GND: Connected to DVSS
Open: No signal
4
JP807
(PORT807)
BICK-PHASE
THR
Select polarity (non-inverted output / inverted output) of
BICK-SEL inputs / outputs.
THR: Non-inverted output. (default)
INV: Inverted output.
5
JP803
SDTO-SEL
SDTO1
Select input to DIT:AK4118A (U600) DAUX
SDTO1: AK5538-SDTO1 is used. (default)
SDTO2: AK5538-SDTO2 is used.
SDTO3: AK5538-SDTO3 is used.
SDTO4: AK5538-SDTO4 is used.
open: No signal for DAUX-AK4118A-T
6
JP804
TDMI-SEL
Open
Select connect to AK5538 (U100) TDMI
Open: No signal for TDMIN (default)
Short: Pin Header PORT801-TDMIN
7
JP800
MCKI-SEL
DIT
Select input to AK5538 (U100) MCLK
DIT: MCLK-AK4118A-T (default)
PORT: Pin Header PORT800-MCLK
EXT: External MCLK (JACK:J800 EXT) input.
GND: Connected to DVSS
8
JP810
EXT-T
Open
Open: No input (default)
Short: External MCLK (JACK:J800 EXT) input.
15
JP1000
TVDD-VSEL
3.3V
Select power supply voltage of TVDD
3.3V: Regulator T1003 (+5V => +3.3V) (default)
1.8V: Regulator T1004 (+5V => +1.8V)
16
JP1001
TVDD-SEL
TVDD
Select power supply to TVDD
REG: Regulator T1003/T1004 (default)
JACK: Power supply jack J1006 “TVDD”
17
JP1002
VDD18-SEL
REG
Select power supply to VDD18
REG: Regulator T1004 (default)
JACK: Power supply jack J1007 “VDD18”
18
JP1003
D33V-SEL
REG
Select power supply to D33V
REG: Regulator T1005 (+5V => +3.3V) (default)
JACK: Power supply jack J1008 “D3.3V”
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19
JP1004
VSS-SEL
Short
Select connection / separation between analog ground AVSS
and digital ground DVSS.
Open:
Separate analog ground from digital ground
Short:
Connect analog ground to digital ground (default)
Table 2. Main board Jumper pin setting
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[3] DIP switches settings
(3-1). Setting for SW600 (Sets AK4118A (U600) audio format and master clock setting)
No.
Switch Name
Function
default
1
DIF2
Set-up of DIF0 pin.
H
2
DIF1
Set-up of DIF1 pin.
L
3
DIF0
Set-up of DIF2 pin.
H
4
OCKS1
Set-up of OCKS1 pin.
H
5
OCKS0
Set-up of OCKS0 pin.
L
Table 3-1. SW600 Setting (AK4118A)
Mode
DIF2 pin
SW600-1
DIF1 pin
SW600-2
DIF0 pin
SW600-3
DAUX
LRCK
BICK
0
0
0
0
24bit, Left
justified
H/L
O
64fs
O
1
0
0
1
24bit, Left
justified
H/L
O
64fs
O
2
0
1
0
24bit, Left
justified
H/L
O
64fs
O
3
0
1
1
24bit, Left
justified
H/L
O
64fs
O
4
1
0
0
24bit, Left
justified
H/L
O
64fs
O
5
1
0
1
24bit, I2S
L/H
O
64fs
O
default
6
1
1
0
24bit, Left
justified
H/L
I
64-128fs
I
7
1
1
1
24bit, I2S
L/H
I
64-128fs
I
Table 3-2. Audio format (AK4118A)
OCKS1 pin
SW600-4
OCKS0 pin
SW600-5
(X’tal)
MCKO1
fs (max)
0
0
256fs
256fs
96 kHz
0
1
256fs
256fs
96 kHz
1
0
512fs
512fs
48 kHz
default
1
1
128fs
128fs
192 kHz
Table 3-3. Master Clock Frequency Select (AK4118A)
(3-2). Setting for SW802 (Sets AK5538 (U100) )
No.
Switch Name
Function
default
1
TEST
TEST Enable.
L
2
PW0
ADC Power Management and Monaural / Stereo select.
H
3
PW1
ADC Power Management and Monaural / Stereo select.
H
4
PW2
ADC Power Management and Monaural / Stereo select.
H
5
MSN
Master/Slave select.
L: Slave Mode
H: Master Mode
L
Table 3-4. SW802 Setting
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(3-3). Setting for SW803 (Sets AK5538 (U100) )
No.
Switch Name
Function
default
1
LDOE
LDO Enable
L: LDO Disable
H: LDO Enable
H
2
ODP
Output Data Placement Select.
L
3
HPFE/DCKS
HPFE : High Pass Filter Enable
L: HPF Disable
H: HPF Enable
DCKS : Master Clock Frequency select at DSD Mode (DSD only)
L: 512fs
H: 768fs
H
4
I2C
Control mode select
L: 3-wire serial control mode
H: I2C Bus serial control mode
H
5
TDM0
TDM Interface Format select #0
L
6
TDM1
TDM Interface Format select #1
L
7
DIF1/DSDSEL1
DIF1 : Audio Data Format select in PCM Mode
L: 24-bit Mode
H: 32-bit Mode
DSDSEL1 : DSD Sampling Rate Control in DSD Mode
L
8
DIF0/DSDSEL0
DIF0 : Audio Data Format select in PCM Mode
L: MSB justified
H: I2S
DSDSEL0 : DSD Sampling Rate Control in DSD Mode
H
9
DP
DSD Mode Enable
L: PCM Mode
H: DSD Mode
L
10
PSN
Control mode select (I2C pin =”H”)
L: I2C Bus serial control mode
H: Parallel control mode
L
Table 3-5. SW803 Setting
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(3-4). Setting for SW804 (Sets AK5538 (U100) )
No.
Switch Name
Function
default
1
CAD0-SPI
Chip Address0 Pin in 3-wire serial control mode.
(I2C pin =”L”)
L
2
CAD0-I2C
Chip Address0 Pin in I2C bus serial control mode.
(I2C pin =”H”, PS pin =”L”)
L
3
CAD1
Chip Address1 Pin in I2C bus or 3-wire serial control mode.
(3-wire : I2C pin =”L”)
(I2C bus : I2C =”H”, PS pin ”L”)
L
4
CKS0
Clock Mode Setting #0
L
5
CKS1
Clock Mode Setting #1
H
6
CKS2
Clock Mode Setting #2
H
7
CKS3
Clock Mode Setting #3
L
8
SLOW/DCKB
SLOW : Slow Roll-OFF Digital Filter select in PCM Mode
DCLKB : Polarity of DCLK in DSD Mode
L
9
SD/PMOD
SD : Short Delay Digital Filter select in PCM Mode
PMOD : DSD Phase Modulation Mode select in DSD Mode
L
10
NC
No use.
-
Table 3-6. SW804 Setting
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Parallel Mode, ODP pin = “L”, Normal Output (AK5538)
PW0 pin
SW802-2
PW1 pin
SW802-3
PW2 pin
SW802-4
Slot 8
Slot 7
Slot 6
Slot 5
Slot 4
Slot 3
Slot 2
Slot 1
L
L
L
All “0”
All “0”
All “0”
All “0”
All “0”
All “0”
All “0”
All “0”
L
L
H
(CH7+8)
/2
(CH7+8)
/2
All “0”
All “0”
(CH3+4)
/2
(CH3+4)
/2
(CH1+2)
/2
(CH1+2)
/2
L
H
L
All “0”
All “0”
(CH5+6)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH3+4)
/2
(CH1+2)
/2
(CH1+2)
/2
L
H
H
(CH7+8)
/2
(CH7+8)
/2
(CH5+6)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH3+4)
/2
(CH1+2)
/2
(CH1+2)
/2
H
L
L
All “0”
CH7
CH6
CH5
CH4
CH3
CH2
CH1
H
L
H
CH8
CH7
All “0”
All “0”
CH4
CH3
CH2
CH1
H
H
L
All “0”
All “0”
CH6
CH5
CH4
CH3
CH2
CH1
H
H
H
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
default
Table 3-7-1. Channel Power & Mono Mode Select (AK5538)
Parallel Mode, ODP pin = “H”, Normal Output (AK5538)
PW0 pin
SW802-2
PW1 pin
SW802-3
PW2 pin
SW802-4
Slot 8
Slot 7
Slot 6
Slot 5
Slot 4
Slot 3
Slot 2
Slot 1
L
L
L
All “0”
All “0”
All “0”
All “0”
All “0”
All “0”
All “0”
All “0”
L
L
H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH5+6
7+8)/4
(CH1+2
+3+4)/4
L
H
L
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH7+8)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH1+2)
/2
L
H
H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH1+2+
3+4+5+6
+7+8)/8
H
L
L
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
H
L
H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH5+6
7+8)/4
(CH1+2
+3+4)/4
H
H
L
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH7+8)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH1+2)
/2
H
H
H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH1+2+
3+4+5+6
+7+8)/8
Table 3-7-2. Channel Power & Mono Mode Select (AK5538)
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CKS3 pin
SW804-7
CKS2 pin
SW804-6
CKS1 pin
SW804-5
CKS0 pin
SW804-4
MSN pin
SW802-5
MCLK
Frequency
fs Range
L(0)
L(0)
L(0)
L(0)
L(0)
128fs
24M
Quad Speed Mode
108kHz fs 216kHz
H(1)
L(0)
L(0)
L(0)
H(1)
L(0)
192fs
36M
Quad Speed Mode
108kHz fs 216kHz
H(1)
L(0)
L(0)
H(1)
L(0)
L(0)
256fs
12M
Normal Speed Mode
8kHz fs 54kHz
H(1)
L(0)
L(0)
H(1)
H(1)
L(0)
256fs
24M
Double Speed Mode
54kHz fs 108kHz
H(1)
L(0)
H(1)
L(0)
L(0)
L(0)
384fs
36M
Double Speed Mode
54kHz fs 108kHz
H(1)
L(0)
H(1)
L(0)
H(1)
L(0)
384fs
18M
Normal Speed Mode
8kHz fs 54kHz
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
512fs
24M
Normal Speed Mode
8kHz fs 54kHz
default
H(1)
L(0)
H(1)
H(1)
H(1)
L(0)
768fs
36M
Normal Speed Mode
8kHz fs 54kHz
H(1)
H(1)
L(0)
L(0)
L(0)
L(0)
64fs
24M
Oct Speed Mode
fs = 384kHz
H(1)
H(1)
L(0)
L(0)
H(1)
L(0)
32fs
24M
Hex Speed Mode
fs = 768kHz
H(1)
H(1)
L(0)
H(1)
L(0)
L(0)
96fs
36M
Oct Speed Mode
fs = 384kHz
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
48fs
36M
Hex Speed Mode
fs = 768kHz
H(1)
H(1)
H(1)
L(0)
L(0)
L(0)
64fs
49.1M
Hex Speed Mode
fs = 768kHz
H(1)
H(1)
H(1)
L(0)
H(1)
L(0)
1024fs
32M
Normal Speed Mode
8kHz ≤fs ≤32kHz
H(1)
H(1)
H(1)
H(1)
L(0)
L(0)
NA
NA
H(1)
H(1)
H(1)
H(1)
H(1)
L(0)
Auto
8kHz fs 216kHz
-
Table 3-8. MCLK Frequency Select (AK5538)
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DSDSEL1 pin
SW803-7
DSDSEL0 pin
SW803-6
Frequency Mode
DSD Sampling Frequency
fs=32kHz
fs=44.1kHz
fs=48kHz
L(0)
L(0)
64fs
2.048MHz
2.8224MHz
3.072MHz
default
L(0)
H(1)
128fs
4.096MHz
5.6448MHz
6.144MHz
H(1)
L(0)
256fs
8.192MHz
11.2896MHz
12.288MHz
H(1)
H(1)
-
Reserved
(8.192MHz)
Reserved
(11.2896MHz)
Reserved
(12.288MHz)
Table 3-9. DSD Sampling Frequency Select (AK5538)
No.
Multiplex
Mode
Speed
Mode
TDM1
SW803-6
TDM0
SW803-5
MSN
SW802-5
DIF1
SW803-7
DIF0
SW803-8
SDTO
LRCK
BICK
MCLK
Pol.
I/O
Freq.
I/O
Freq.
I/O
0
Normal
Normal
Double
Quad
L(0)
L(0)
L(0)
L(0)
L(0)
24-bit, MSB
H/L
I
48-128fs
I
128-1024fs
I
1
L(0)
H(1)
24-bit, I2S
L/H
I
48-128fs
I
128-1024fs
I
default
2
H(1)
L(0)
32-bit, MSB
H/L
I
64-128fs
I
128-1024fs
I
3
H(1)
H(1)
32-bit, I2S
L/H
I
64-128fs
I
128-1024fs
I
4
H(1)
L(0)
L(0)
24-bit, MSB
H/L
O
64fs
O
128-1024fs
I
5
L(0)
H(1)
24-bit, I2S
L/H
O
64fs
O
128-1024fs
I
6
H(1)
L(0)
32-bit, MSB
H/L
O
64fs
O
128-1024fs
I
7
H(1)
H(1)
32-bit, I2S
L/H
O
64fs
O
128-1024fs
I
8
OCT
HEX
L(0)
L(0)
L(0)
*
L(0)
16-bit, MSB

I
32fs
I
32-96fs
I
9
*
H(1)
16-bit, I2S

I
32fs
I
32-96fs
I
10
*
L(0)
24-bit, MSB

I
48fs
I
32-96fs
I
11
*
H(1)
24-bit, I2S

I
48fs
I
32-96fs
I
12
L(0)
L(0)
24-bit, MSB

I
64fs
I
32-96fs
I
13
L(0)
H(1)
24-bit, I2S

I
64fs
I
32-96fs
I
14
H(1)
L(0)
32-bit, MSB

I
64fs
I
32-96fs
I
15
H(1)
H(1)
32-bit, I2S

I
64fs
I
32-96fs
I
16
H(1)
*
L(0)
16-bit, MSB

O
32fs
O
32fs
I
17
*
H(1)
16-bit, I2S

O
32fs
O
32fs
I
18
*
L(0)
24-bit, MSB

O
48fs
O
48fs
I
19
*
H(1)
24-bit, I2S

O
48fs
O
48fs
I
20
L(0)
L(0)
24-bit, MSB

O
64fs
O
64-96fs
I
21
L(0)
H(1)
24-bit, I2S

O
64fs
O
64-96fs
I
22
H(1)
L(0)
32-bit, MSB

O
64fs
O
64-96fs
I
23
H(1)
H(1)
32-bit, I2S

O
64fs
O
64-96fs
I
Table 3-10. Audio Interface Format Select ( Normal mode, OCT/HEX mode) : PCM Mode (AK5538)
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No.
Multiplex
Mode
Speed
Mode
TDM1
SW803-6
TDM0
SW803-5
MSN
SW802-5
DIF1
SW803-7
DIF0
SW803-8
SDTO
LRCK
BICK
MCLK
Edg.
I/O
Freq.
I/O
Freq.
I/O
24
TDM128
Normal
Double
Quad
L(0)
H(1)
L(0)
L(0)
L(0)
24-bit, MSB

I
128fs
I
128-1024fs
I
25
L(0)
H(1)
24-bit, I2S

I
128fs
I
128-1024fs
I
26
H(1)
L(0)
32-bit, MSB

I
128fs
I
128-1024fs
I
27
H(1)
H(1)
32-bit, I2S

I
128fs
I
128-1024fs
I
28
H(1)
L(0)
L(0)
24-bit, MSB

O
128fs
O
128-1024fs
I
29
L(0)
H(1)
24-bit, I2S

O
128fs
O
128-1024fs
I
30
H(1)
L(0)
32-bit, MSB

O
128fs
O
128-1024fs
I
31
H(1)
H(1)
32-bit, I2S

O
128fs
O
128-1024fs
I
32
TDM256
Normal
Double
H(1)
L(0)
L(0)
L(0)
L(0)
24-bit, MSB

I
256fs
I
256-1024fs
I
33
L(0)
H(1)
24-bit, I2S

I
256fs
I
256-1024fs
I
34
H(1)
L(0)
32-bit, MSB

I
256fs
I
256-1024fs
I
35
H(1)
H(1)
32-bit, I2S

I
256fs
I
256-1024fs
I
36
H(1)
L(0)
L(0)
24-bit, MSB

O
256fs
O
256-1024fs
I
37
L(0)
H(1)
24-bit, I2S

O
256fs
O
256-1024fs
I
38
H(1)
L(0)
32-bit, MSB

O
256fs
O
256-1024fs
I
39
H(1)
H(1)
32-bit, I2S

O
256fs
O
256-1024fs
I
40
TDM512
Normal
H(1)
H(1)
L(0)
L(0)
L(0)
24-bit, MSB

I
512fs
I
512-1024fs
I
41
L(0)
H(1)
24-bit, I2S

I
512fs
I
512-1024fs
I
42
H(1)
L(0)
32-bit, MSB

I
512fs
I
512-1024fs
I
43
H(1)
H(1)
32-bit, I2S

I
512fs
I
512-1024fs
I
44
H(1)
L(0)
L(0)
24-bit, MSB

O
512fs
O
512-1024fs
I
45
L(0)
H(1)
24-bit, I2S

O
512fs
O
512-1024fs
I
46
H(1)
L(0)
32-bit, MSB

O
512fs
O
512-1024fs
I
47
H(1)
H(1)
32-bit, I2S

O
512fs
O
512-1024fs
I
Table 3-11. Audio Interface Format Select ( TDM mode) : PCM Mode (AK5538)
SD
SW804-9
SLOW
SW804-8
Filter
L
L
Sharp Roll-off Filter
default
L
H
Slow Roll-off Filter
H
L
Short Delay Sharp Roll-off Filter
H
H
Short Delay Slow Roll-off Filter
Table 3-12. Digital Filter Select : PCM Mode (AK5538)
LDOE
SW803-1
PDN
SW800
LDO
VDD18 pin
TVDD pin
Power Supply
L
L
OFF
External Power Supply 1.7~1.98V
1.7~1.98V
L
H
OFF
External Power Supply 1.7~1.98V
1.7~1.98V
H
L
OFF
Internal 500Pull Down
3.0~3.6V
H
H
ON
LDO Power Output
3.0~3.6V
default
Table 3-13. LDO Select (AK5538)
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[AKD5538-B]
<KM131000> 2018/10
I2C pin
SW803-4
PSN pin
SW803-10
Control Mode
L
L
3-wire Serial
L
H
3-wire Serial
H
L
I2C Bus
default
H
H
Parallel
Table 3-14. Control Mode Select (AK5538)
[4] Toggle switches settings
Up=”H”, Down=”L”
[SW800] ( Power Down (PDN) for AK5538):
Power Down (PDN) Switch for AK5538
Reset AK5538 (U100) once by brining SW800 to “L” once upon power-up.
Keep “H” when AK5538 is in use; keep “L” when AK5538 is not in use.
[SW801] ( Power Down (PDN) for AK4118A):
Power Down (PDN) Switch for AK4118A
Reset AK4118A (U600) once by brining SW801 to “L” once upon power-up.
Keep “H” when AK4118A is in use; keep “L” when AK4118A is not in use.
[5] Register control (Serial control)
AKD5538-B can be controlled USB control box.
Connect board to PC using 10-wire flat cable (PORT700 –serial uP-IF) included with the AKD5538-B.
There is a mark on the no.1-pin of the 10-pin Connector. See Figure 3..
The pin assignments of PORT below.
PORT700
uP I/F
1
2
9
10
GND
GND
GND
GND
GND
CSN
CCLK / SCL
CDTI / SDA
NC
NC
Figure 3. The pin assignments of PORT700
The control software is packed with the evaluation board. The software operation sequence is included in the
evaluation board manual.
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[AKD5538-B]
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[6] Evaluation modes
(6-1) ADC Differential Analog Input Connector
ADC
Channel
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch8
8ch
J200
J201
J300
J301
J400
J401
J500
J501
6ch
J200
J201
J300
J301
J400
J401
-
-
Table 6-1. Differential Analog Input Connector
Example: 8ch ADC
1ch: Cannon Connector = J200, 2ch: Cannon Connector = J201
3ch: Cannon Connector = J300, 4ch: Cannon Connector = J301
5ch: Cannon Connector = J400, 6ch: Cannon Connector = J401
7ch: Cannon Connector = J500, 8ch: Cannon Connector = J501
(6-2) ADC (Analog Digital) : PCM Mode, Slave Mode
Toggle switch setting:
SW800
SW801
L→H
L→H
AK5538(U100) : Used
AK4118A(U600) : Used
Table 6-2-1. Toggle switch setting
Start up Control Register Setting
1: Port Reset & Write Default.
2: Set Addr: 02h = “33” to Data and Clock format on ADC. Other control register settings are default.
Mode settings : Normal Speed Mode, 24bit, I2S, MCLK=512fs
DIF1-0: Audio Data Interface Modes Select (Table 3-5, Table 3-10)
CKS3-0: Sampling Speed Mode and MCLK Frequency Select (Table 3-6, Table 3-8)
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H
Control 1
CKS3
CKS2
CKS1
CKS0
DIF1
DIF0
HPFE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
1
Table 6-2-2. Addr 02H control register setting
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(6-3) ADC (Analog Digital) : PCM Mode, Master Mode
Toggle switch setting:
SW800
SW801
L→H
L→H
AK5538(U100) : Used
AK4118A(U600) : Used
Table 6-3-1. Toggle switch setting
Start up Control Register Setting
1: Port Reset & Write Default.
2: Set Addr: 02h = “33” to Data and Clock format on ADC. Other control register settings are default.
3: Set SW802-5 =”H”(MSN pin=”H”) to Master Mode on ADC. Other switch settings are default.
Mode settings : Normal Speed Mode, 24bit, I2S, MCLK=512fs
DIF1-0: Audio Data Interface Modes Select (Table 3-5, Table 3-10)
CKS3-0: Sampling Speed Mode and MCLK Frequency Select (Table 3-6, Table 3-8)
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H
Control 1
CKS3
CKS2
CKS1
CKS0
DIF1
DIF0
HPFE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
1
Table 6-3-2. Addr 02H control register setting
(6-4) ADC (Analog Digital) : DSD Mode
Toggle switch setting:
SW800
SW801
L→H
L→H
AK5538(U100) : Used
AK4118A(U600) : Used
Table 6-4-1. Toggle switch setting
Start up Control Register Setting
1: Port Reset & Write Default.
2: Set Addr: 04h = “80” to DSD Mode on ADC. Other control register settings are default.
DP: DSD Mode Select
0: PCM Mode (default)
1: DSD Mode
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
04H
DSD1
DP
SD
SLOW
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Table 6-4-2. Addr 04H control register setting
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[AKD5538-B]
<KM131000> 2018/10
Control Software Manual
Set-up evaluation board and control software
1. Set up AKD5538-B evaluation board according to above instructions.
2. Connect PC with AKD5538-B evaluation board by USBcontrol box (included in package).
3. Insert the CD-ROM labeled “AKD5538-B Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive, double-click on “akd5538.exe” and set up the control program.
5. Evaluate according to the following.
Operation flow
1. Set up control program as above and open control program.
The following operation screen will be shown. (Default setting)
Figure7-1. Control software window
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[AKD5538-B]
<KM131000> 2018/10
2. Click the “Write” button on right side of Addr 00H register.
Figure 7-2. Register set window
3. Input dummy command settings and click “OK”to write dummy command to AK5538.
The following No Ack error message will pop up. Click “OK”.
Figure 7-3. No ack message window
4. Input registers accordingly into dialog box to evaluate AK5538.
Button Functions
1. [Port Reset] : Set up USB interface board (AKDUSBIF-B).
2. [Write Default] : Initialize all register setting.
3. [All Write] : Write all registers currently displayed.
4. [All Read] : Read all register setting.
5. [Save] : Save the current register setting to .akr file.
6. [Load] : Load register setting from saved .akr file.
7. [All Reg Write] : Opens “All Register Write” dialog box. (see Dialog boxes below)
8. [Data R/W] : Opens “Data Read/Write” dialog box . (see Dialog boxes below)
9. [Read] : Read and display current register setting in register window (on right side of main window).
Different from [All Read] as it does not reflect to the register map.
10. [Close] : Close Control Software window.
- 20-