Beijing ART Tech PXI8622 User manual

PXI8622
User’s Manual
Beijing ART Technology Co., Ltd.

PXI8622 Data Acquisition V6.0.15
Contents
Contents.............................................................................................................................................................................. 2
Chapter 1 Overview ........................................................................................................................................................... 3
Chapter 2 Components Layout Diagram and a Brief Description..................................................................................... 5
2.1 The Main Components Layout Diagram .............................................................................................................. 5
2.2 The Function Description for the Main Component............................................................................................. 5
2.2.1 Signal Input and Output Connectors ......................................................................................................... 5
2.2.2 Potentiometer............................................................................................................................................. 5
2.2.3 Physical ID of DIP Switch......................................................................................................................... 5
2.2.4 Status Light................................................................................................................................................ 6
Chapter 3 Signal Connectors............................................................................................................................................. 7
3.1 The Definition of Signal Input and Output Connectors........................................................................................ 7
Chapter 4 Connection Ways for Each Signal ..................................................................................................................... 8
4.1 AD Input Signal Connection Mode ...................................................................................................................... 8
4.1.1 AD Single-ended Input Connection Mode ................................................................................................ 8
4.1.2 AD Double-ended Input Connection Mode............................................................................................... 8
4.2 Digital Input/Output Connection Mode................................................................................................................ 8
4.4 Methods of Realizing the Multi-card Synchronization ........................................................................................ 9
Chapter 5 The Instruction of the AD Trigger Function.................................................................................................... 11
5.1 AD Internal Trigger Mode.................................................................................................................................. 11
5.2 AD External Trigger Mode................................................................................................................................. 11
Chapter 6 Methods of using AD Internal and External Clock Function.......................................................................... 14
6.1 Internal Clock Function of AD ........................................................................................................................... 14
6.2 External Clock Function of AD.......................................................................................................................... 14
6.3 Methods of Using AD Continuum and Grouping Sampling Function ............................................................... 14
6.3.1 AD Continuum Sampling Function......................................................................................................... 14
6.3.2 AD Grouping Sampling Function............................................................................................................ 15
Chapter 7 Notes, Calibration and Warranty Policy......................................................................................................... 18
7.1 Notes .................................................................................................................................................................. 18
7.2 Analog Signal Input Calibration......................................................................................................................... 19
7.3 Warranty Policy.................................................................................................................................................. 19
Products Rapid Installation and Self-check...................................................................................................................... 20
Rapid Installation ..................................................................................................................................................... 20
Self-check................................................................................................................................................................. 21
Delete Wrong Installation......................................................................................................................................... 21
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PXI8622 Data Acquisition V6.0.15
Chapter 1 Overview
In the fields of Real-time Signal Processing, Digital Image Processing and others, high-speed and high-precision data
acquisition modules are demanded. ART PXI8622 data acquisition module, which brings in advantages of similar
products that produced in China and other countries, is convenient for use, high cost and stable performance.
ART PXI8622 is a data acquisition module based on PXI bus. It can be directly inserted into IBM-PC/AT or a computer
which is compatible with PXI8622 to constitute the laboratory, product quality testing center and systems for different
areas of data acquisition, waveform analysis and processing. It may also constitute the monitoring system for industrial
production process.
Unpacking Checklist
Check the shipping carton for any damage. If the shipping carton and contents are damaged, notify the local dealer or
sales for a replacement. Retain the shipping carton and packing material for inspection by the dealer.
Check for the following items in the package. If there are any missing items, contact your local dealer or sales.
¾PXI8622 Data Acquisition Board
¾ART Disk
a) user’s manual (pdf)
b) drive
c) catalog
¾Warranty Card
FEATURES
AD analog input
¾Input Range: ±10V, ±5V, ±2.5, 0～10V, 0～5V
¾16-bit resolution
¾Sampling Rate: 1Hz～250KHz
¾Analog Input Mode: 32SE/16DI
¾Data Read Mode: non-empty, half-full inquiry mode, DMA mode and inquiry mode
¾Memory Depth: 8K word FIFO memory
¾Memory Signs: non-empty, half-full and overflow
¾AD Mode: continuum sampling , grouping sampling
¾Group Interval: software-configurable, minimum value is sampling period, maximum value is 419430uS
¾Loops of Group: software-configurable, minimum value is one time , maximum value is 255 times
¾Board Clock Output Frequency: the real sampling frequency of the current AD
¾Clock Source: external clock, internal clock( software-configurable)
¾Trigger Mode: software trigger, hardware trigger(external trigger)
¾Trigger Type: level trigger , edge trigger
¾Trigger Direction: negative, positive, positive and negative trigger
¾Trigger Source: DTR
¾Trigger Source DTR Input Range: standard TTL level
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PXI8622 Data Acquisition V6.0.15
¾AD Conversion Time: ≤10uS
¾Programmable Gain: 1, 2, 4, 8 times (AD8251)or 1, 2, 5, 10 times (AD8250) or 1, 10, 100, 1000 times
(AD8253)
¾Analog Input Impedance: 10MΩ
¾Amplifier Set-up Time: 785nS(0.001%)(max)
¾Non-linear error: ±3LSB(Maximum)
¾System Measurement Accuracy: 0.01%
¾Operating Temperature Range: 0℃ ～55℃
¾Storage Temperature Range: -20℃～70℃
DI digital input
¾Channel No.: 14-channel
¾Electric Standard: TTL compatible
¾High Voltage: ≧2V
¾Low Voltage: ≦0.8V
DO digital output
¾Channel No.: 14-channel
¾Electrical Standard: CMOS compatible
¾High Voltage: ≧4.45V
¾Low Voltage: ≦0.5V
¾Power-on Reset
Other features
Board Clock Oscillation: 40MHz
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PXI8622 Data Acquisition V6.0.15
Chapter 2 Components Layout Diagram and a Brief Description
2.1 The Main Components Layout Diagram
2.2 The Function Description for the Main Component
2.2.1 Signal Input and Output Connectors
CN1: analog signal input and output connectors
2.2.2 Potentiometer
RP1: AD analog signal input zero-point adjustment potentiometer
RP2: AD analog signal input full-scale adjustment potentiometer
2.2.3 Physical ID of DIP Switch
DID1: Set physical ID number. When the PC is installed more than one PXI8622 , you can use the DIP switch to set a
physical ID number for each board, which makes it very convenient for users to distinguish and visit each board in the
progress of the hardware configuration and software programming. The following four-place numbers are expressed by
the binary system: When DIP switch points to "ON", that means "1", and when it points to the other side, that means
"0." As they are shown in the following diagrams: place "ID3" is the high place."ID0" is the low place, and the black
part in the diagram represents the location of the switch. (Test softwares of the company often use the logic ID
management equipments and at this moment the physical ID DIP switch is invalid. If you want to use more than one
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PXI8622 Data Acquisition V6.0.15
kind of the equipments in one and the same system at the same time, please use the physical ID as much as possible. As
for the differences between logic ID and physical ID, please refer to the function explanations of "CreateDevice" and
"CreateDeviceEx" of The Prototype Explanation of Device Object Management Function in PXI8622S software
specification).
ON
1
ID0ID1ID2ID3
234
ON
DID1
The above chart shows"1111", so it means that the physical ID is 15.
ON
1
ID0ID1ID2ID3
234
ON
DID1
The above chart shows"0111", so it means that the physical ID is 7.
ON
1
ID0ID1ID2ID3
234
ON
DID1
The above chart shows"0101", so it means that the physical ID is 5.
ID3 ID2 ID1 ID0 物理ID（Hex）物理ID（Dec）
OFF（0） OFF（0） OFF（0） OFF（0） 0 0
OFF（0） OFF（0） OFF（0） ON（1） 1 1
OFF（0） OFF（0） ON（1） OFF（0） 2 2
OFF（0） OFF（0） ON（1） ON（1） 3 3
OFF（0） ON（1） OFF（0） OFF（0） 4 4
OFF（0） ON（1） OFF（0） ON（1） 5 5
OFF（0） ON（1） ON（1） OFF（0） 6 6
OFF（0） ON（1） ON（1） ON（1） 7 7
ON（1） OFF（0） OFF（0） OFF（0） 8 8
ON（1） OFF（0） OFF（0） ON（1） 9 9
ON（1） OFF（0） ON（1） OFF（0） A 10
ON（1） OFF（0） ON（1） ON（1） B 11
ON（1） ON（1） OFF（0） OFF（0） C 12
ON（1） ON（1） OFF（0） ON（1） D 13
ON（1） ON（1） ON（1） OFF（0） E 14
ON（1） ON（1） ON（1） ON（1） F 15
2.2.4 Status Light
+5VD: 5V digital power supply status light, on for normal.
OVR: FIFO overflows status light, on for overflow.
AD Read: read FIFO status light. When the light is scintillating, it shows that it is reading FIFO.
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PXI8622 Data Acquisition V6.0.15
Chapter 3 Signal Connectors
3.1 The Definition of Signal Input and Output Connectors
68-core plug on the CN1 pin definition
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
55
54
53
52
51
50
49
48
47
46
45
44
68
67
66
65
64
63
20
21
22
23
24
25
62
61
60
59
58
57
56
26
27
28
29
30
31
32
33
34
43
42
41
40
39
38
37
36
35
AI1
AI3
AI5
AI7
AI9
AI11
AI13
AI15
AI17
AI19
AI21
AI23
AI25
AI27
AI29
AI31
AGND
DGND
DI0
DI2
DI4
DI6
DI8
DI10
DI12
DO0
DO2
DO4
DO6
DO8
DO10
DO12
DTR
CLKOUT
AI0
AI2
AI4
AI6
AI8
AI10
AI12
AI14
AI16
AI18
AI20
AI22
AI24
AI26
AI28
AI30
AGND
DGND
DI1
DI3
DI5
DI7
DI9
DI11
DI13
DO1
DO3
DO5
DO7
DO9
DO11
DO13
DGND
CLKIN
Pin definition about AD:
Pin name Type Pin function definition
AI0～AI31 Input AD analog input, reference ground is AGND.
DI0～DI13 Input Digital input.
DO0～DO13 Output Digital output.
AGND Analog ground. This AGND pin should be connected to the system’s AGND plane.
DGND Digital ground. Ground reference for Digital circuitry.
CLKIN Input External clock input, please use DGND as reference ground.
CLKOUT Output Internal clock output, when allow clock output, it is internal clock output, otherwise it
is CNT counter output. DGND for reference ground.
DTR Input Digital trigger signal input, choose DGND as reference ground.
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PXI8622 Data Acquisition V6.0.15
Chapter 4 Connection Ways for Each Signal
4.1 AD Input Signal Connection Mode
4.1.1 AD Single-ended Input Connection Mode
Single-ended mode can achieve a signal input by one channel, and several signals use the common reference ground.
This mode is widely applied in occasions of the small interference and relatively many channels.
Figure 4.1.1 single-ended input connection Figure 4.1.2 double-ended input connection
4.1.2 AD Double-ended Input Connection Mode
Double-ended input mode, which was also called differential input mode, uses positive and negative channels to input a
signal. This mode is mostly used when biggish interference happens and the channel numbers are few.
Single-ended/double-ended mode can be set by the software, please refer to PXI8622 software manual.
According to the diagram below, PXI8622 board can be connected as analog voltage double-ended input mode, which
can effectively suppress common-mode interference signal to improve the accuracy of acquisition. Positive side of the
16-channel analog input signal is connected to AI0~AI15, the negative side of the analog input signal is connected to
AI16-~AI31-, equipments in industrial sites share the AGND with PXI8622 board.
4.2 Digital Input/Output Connection Mode
Figure 4.2 .1digital signal input connection Figure 4.2.2 digital signal output connection
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PXI8622 Data Acquisition V6.0.15
Figure 4.2.3 clock input / output and trigger signal connection
4.4 Methods of Realizing the Multi-card Synchronization
Three methods can realize the synchronization for the
PXI8622, the first method is using the cascade
master-slave card, the second one is using the common
external trigger, and the last one is using the common
external clock.
When using master-slave cascade card programs, the
master card generally uses the internal clock source
model, while the slave card uses the external clock
source mode. After the master card and the slave card are
initialized according to the corresponding clock source
mode. At first, start all the slave cards, as the main card
has not been activated and there is no output clock signal,
so the slave card enters the wait state until the main card
was activated. At this moment, the multi-card
synchronization has been realized. When you need to
sample more than channels of a card, you could consider
using the multi-card cascaded model to expand the
number of channels.
Slave Card 2
CLKOUT
CLKIN
CLKIN Slave Card 1
Master Card
When using the common external trigger, please make
sure all parameters of different PXI8622 are the same. At
first, configure hardware parameters, and use analog or
digital signal triggering (ATR or DTR), then connect the
signal that will be sampled by PXI8622, input triggering
signal from ART pin or DTR pin, then click “Start
Sampling” button, at this time, PXI8622 does not sample
any signal but waits for external trigger signal. When
each module is waiting for external trigger signal, use
the common external trigger signal to startup modules, at
last, we can realize synchronization data acquisition in
this way. See the following figure:
PXI8622
External Trigger Signal
DTR
DTR
DTR PXI8622
PXI8622
Note: when using the DTR, use the internal clock mode
When using the common external clock trigger, please
make sure all parameters of different PXI8622 are the
same. At first, configure hardware parameters, and use
external clock, then connect the signal that will be
sampled by PXI8622, input trigger signal from ART pin
or DTR pin, then click “Start Sampling” button, at this
time, PXI8622 does not sample any signal, but wait for
external clock signal. When each module is waiting for
external clock signal, use the common external clock
signal to startup modules, at last, we realize
synchronization data acquisition in this way. See the
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PXI8622 Data Acquisition V6.0.15
following figure:
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PXI8622 Data Acquisition V6.0.15
Chapter 5 The Instruction of the AD Trigger Function
5.1 AD Internal Trigger Mode
When AD is in the initialization, if the AD hardware parameter ADPara.TriggerMode = PXI8622_TRIGMODE_SOFT,
we can achieve the internal trigger acquisition. In this function, when calling the StartDeviceProAD function, it will
generate AD start pulse, AD immediately access to the conversion process and not wait for the conditions of any other
external hardware. It also can be interpreted as the software trigger.
As for the specific process, please see the figure below, the cycle of the AD work pulse is decided by the sampling
frequency.
F
igure 5.1 Internal Trigger Mode
The first working
pulse after the AD
start pulse
AD Start Pulse
5.2 AD External Trigger Mode
When AD is in the initialization, if the AD hardware parameter ADPara.TriggerMode = PXI8622_TRIGMODE_POST,
we can achieve the external trigger acquisition. In this function, when calling the StartDeviceProAD function, AD will
not immediately access to the conversion process but wait for the external trigger source signals accord with the
condition, then start converting the data. It also can be interpreted as the hardware trigger. Trigger source is the DTR
(Digital Trigger Source).
When the trigger signal is the digital signal (standard TTL-level), using the DTR trigger source. There are two trigger
types: edge trigger and pulse level trigger.
(1) Edge trigger function
Edge trigger is to capture the characteristics of the changes between the trigger source signal and the trigger level signal
to trigger AD conversion.
When ADPara.TriggerDir = PXI8622_TRIGDIR_NEGATIVE, choose the trigger mode as the falling edge trigger. That
is, when the DTR trigger signal is on the falling edge, AD will immediately access to the conversion process, and its
follow-up changes have no effect on AD acquisition.
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PXI8622 Data Acquisition V6.0.15
Digital Trigger Signal
The waiting time
The falling edge before
the AD started is invalid
The first falling edge after the
AD started is valid
Figure 5.2.1 Falling edge Trigger
The first working
pulse after triggered
AD Start Pulse
AD Working Pulse
When ADPara.TriggerDir = PXI8622_TRIGDIR_POSITIVE, choose the trigger mode as rising edge trigger. That is,
when the DTR trigger signal is on the rising edge, AD will immediately access to the conversion process, and its
follow-up changes have no effect on AD acquisition.
When ADPara.TriggerDir = PXI8622_TRIGDIR_POSIT_NEGAT, choose the trigger mode as rising or falling edge
trigger. That is, when the DTR trigger signal is on the rising or falling edge, AD will immediately access to the
conversion process, and its follow-up changes have no effect on AD acquisition. This function can be used in the case
that the acquisition will occur if the exoteric signal changes.
（2）Level trigger function
Level trigger is to capture the condition that trigger signal is higher or lower than the trigger level to trigger AD
conversion.
When ADPara.TriggerDir = PXI8622_TRIGDIR_NEGATIVE, it means the trigger level is low. When DTR trigger
signal is in low level, AD is in the conversion process, once the trigger signal is in the high level, AD conversion will
automatically stop, when the trigger signal is in the low level again, AD will re-access to the conversion process, that is,
only converting the data when the trigger signal is in the low level.
When ADPara.TriggerDir = PXI8622_TRIGDIR_POSITIVE, it means the trigger level is high. When DTR trigger
signal is in high level, AD is in the conversion process, once the trigger signal is in the low level, AD conversion will
automatically stop, when the trigger signal is in the high level again, AD will re-access to the conversion process, that
is, only converting the data when the trigger signal is in the high level.
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PXI8622 Data Acquisition V6.0.15
AD Working Pulse
AD Start Pulse
The waiting time
The high level before
the AD started is invalid
Figure 5.2.2 High Level Trigger
The first
p
ulse after
the AD triggered
Digital Trigger Signal
Pause
mode
When ADPara.TriggerDir = PXI8622_TRIGDIR_POSIT_NEGAT, it means the trigger level is low or high. The effect
is the same as the internal software trigger.
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PXI8622 Data Acquisition V6.0.15
Chapter 6 Methods of using AD Internal and External Clock
Function
6.1 Internal Clock Function of AD
Internal Clock Function refers to the use of on-board clock oscillator and the clock signals which are produced by the
user-specified frequency to trigger the AD conversion regularly. To use the clock function, the hardware parameters
ADPara.ClockSource = PXI8622 _CLOCKSRC_IN should be installed in the software. The frequency of the clock in
the software depends on the hardware parameters ADPara.Frequency. For example, if Frequency = 100000, that means
AD work frequency is 100000Hz (that is, 100 KHz, 10μs /point).
6.2 External Clock Function of AD
External Clock Function refers to the use of the outside clock signals to trigger the AD conversion regularly. The clock
signals are provide by the CLKIN pin of the CN1 connector. The outside clock can be provided by PXI8622 clock
output (CN1 of CLKOUT), as well as other equipments, for example clock frequency generators. To use the external
clock function, the hardware parameters ADPara.ClockSource = PXI8622_CLOCKSRC_OUT should be installed in
the software. The clock frequency depends on the frequency of the external clock, and the clock frequency on-board
(that is, the frequency depends on the hardware parameters ADPara.Frequency) only functions in the packet acquisition
mode and its sampling frequency of the AD is fully controlled by the external clock frequency.
6.3 Methods of Using AD Continuum and Grouping Sampling Function
6.3.1 AD Continuum Sampling Function
The continuous acquisition function means the sampling periods for every two data points are completely equal in the
sampling process of AD, that is, completely uniform speed acquisition, without any pause, so we call that continuous
acquisition.
To use the continuous acquisition function, the hardware parameters ADPara.ADMode = PXI8622
_ADMODE_SEQUENCE should be installed in the software. For example, in the internal clock mode, hardware
parameters ADPara.Frequency = 100000 (100KHz) should be installed, and 10 microseconds after the AD converts the
first data point, the second data point conversion starts, and then 10 microseconds later the third data point begins to
convert, and so on.
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6.3.2 AD Grouping Sampling Function
Grouping acquisition (pseudo-synchronous acquisition) function refers to the sampling clock frequency conversion
among the channels of the group in the AD sampling process, and also a certain waiting time exists between every two
groups, this period of time is known as the Group Interval. Loops of group refer to numbers of the cycle acquisition for
each channel in the same group. In the internal clock mode and the fixed-frequency external clock mode, the time
between the groups is known as group cycle. The conversion process of this acquisition mode as follows: a short time
stop after the channels conversion in the group (that is, Group Interval), and then converting the next group, followed
by repeated operations in order, so we call it grouping acquisition.
The purpose of the application of the grouping acquisition is that: at a relatively slow frequency, to ensure that all of the
time difference between channels to become smaller in order to make the phase difference become smaller, thus to
ensure the synchronization of the channels, so we also say it is the pseudo-synchronous acquisition function. In a group,
the higher the sampling frequency is, the longer Group Interval is, and the better the relative synchronization signal is.
The sampling frequency in a group depends on ADPara. Frequency, Loops of group depends on
ADPara.LoopsOfGroup, the Group Interval depend on ADPara. Group Interval.
Based on the grouping function, it can be divided into the internal clock mode and the external clock mode. Under the
internal clock mode, the group cycle is decided by the internal clock sampling period, the total number of sampling
channels, Loops of group and Group Interval together. In each cycle of a group, AD only collects a set of data. Under
the external clock mode, external clock cycle ≥internal clock sampling cycle ×the total number of sampling
channels ×Loops of group + AD chip conversion time, AD data acquisition is controlled and triggered by external
clock. The external clock mode is divided into fixed frequency external clock mode and unfixed frequency external
clock mode. Under the fixed frequency external clock mode, the group cycle is the sampling period of the external
clock.
The formula for calculating the external signal frequency is as follows:
Under the internal clock mode:
Group Cycle = the internal clock sampling period ×the total number of sample channels ×Loops of group + AD chips
conversion time + Group Interval
External signal cycle = (cycle signal points / Loops of group) ×Group Cycle
External signal frequency = 1 / external signal cycle
Under the external clock mode: (a fixed-frequency external clock)
Group Cycle = external clock cycle
External signal cycle = (cycle signal points / Loops of group) ×Group Cycle
External signal frequency = 1 / external signal cycle
Formula Notes:
The internal sampling clock cycle = 1 / (AD Para. Frequency)
The total number of sampling channels = AD Para. Last Channel – AD Para. First Channel + 1
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PXI8622 Data Acquisition V6.0.15
Loops of group == ADPara.LoopsOfGroup
AD Chips conversion time = see "AD Analog Input Function" parameter
Group Interval = AD Para. Group Interval
Signal Cycle Points = with the display of the waveform signal in test procedures, we can use the mouse to measure the
signal cycle points.
Under the internal clock mode, for example, sample two-channel 0, 1, and then 0 and 1 become a group. Sampling
frequency (Frequency) = 100000Hz (cycle is 10μs), Loops of group is 1, Group Interval = 50μs, then the acquisition
process is to collect a set of data first, including a data of channel 0 and a data of channel 1. We need 10μs to sample
the two data, 20μs to convert the data from the two channels. After the conversion time of an AD chip, AD will
automatically cut-off to enter into the waiting state until the 50μs group interval ends. We start the next group, begin to
convert the data of channel 0 and 1, and then enter into the waiting state again, and the conversion is going on in this
way, as the diagram following shows:
Start Enabled
Convert Pulse
Figure 6.1 Grouping Sampling which grouping cycle No is 1 under the Internal Clock Mode
d
a c
ba
Note: a―internal clock sample cycle
b―AD chips conversion time
c―Group Interval
d―group cycle
Change the loops of group into 2, then the acquisition process is to collect the first set of data, including two data of
channel 0 and two data of channel 1, the conversion order is 0,1,0,1. We need 10μs to sample each of the four data.
After the conversion time of an AD chip, AD will automatically stop to enter into the waiting state until the 50μs Group
Interval ends. We start the next group, begin to convert the data of channel 0 and 1, and then enter into the waiting state
again, and the conversion is going on in this way, as the diagram following shows:
Start Enabled
Convert Pulse
Figure 6.2 Grouping Sampling which grouping cycle No is 2 under the Internal Clock Mode
d
a c
ba
Notes: a―internal clock sample cycle
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PXI8622 Data Acquisition V6.0.15
b―AD chips conversion time
c―Group Interval
d―group cycle
Under the external clock mode, the requirement is: the external clock cycle ≥the internal clock sampling period ×the
total number of sampling channels×Loops of group + AD chip conversion time, otherwise, the external clock
appearing in the group conversion time will be ignored.
Under the fixed-frequency external clock mode, for example, when sampling data of two-channel 0, 1, then channel 0
and channel 1 consist of a group. Sampling frequency (Frequency) = 100000Hz (the cycle is 10μs), Loops of group is 2,
then the acquisition process is to collect the first set of data, including two data of channel 0 and two data of channel 1,
the order of conversion 0,1,0,1, We need 10μs to sample the four data and 40μs to convert of the four data. After the
conversion time of an AD chip, AD will automatically stop to enter into the waiting state until the next edge of the
external clock triggers AD to do the next acquisition, and the conversion is going on in this way, as the diagram
following shows:
The external clock before
the start pulse is ignored
External Clock
Convert Pulse
a
Figure 6.3 Grouping sampling under the fixed frequency external clock mode
Start Enabled
d
b
Notes: a―internal clock sample cycle
b―AD chips conversion time
d―group cycle（external clock cycle）
Under an unfixed-frequency external clock mode, for example, the grouping sampling principle is the same as that of
the fixed-frequency external clock mode. Under this mode, users can control any channel and any number of data.
Users will connect the control signals with the clock input of the card (CLKIN), set the sampling channels and Loops
of group. When there are external clock signals, it will sample the data which is set by users. Because the external
clock frequency is not fixed, the size of external clock cycle is inconsistent but to meet: the external clock cycle ≥
the internal clock sampling period ×the total number of sampling channels ×Loops of group + AD chip conversion
time, , otherwise, the external clock edge appearing in the group conversion time will be ignored.
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PXI8622 Data Acquisition V6.0.15
External Clock
Convert Pulse
a
Figure 6.4 Grouping sampling under the not fixed frequency external clock mode
Start Enabled
b
Note: a―internal clock sample cycle
b―AD chips conversion time
Chapter 7 Notes, Calibration and Warranty Policy
7.1 Notes
In our products’ packing, user can find a user manual, a PXI8622 module and a quality guarantee card. Users must
keep quality guarantee card carefully, if the products have some problems and need repairing, please send products
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PXI8622 Data Acquisition V6.0.15
together with quality guarantee card to ART, we will provide good after-sale service and solve the problem as quickly
as we can.
When using PXI8622, in order to prevent the IC (chip) from electrostatic harm, please do not touch IC (chip) in the
front panel of PXI8622 module.
7.2 Analog Signal Input Calibration
Every device has to be calibrated before sending from the factory. It is necessary to calibrate the module again if
users want to after using for a period of time or changing the input range. PXI8622 default input range: ±10V, in the
manual, we introduce how to calibrate PXI8622 in ±10V, calibrations of other input ranges are similar.
Prepare a digital voltage instrument which the resolution is more than 5.5 bit, install the PXI8622 module, and then
power on, warm-up for fifteen minutes.
1) Zero adjustment: select one channel of analog inputs, take the channel AI0for example, connect 0V to AI0, and
then run ART Data Acquisition Measurement Suite in the WINDOWS. Choose channel 0, ±10V input range
and start sampling, adjust potentiometer RP1 in order to make voltage value is 0.000V or about 0.000V. Zero
adjustment of other channels is alike.
2) Full-scale adjustment: select one channel of analog inputs, take the channel AI0 for example, connect
9999.69mV to AI0, and then run ART Data Acquisition Measurement Suite in the WINDOWS. Choose
channel 0, ±10V input range and start sampling, adjust potentiometer RP2 in order to make voltage value is
9999.69mV or about 9999.69mV. Full-scale adjustment of other channels is alike.
3) Repeat steps above until meet the requirement.
7.3 Warranty Policy
Thank you for choosing ART. To understand your rights and enjoy all the after-sales services we offer, please read the
following carefully.
1. Before using ART’s products please read the user manual and follow the instructions exactly. When sending in
damaged products for repair, please attach an RMA application form which can be downloaded from:
www.art-control.com.
2. All ART products come with a limited two-year warranty:
¾The warranty period starts on the day the product is shipped from ART’s factory
¾For products containing storage devices (hard drives, flash cards, etc.), please back up your data before sending
them for repair. ART is not responsible for any loss of data.
¾Please ensure the use of properly licensed software with our systems. ART does not condone the use of pirated
software and will not service systems using such software. ART will not be held legally responsible for products
shipped with unlicensed software installed by the user.
3. Our repair service is not covered by ART's guarantee in the following situations:
¾Damage caused by not following instructions in the User's Manual.
¾Damage caused by carelessness on the user's part during product transportation.
¾Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).
¾Damage from improper repair by unauthorized ART technicians.
¾Products with altered and/or damaged serial numbers are not entitled to our service.
4. Customers are responsible for shipping costs to transport damaged products to our company or sales office.
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PXI8622 Data Acquisition V6.0.15
5. To ensure the speed and quality of product repair, please download an RMA application form from our company
website.
Products Rapid Installation and Self-check
Rapid Installation
Product-driven procedure is the operating system adaptive installation mode. After inserting the disc, you can select the
appropriate board type on the pop-up interface, click the button【driver installation】; or select CD-ROM drive in
Resource Explorer, locate the product catalog and enter into the APP folder, and implement Setup.exe file. After the
installation, pop-up CD-ROM, shut off your computer, insert the PCI card. If it is a USB product, it can be directly
inserted into the device. When the system prompts that it finds a new hardware, you do not specify a drive path, the
operating system can automatically look up it from the system directory, and then you can complete the installation.
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