BitFlow Cyton-CXP Quick user guide

The Cyton-CXP
Hardware Reference Manual
BitFlow, Inc.
400 West Cummings Park, Suite 5050
Woburn, MA 01801
USA
Tel: [phone]
Fax: [phone]
Email: [email protected]
Web: www.bitflow.com
Revision A.0

© 2014 BitFlow, Inc. All Rights Reserved.
This document, in whole or in part, may not be copied, photocopied, reproduced, trans-
lated or reduced to any other electronic medium or machine readable form without the
prior written consent of BitFlow, Inc.
BitFlow, Inc. makes no implicit warranty for the use of its products and assumes no
responsibility for any errors that may appear in this document, nor does it make a commit-
ment to update the information contained herein.
BitFlow, Inc. retains the right to make changes to these specifications at any time without
notice.
All trademarks are properties of their respective holders.
Revision History:
Revision Date Comments
Pre 2013-10-10 Preliminary
A.0 2014-10-10 Synchronized with SDK 5.90

Table of Contents
BitFlow, Inc.
Table of Contents
P - Preface
Purpose CYT-P-1
Support Services CYT-P-1
Technical Support CYT-P-1
Sales Support CYT-P-1
Conventions CYT-P-2
Bitfield definitions CYT-P-3
Example Bitfield Definition CYT-P-3
Bitfield Definition Explanation. CYT-P-3
1 - General Description and Architecture
The Cyton-CXP family CYT-1-1
CoaXPress CYT-1-1
Virtual vs. Hardware CYT-1-1
The Virtual Frame Grabber (VFG) CYT-1-2
Cyton Configuration Spaces CYT-1-2
Firmware, Camera Files and Downloads CYT-1-4
General Description CYT-1-5
Video Data CYT-1-6
Command and Control Packets CYT-1-6
CXP Triggers CYT-1-6
Up Link CYT-1-6
Cyton-CXP I/O system CYT-1-7
The Timing Sequencer Signal Generator CYT-1-7
The Volume Of Interest Acquisition Engine CYT-1-7
The StreamSync System CYT-1-7
CoaXPress Power CYT-1-8
The Routing of CXP Links to VFGs CYT-1-9
The BitFlow CXP Models CYT-1-10
2 - The StreamSync Acquisition Engine
Introduction CYT-2-1
The StreamSync Acquisition Engine World CYT-2-2
Controlling the StreamSync Acquisition Engine CYT-2-2
Observing the StreamSync Acquisition Engine CYT-2-4
Synchronizing the StreamSync Acquisition Engine With the Camera CYT-2-4
Regions Of Interest (ROI) with the StreamSync Acquisition Engine. CYT-2-4
Triggering the StreamSync Acquisition Enginer CYT-2-6
Comparing the StreamSync Acquisition Engine to Other BitFlow products CYT-2-7
AE_CON CYT-2-8
AE_STATUS CYT-2-10

Table of Contents
BitFlow, Inc.
AE_STREAM_SEL CYT-2-12
V_WIN_DIM CYT-2-14
Z_WIN_CON CYT-2-16
Z_WIN_DIM CYT-2-19
Y_WIN_CON CYT-2-21
Y_WIN_DIM CYT-2-24
X_WIN_DIM CYT-2-26
V_ACQUIRED CYT-2-28
Z_ACQUIRED CYT-2-30
Y_ACQUIRED CYT-2-32
X_ACQUIRED CYT-2-34
CON489 CYT-2-36
CON490 CYT-2-38
CON548 CYT-2-40
CON549 CYT-2-42
SF_DIM CYT-2-44
SF_CON CYT-2-46
3 - The StreamSync Buffer Manager
Introduction CYT-3-1
The Buffer Manager Details CYT-3-2
CON485 Register CYT-3-3
CON486 Register CYT-3-5
BUF_MGR_CON CYT-3-7
BUF_MGR_TIMEOUT CYT-3-9
BOARD_CONFIG CYT-3-11
PACKETS_SENT_STATUS CYT-3-13
QUADS_USED_STATUS CYT-3-15
QTABS_USED_STATUS CYT-3-17
PKT_STAT CYT-3-19
QUADS_LOADED_STATUS CYT-3-22
QTABS_LOADED_STATUS CYT-3-24
BUF_MGR_STATUS CYT-3-26
PKT_CON CYT-3-29
4 - Timing Sequencer
Introduction CYT-4-1
Description CYT-4-1
TS_CONTROL CYT-4-3
TS_TABLE_CONTROL CYT-4-6
TS_TABLE_ENTRY CYT-4-8
5 - Quadrature Encoder
Introduction CYT-5-1

Table of Contents
BitFlow, Inc.
Simple Encoder Mode CYT-5-1
Positive or Negative Only Acquisition CYT-5-1
Interval Mode CYT-5-2
Re-Acquisition Prevention CYT-5-2
Scan Step Mode CYT-5-2
Combining Modes CYT-5-2
Control Registers CYT-5-2
Observability CYT-5-3
Electrical Connections CYT-5-3
Understanding Stage Movement vs. Quadrature Encoder Modes CYT-5-4
CON15 Register CYT-5-6
CON16 Register CYT-5-10
CON22 Register CYT-5-12
CON51 Register CYT-5-14
6 - Encoder Divider
Introduction CYT-6-1
Encoder Divider Details CYT-6-2
Formula CYT-6-2
Example CYT-6-2
Restrictions CYT-6-2
PLL Locking CYT-6-3
Handling Encoder Slow Down or Stopping CYT-6-3
Encoder Divider Control Registers CYT-6-4
7 - Karbon/Cyton-CXP I/O System Registers
Introduction CYT-7-1
CON60 CYT-7-2
CON61 CYT-7-4
CON62 CYT-7-6
CON63 CYT-7-10
CON64 CYT-7-15
8 - CXP Subsystem Registers
Introduction CYT-8-1
CON104 CYT-8-2
CON105 CYT-8-6
CON106 CYT-8-8
CON107 CYT-8-10
CON108 CYT-8-12
CON109 CYT-8-14
CON110 CYT-8-16
CON111 CYT-8-18
CON115 CYT-8-20

Table of Contents
BitFlow, Inc.
CON116 CYT-8-22
CON117 CYT-8-26
CON118 CYT-8-29
CON120 CYT-8-32
CON121 CYT-8-34
CON122 CYT-8-36
CON123 CYT-8-38
CON126 CYT-8-40
CON127 CYT-8-42
CON128 CYT-8-44
CON131 CYT-8-46
CON136 CYT-8-48
CON137 CYT-8-51
CON138 CYT-8-53
CON139 CYT-8-55
CON140 CYT-8-57
CON141 CYT-8-59
CON142 CYT-8-61
CON143 CYT-8-63
CON147 CYT-8-65
CON148 CYT-8-67
CON149 CYT-8-70
CON150 CYT-8-73
CON152 CYT-8-76
CON153 CYT-8-78
CON154 CYT-8-80
CON155 CYT-8-82
CON158 CYT-8-84
CON159 CYT-8-86
CON160 CYT-8-88
CON163 CYT-8-90
CON168 CYT-8-92
CON169 CYT-8-95
CON170 CYT-8-97
CON171 CYT-8-99
CON172 CYT-8-101
CON173 CYT-8-103
CON174 CYT-8-105
CON175 CYT-8-107
CON179 CYT-8-109
CON180 CYT-8-111
CON181 CYT-8-114
CON182 CYT-8-117
CON184 CYT-8-120
CON185 CYT-8-122
CON186 CYT-8-124
CON187 CYT-8-126
CON190 CYT-8-128
CON191 CYT-8-130
CON192 CYT-8-132

Table of Contents
Version Pre BitFlow, Inc. CYT-TOC-5
CON195 CYT-8-134
CON200 CYT-8-136
CON201 CYT-8-139
CON202 CYT-8-141
CON203 CYT-8-143
CON204 CYT-8-145
CON205 CYT-8-147
CON206 CYT-8-149
CON207 CYT-8-151
CON211 CYT-8-153
CON212 CYT-8-155
CON213 CYT-8-158
CON214 CYT-8-161
CON216 CYT-8-164
CON217 CYT-8-166
CON218 CYT-8-168
CON219 CYT-8-170
CON222 CYT-8-172
CON223 CYT-8-174
CON224 CYT-8-176
CON227 CYT-8-178
CON356 CYT-8-180
CON357 CYT-8-182
CON358 CYT-8-184
CON360 CYT-8-186
CON361 CYT-8-188
CON363 CYT-8-190
CON372 CYT-8-192
CON428 CYT-8-194
9 - Electrical Interfacing
Introduction CYT-9-1
Trigger CYT-9-2
Trigger Input Types CYT-9-2
The Optocoupled Trigger CYT-9-2
Encoder CYT-9-4
Encoder Input Types CYT-9-4
The Optocoupled Encoder CYT-9-4
General Purpose Inputs (GPIN) CYT-9-6
Introduction CYT-9-6
R64 GPIN Configuration CYT-9-6
Neon-CL GPIN Configuration CYT-9-6
Karbon-CL GPIN Configuration CYT-9-6
Karbon-CXP Input Configuration CYT-9-7
General Purpose Outputs (GPOUT) CYT-9-8
Introduction CYT-9-8
GPOUT Source Options (CL Only) CYT-9-8
R64 GPOUT Configuration CYT-9-8

The Cyton-CXP
CYT-TOC-6 BitFlow, Inc. Version Pre
Neon-CL GPOUT Configuration CYT-9-9
Karbon-CL GPOUT Configuration CYT-9-9
Karbon-CXP GPOUT Configuration CYT-9-10
GPOUT Open Collector Drivers CYT-9-10
Camera Link Controls (CCs) CYT-9-13
10 - Mechanical
Introduction CYT-10-1
The Cyton-CXP Connectors CYT-10-2
The CXP Connectors CYT-10-2
Switches CYT-10-3
LEDs CYT-10-5
CXP Downlink LED Meaning CYT-10-6
CXP Uplink LED Meaning CYT-10-6
Button CYT-10-7
The Auxilary Power Connector (P4) CYT-10-8
The I/O Box Connector (P1) CYT-10-9
I/O Connector Pinout for the Cyton-CXP CYT-10-10

Preface Purpose
Version A.0 BitFlow, Inc. CYT-P-1
Preface
Chapter P
P. 1 Pu r p o s e
This Hardware Reference Manual is intended for anyone using the Cyton-CXP frame
grabber. The purpose of this manual is two-fold. First, this manual completely
describes how the board works. Second, it is a reference manual describing in detail
the functionality of all of the board’s registers.
P.1.1 Support Services
BitFlow, Inc. provides both sales and technical support for the Karbon family of prod-
ucts.
P.1.2 Technical Support
Our web site is www.bitflow.com.
Technical support is available at 781-932-2900 from 9:00 AM to 6:00 PM Eastern Stan-
dard Time, Monday through Friday.
For technical support by email ([e-mail]) or by FAX [phone]),
please include the following:
Product name
Camera type and mode being used
Software revision number
Computer CPU type, PCI chipset, bus speed
Operating system
Example code (if applicable)
P.1.3 Sales Support
Contact your local BitFlow Sales Representative, Dealer, or Distributor for information
about how BitFlow can help you solve your most demanding camera interfacing
problems. Refer to the BitFlow, Inc. web site (www.bitflow.com) for a list of North
American representatives and worldwide distributors.

Purpose The Cyton-CXP
CYT-P-2 BitFlow, Inc. Version A.0
P.1.4 Conventions
Table P-1 shows the conventions that are used for numerical notation in this manual.
Table P-2 shows the numerical abbreviations that are used in this manual.
Table P-1 Base Abbreviations
Base Designator Example
Binary b 1010b
Decimal None 4223
Hexidecimal h 12fah
Table P-2 Numeric Abbreviations
Abbreviation Value Example
K 1024 256K
M 1048576 1M

Preface Bitfield definitions
Version A.0 BitFlow, Inc. CYT-P-3
P.2 Bitfield definitions
P.2.1 Example Bitfield Definition
Here is what each bitfield definition looks like:
BITFIELD R/W, CON0[7..0], Alta, Karbon-CL, Karbon-CXP, Neon, R64
Bitfield discussion.
P.2.2 Bitfield Definition Explanation.
The definitions is broken into three sections (see Table P-3).
Table P-3 Bitfield Sections.
Section Meaning
Bitfield name This is the name of the bitfield. This name is use to program
this bitfield from software or from within and camera config-
uration file. When programming bitfields from software
using a Peek or Poke function, the bitfield is preceded with
“REG_”. For example the bitfield CFREQ is referred to in
software as REG_CFREQ.
Bitfield details This section describes how the bitfield is accessed. The first
part describes the how the bits can be accessed. For exam-
ple R/W means the register can be both read and writen.
See theTable P-4 for details.The second part is the wide reg-
ister that the bitfield is located in. In the example above this
bitfield is in CON0. Following the wide register name is a
bitfield location description, in hardware engineering for-
mat. For example, [7..0], means the bitfield has 8 bits, loca-
tion in positions 0 to 7. Finally this section also indicates if
the register is specific to only one product family.
Bitfield discussion This section explains the purposed of the bitfield in detail.
Usually meaning of every possible value of the bitfield is
listed.

Bitfield definitions The Cyton-CXP
CYT-P-4 BitFlow, Inc. Version A.0
Table P-4 explains the abbreviations used in the bitfield definitions.
Table P-4 Abbreviations
Access Meaning
R/W Bitfield can be read and written.
RO Bitfield can only be read. Writing to this bit has no effect.
WO Bitfield can only be written. Reading from this bit will return
meaningless values.
Karbon-CL This bitfield is functional only the Karbon-CL.
Karbon-CXP This bitfield is functional only the Karbon-CXP.
Neon This bitfield is functional only the Neon
R64 This bitfield is functional only the R64 family.
Alta This bitfield is functional only the Alta family.
Cyton-CXP This bitfield is functional only on the Cyton-CXP family

General Description and Architecture The Cyton-CXP family
Version A.0 BitFlow, Inc. CYT-1-1
General Description and Architecture
Chapter 1
1.1 The Cyton-CXP family
The purpose of this chapter is to explain, at a block diagram level, how the Cyton-CXP
works. Currently there is two main models in the Cytron-CXP family:
CYT-PC2-CXP4, provides four 6.25 Gb/S CXP links
CYT-PC2-CXP2, provides two 6.25 Gb/S CXP links
To see how Cyton compares to the Karbon CXP models, see Section 1.5
1.1.1 CoaXPress
In order to understand how the Cyton-CXP works, it is helpful to understand the
basics of CoaXPress. It is beyond the scope of this manual to describe how CoaX-
PRess works, however, more information on the CoaXPress specification is available
from www.coaxpress.com.
1.1.2 Virtual vs. Hardware
It’s important to understand how this manual works. Some chapters of this manual dis-
cuss the Cyton-CXP as a hardware platform (this chapter is a good example). While
other chapters discuss the details of the virtual frame grabbers (VFG) that this hard-
ware platform supports. The concept of the virtual frame grabber is described below,
but basically the idea is that one hardware platform can support more than one
device. In the case of the Cyton-CXP, these devices are frame grabbers.
Note that we are not using the word virtual here in the sense of “a software virtualiza-
tion of a hardware device”, these VFGs are real hardware. The reason we using “vir-
tual” is because the term “frame grabber” has more than one meaning. It can mean
the piece of hardware that you put in your computer, or it can mean the device that
the your software application is controlling and getting images from. For the pur-
poses of this manual, “virtual frame grabber” means the device that your application
is interfaces with. While this might sound complicated, the implementation is simple.
You plug our Cyton-CXP frame grabber into your PC, and your application interacts
with one or more VFGs available. Everything else is taken care of by the BitFlow driv-
ers.

The Cyton-CXP family The Cyton-CXP
CYT-1-2 BitFlow, Inc. Version A.0
1.1.3 The Virtual Frame Grabber (VFG)
The idea behind the VFG is to separate the hardware platform (connectors, laminate,
FPGAs, etc.) from the frame grabbing functionality that software applications work
with. The primary reason behind this separation is that the turn around time for hard-
ware is much longer than the turn around time for modifying virtual frame grabbers.
To create a brand new virtual frame grabber, or to modify an existing one, simply
requires writing new firmware or updating existing firmware.
The idea of modifying a frame grabber by making changes to its firmware is not new.
BitFlow has been doing this since its very first product. However, unique to BitFlow
products is the fact the entire frame grabber is written in firmware. The only fixed
hardware components are the interfaces to the outside world (e.g. the interface chips
on the front end). Everything else that makes up the board, camera control, data buff-
ering, DMA engine, etc. is written in firmware. This gives the platform incredible levels
of flexibility and opens the door to unlimited customization.
1.1.4 Cyton Configuration Spaces
The Cyton-CXP model supports four VFGs. Each VFG appears to operating system
and your software as a separate device. Each VFG will can connect to one or more
CXP links. Figure 1-1 shows the block diagram of the for board.7

General Description and Architecture The Cyton-CXP family
Version A.0 BitFlow, Inc. CYT-1-3
Figure 1-1 The Cyton-CXP Block Diagram
Only available on
Karbon-CXP4
CXP
Connector
2
Acquitision,
Control,
I/O
0
Acquitision,
Control,
I/O
1
Acquitision,
Control,
I/O
2
Acquitision,
Control,
I/O
3
PCI
Device
0
PCI
Device
1
PCI
Device
2
PCI
Device
3
CXP
Transciever &
SERDES
CXP
Transciever &
SERDES
CXP
Transciever &
SERDES
CXP Packetizer/De-packetizer
CXP Command Packet Control
CXP Data Packet Router
CXP
Transciever &
SERDES
PCI Express Bus
CXP
Connector
3
CXP
Connector
4
CXP
Connector
1
CXP
Connector
2
Acquitision
Engine,
Control,
I/O
0
Acquitision
Engine,
Control,
I/O
1
Acquitision
Engine,
Control,
I/O
2
Acquitision
Engine,
Control,
I/O
3
PCI Interface,
Buffer Manager
0
PCI Interface,
Buffer Manager
1
PCI Interface,
Buffer Manager
2
PCI Interface,
Buffer Manager
3
CXP
Transciever &
SERDES
CXP
Transciever &
SERDES
CXP
Transciever &
SERDES
CXP Packetizer/De-packetizer
CXP Command Packet Control
CXP Data Packet Router
CXP
Transciever &
SERDES
PCI Express Bus
CXP
Connector
3
CXP
Connector
4
CXP
Connector
1

Firmware, Camera Files and Downloads The Cyton-CXP
CYT-1-4 BitFlow, Inc. Version A.0
1.2 Firmware, Camera Files and Downloads
TBD

General Description and Architecture General Description
Version A.0 BitFlow, Inc. CYT-1-5
1.3 General Description
The Cyton-CXP is a x8 PCI Express Gen 2 board. It can work in any PCI Express slot
that it can fit it. Usually this means an x8 or x16 slot. However, some mother boards
have x4 slots with x8 connectors. The Cyton-CXP will work in these slots, although
performance my be somewhat reduced. The Cyton-CXP is a Gen 2 PCIe device, but it
will work in Gen 1 slots, though DMA performance will be degraded. DMA perfor-
mance will be the same for both Gen 2 and Gen 3 slots.
The Cyton-CXP is extremely flexible. Each VFG can acquire from any of the CXP links
on the board (although certain restriction usually apply). In addition, each VFG can
acquire from one or more CXP links. This flexibility means that, for example, the
Cyton-CXP can be used as two VFGs, each acquiring from a dual link CXP camera, or
one VFG acquiring from a quad link CXP camera (in this case, the other VFGs would
not be used).
Figure 1-2 shows the block diagram of a Cyton-CXP VFG when it used with a single
link camera.
Figure 1-2 Cyton-CXP Single Link Configuration
Data
I/OI/O
PCIe
Control
Interface
Power
CXP
Physical
Layer
Acquision
Engine
De-packetizer
PCI Express Bus
I/O
Connector
Packetizer
Buffer
Manager
I/O
System
Camera
Communications
Control
CXP BNC
Connector

General Description The Cyton-CXP
CYT-1-6 BitFlow, Inc. Version A.0
1.3.1 Video Data
Three types of packets are sent from the camera on the CoaXPress downlink: Video
(stream) data, control (command) packets and Trigger packets. Video packets contain
video information (pixels). Control packets contain commands and response. The
control packets are use to read/write from/to the cameras internal register space. Trig-
ger packets are used to send triggers to the host.
Packets containing video data are sent to a stream assembler. The stream assembler
builds up lines of video data which are then sent to the acquisition and control logic
(see Figure 1-2). From this point on the Cyton-CXP works very similar to all of BitFlow’s
frame grabbers. The acquisition circuit determines which pixels of which lines of
which frames are to be acquired. The correct pixels are then sent to a FIFO, the output
of which read by the DMA engine. The DMA engine then DMAs the data to host
memory.
CoaXPress cameras can output video on multiple links simultaneously. There is no
correlation between parts of the sensor and CXP links (like there is between sensor
taps and Camera Link taps). Any part of any line can be sent on any link in a multi-link
camera. The stream assembler must decode the packet headers and assemble raster
format lines.
1.3.2 Command and Control Packets
The second type of packet coming from the camera is a control packet. When the
board sees a control packet, it unwraps the packet and sends the contents into a con-
trol data FIFO. The host then reads and decodes this FIFO. Currently (as of CoaXPress
specification 1.1) control packets are synchronous. This means that the camera will
only send a control packet in response to a control packet sent from the host. For this
reason, software can be fully under control of the control packets sent from the cam-
era. It is not necessary to have an interrupt driven control packet circuit as there is for
serial communications in Camera Link. However, this may change with future revision
os the CoaXPress specification.
1.3.3 CXP Triggers
The third type of packet the Cyton-CXP handles are the trigger packets. The camera
can send a trigger packet at any time. The Cyton-CXP maps the trigger packet into the
board’s trigger circuitry. It is one possible source for the internal trigger signal.
1.3.4 Up Link
CoaXPress provides a high speed uplink to control the camera. The uplink is also
packet based like the downlink. However, the uplink only supports two types of pack-
ets, control and Trigger. These packets are similar to the packets in the downlink. For
control packets, the BitFlow software builds up the packet in the board’s outgoing
control packet FIFO. Once the packet is fully built, a single bit sends the packet to the

General Description and Architecture General Description
Version A.0 BitFlow, Inc. CYT-1-7
camera. Trigger packets work in a similar manner, the trigger packet is a destination
for the board’s I/O system, and any number of sources can be routed to the CXP trig-
ger.
1.3.5 Cyton-CXP I/O system
The Cyton-CXP has a sophisticated I/O system, which is extremely flexible. The system
take in many inputs, routes them to a number of internal signals which can be further
manipulate, then routes the results to a wide rand of outputs. The I/O system is dis-
cuss in more detail in Section 7.1.
1.3.6 The Timing Sequencer Signal Generator
With the introduction of the Cyton-CXP, BitFlow is introducing a new signal generator,
the Timing Sequencer. The Timing Sequencer (TS) is more flexible and more power
than the timing generators used on early BitFlow frame grabbers. It has the ability to
output multiple different size pulses, each of which can free-run or require a trigger.
The TS is more accurate than the NTG and has a finer granularity. The TS can also be
changed on the fly, with switch overs to the new timing exactly synchronized. See sec-
tion 4.1 for more information.
1.3.7 The Volume Of Interest Acquisition Engine
The Cyton-CXP introduces the concept of Volume of Interest (VOI) as part of its
StreamSync Acquisition Engine. This has been designed from the ground up to satisfy
the needs of real world machine vision application. The VOI provide robust and flexi-
ble programming that can handle of a wide variety of pixel, line, frame and sequence
acquisition commands either manually from software control, or externally via hard-
ware triggers. There is fully support for X and Y offsets, X and Y Region of interests,
sequences and sequences of sequences. See section 2.2 for more information.
1.3.8 The StreamSync System
The Cyton-CXP has a brand new, designed from scratch acquisition and DMA engine
called the StreamSync system. The StreamSync system has been designed to opti-
mize acquisition and DMA throughput over the PCIe bus given a wider variety of
internal PC conditions. In addition, the Stream Sync system has been designed to
automatically resync and recover should there every be packet lost (either on the
input or the output side of the board), resulting in much more usable and fault toler-
ant image sequences in host memory. For more information see Section 2.1 and Sec-
tion 3.1.

General Description The Cyton-CXP
CYT-1-8 BitFlow, Inc. Version A.0
1.3.9 CoaXPress Power
The CoaXPress specification specifies that the frame grabber must be cable of supply-
ing up to 13 W at 24V on each CXP link. The Cyton-CXP conforms to this specification.
Some cameras do not require power, so the Cyton-CXP can optionally turn power on
or off via its registers. Normally this information is part of the camera configuration
file, thus files for cameras that require power are so indicated.
The Cyton-CXP automatically powers up all links that need power (i.e. correctly
responde to the sense circuit). This happens as soon as the system is booted.
The Cyton-CXP constantly monitors the current on each CXP link, if either over current
or under current conditions exist, the power will be turned off. The monitoring system
is purely in hardware, so no host computer intervention is required in order to safe-
guard the power source.
For situation where the camera requires more power than the PCIe bus can supply to
the frame grabber, the P4 connector can be use. This connector can be connect to the
PC’s power supply and all camera power will come from this connector.