CCS 2820 User manual

OWNER'S MANUAL
Model 2820
System Processor
d-
I
California COlDpater SystelDs

CCS MODEL 2820
SYSTEM PROCESSOR
,USER'S MANUAL
MANUAL 89000-02820 REV. A
COPYRIGHT 1981
CALIFORNIA COMPUTER SYSTEMS
250 CARIBBEAN DRIVE
SUNNYVALE CA 94086

Copyright 1981 by California Computer Systems.
All rights reserved. No part of this publication may be
reproduced in any form or by any means without express
permission of California Computer Systems.
The information contained in this manual is believed
to be correct at the time of publication. However, CCS
assumes no liability resulting from the use of this
pUblication.
Publication history:
Revision A printed March 1981
Z-80 is a trademark of Zilog, Inc.

CHAPTER 1INTRODUCTION
TABLE OF CONTENTS
1 .1 B.ASIC FEATURES ............................•.. 1-1
1.2 USING THIS MANUAL 1-3
1.3 SERVICE 1-3
1.4 SPECIFICATIONS 1-4
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
CHAPTER 3
2820 CONFIGURATION
THE CLOCK JUMPFR ........................•....
THE WAIT CONDITION AND LENGTH JUMPERS .
THE RESET JUMPER .
THE POWERFAIL JUMPER .
THE REFRESH AND MREQ JUMPFRS .
THE S 10 RCLK JUMPFR .
THE ADDRESS SELECT JUt1PERS .
THE DMA READY PIN .
THE S 10 INTERFACE JUr·1PERS .
THE INTERRUPT DAISY CHAIN PADS .
PROGRAMMING INFORMATION
2-3
2-3
2-4
2-4
2-4
2-5
2-5
2-6
2-7
2-7
3.1
3.2
3.3
3.4
3.5
THE CPU
THE DMA
THE PIa
THE CTC
THE SIO
· .
CONTROLLER ...............•...........
·.
· .
·.
3-1
3-1
3-2
3-3
3-4

THE Z-80 CPU ................•••..............
Z-80 FAMILY INTERFACING ..........•...........
THE PIa .
THE 810 .
THE eTC ......••...................•..........
THE DMA ••••••••••••••••••••••••••••••••••••••
THE INTERRUPT DAISY CHAIN .
Z-80 PERIPHERAL ADDRESSING .
BUS IMPLEMENTATION .
THE SYSTEM CLOCK .
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
2820 HARDWARE DESIGN
WAIT CIRCUITRY
4-1
4-1
4-3
4-5
4-5
4-7
4-10
4-11
4-13
4-14
4-14
APPENDIX ATECHNICAL
INFORMATION
A.1 USER-REPLACEABLE PARTS A-2
A.2 PARALLEL CABLE CONNECTOR PINOUTS '............. A-4
A.3 PARALLEL ON-BOARD CONNECTOR PINOUTS A-4
A.4 SERIAL CABLE CONNECTOR PINOUTS A-5
A.5 DEFINITION OF RS-232-C CONFIGURATIONS A-6
A.6 SIGNAL CHART FOR RS-232-C CONFIGURATIONS A-6
A.7 Z-80 CHIP PINOUTS A-7
A.8 2820 BUS OUTPUT WAVEFORMS A-8
A.9 SCHE~~TIC/LOGIC DIAGRAM A-9
APPENDIX BDAISY CHAIN CONFIGURATIONS
B.1 THE INTERRUPT DAISY CHAIN B-1
B.2 DAISY-CHAINING DMA CONTROLLERS ....•.......... B-1

CHAPTER 1
INTRODUCTION
1.1 BASIC FEATURES
The CCS 2820, the central processinq unit of the
CCS-200, 300, and 400 systems, has been desiqned to take
full advantage of high-performance Z-80 technology. Besides
the Z-80 CPU, the board features four devices designed
especially for use with the Z-80 CPU: a Parallel I/O
Controller (PIa), a Serial I/O Controller (SIO), a Clock
Timer Circuit (CTC), and a Direct Memory Access Controller
(DMA). The relationships of these devices are shown in
Figure 1.1, a block diagram of the 2820. The Z-80
support devices interface with each other with a minimum of
external logic. All four peripheral devices participate in
an interrupt daisy chain to take advantage of the powerful
interrupt-processing capabilities of the Z-80 cpu. The PIO
interface is configured for a Centronics-type printer, while
the SIO interface meets the RS-232-C specifications.
Much of the circuitry on the 2820 is' devoted to
implementation of the bus signals, adapting the Z-80 signals
to the S-100 bus. Included is a crystal-controlled clock
circuit which provides the 2 MHz bus signal and a 4 MHz
system clock.
Several hardware-selectable options incorpora~ed on the
2820 provide for flexibility in system configuration. All
options are hardwired for the standard confiquration,
eliminating preliminary set-up procedures, but users who
desire to select a non-standard option may easily do so.
User-selectable options include peripheral base addresses,
non-maskable powerfail interrupts, and automatic wait state
generation.

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INTRODUCTION
1.2 USING THIS MANUAL
1-3
Host System 200, 300, and 400 users will not find it
necessary to consult this manual; the information they
require is in the System Operation Manual for their
particular system. This manual is provided for those who
will at some time reconfigure, program, or trouble-shoot the
2820. Chapter 2 provides instructions for all of the
configuration options of the 2820. Full programming
instructions for the Z-80 family devices are provided in the
Programming Guide that is included in the documentation
package of each system. However, device implementation
often limits the programming options; such limitations of
the DHA, SIO, PIO, and CTC on the 2820 are treated in
Chapter 3. Chapter 4 and the schematic and pinouts in
Appendix A provide information necessary for
trouble-shooting the 2820.
IEEE conventions regarding signal names/mnemonics and
the identification of low-active signals by an asterisk
after the name/mnemonic (e.g., pWR*) are followed throughout
the manual.
1.3 SERVICE
If at some point you need to return your 2820 or other
CCS product to the factory for service, first write to the
Customer Service Department at the address given below to
obtain an ~1A (Return Materials Authorization) number.
Products returned without an RMA number will be refused by
the Shipping and Receiving Department.
Customer Service Department
California Computer Systems
253 Caribbean Drive
Sunnyvale Ca 94086

1-4 INTRODUCTION
1.4 SPECIFICATIONS
SIZE:
Board:
Connector:
Component Ht:
POWER SUPPLY:
+8 Volts
+16 Volts
-16 Volts
Consumption:
10" long x 5" wide
6.365" long x .3" wide"
2.125" from right of board
less than .5
11
Regulated On-Board to +5 Volts
Regulated On-Board to +12 Volts
Regulated On-Board to -12 Volts
@600 rnA at +8 V.
@100 rnA at +16 V.
@100 rnA at -16 V.
Heat Burden:
O°C. to +70°C.
less than 90%
116 gram-calories/minute
.48 BTU/minute
ENVIRONMENTAL REQUIREMENTS:
Temperature:
Humidity:
ON-BOARD DEVICES:
Z-80 CPU
Z-80 Direct Memory Access Controller
Z-80 Parallel Input/Output Controller
Z-80 Serial Input/Output Controller
Z-80 Clock/Timer Circuit
Crystal-Controlled 2and 4 MHz Clock Circuitry
INTERFACES:
System Bus:
Peripheral:
ADDITIONAL FEATURES:
S-100-Based
Jumper-Enabled MREQ* and REFRESH* lines
Two RS-232-C Serial Interfaces: DCE
Programmable Baud Rates
~e-configurabl~ for DTE
Jumperable External Clock, Port B
One Parallel Printer Interface
Centronics-Type
Separate Data and Status Ports
Relectable Peripheral Base Addresses
4 MHz Operation
Two Programmable Real-Time Clocks
Jumperable Non-Maskable Interrupt on Power Fail
On-Board Peripheral Interrupt Daisy Chain with
Look-Ahead for Off-Board Expansion
DMA Daisy Chain Capability
Jumper-Enabled Single or Double Wait State
Gefters,tion in,J:.iO,MemorYI andior HI Cycles
Low-Power Schottky and MOS Dev1ces for Minimum
Power Consumption
Sockets for All lCs
Fiberglass Epoxy (FR-4) PC Board
Solder-Masked Both Sides
Gold-Plated Connector Fingers
Silk-Screened Component Outlines, Part Desi~nations,
Refe~2nce Numbers

CHAPTER 2
CONFIGURATION
The 2820 includes a number of user-configurable
options. None of these options require configuration before
the board can be installed and operated: all are hard-wired
for standard operating parameters of Systems 200, 300, and
400. However, jumper pads have been included on the PC
board to allow selection of alternatives to some hard-wired
features. Selection of non-standard features involves the
installation of jumper pins or wires and, in most cases, the
cutting of traces on the PC board .
Fiqure 2.1 illustrates the
Individual jumpers and headers
descriptive sections that follow.
2820 jumper locations.
are illustrated in the

REFRESH
BUS LINE
JUMPER
POWERFAIL
NMI
JUMPER
WAIT STATE
LENGTH
JUMPER
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CLOCK RATE
SElECT
JUMPER
~iEAIAl NO
WAIT STATE
CONDITION
JUMPERS
RESET
SElECT
JUMPER
SIO CH. B
CLOCK
JUMPER
SIO CH. A
INTERFACE
JUMPER
PADS
MREQ
BUS LINE
JUMPER
DMA
READY
JUMPER
PAD
SIO CH. B
INTERFACE
JUMPER
PADS
ADDRESS
SELECT
JUMPER
PADS
INTERRUPT
DAISY CHAIN
JUMPER PADS
IPIO
lEO
PIO lEI
510 lEa
510 IlIEt:
.... ,E.
ODMA ,_
O':TC '"
OCTC lEt

2820 CONFIGURATION
2.1 THE CLOCK JUMPER
This jumper, present on some versions
of the 2820, controls the system clock
rate and is hard-wired for 4 MHz
operation. Most users will want to take
advanta~e of the Z-80's ability to operate
at 4HHz. However, users who have a
specific hardware or software requirement
for 2MHz operation may select a 2 MHz
system clock by cutting the trace between
the middle and 4 MHz pads and installing a
jumper wire between the middle and 2 MHz
pads. Figure 2.2 illustrates the eLK
jumper configured for a 2 MHz system
clock.
2.2 THE WAIT CONDITION AND LENGTH JUHPERS
The CPU's WAIT* input can be forced
low by anyone of three signals. The
first two, RDY and XRDY, are bus lines
controlled by peripheral devices. The
third signal is produced on-board the 2820
and controlled by four jumpers. Three
wait condition jumpers, MI, 10, and MEM,
allow insertion of waits in every machine
cycle of a given type. From 0 to 3 of
these jumpers may be installed, allowing
wait state generation to be tailored to
the elements of a system. For example,
because in HI cycles the memory access
time is about one half clock cycle shorter
than in a memory read or write cycle,
waits may be desired only during MI
cycles.
2-3
l· ...... ICLK
4 2
FIGURE 2.2
I. -IWAIT
2 1 STATE
DIO
DMEM
1-IM1
FIGURE 2.3
The \'lAIT STA.TE
cycles--l or 2--to be
of the wait state for
jumpers but does not
either RDY or XRDY is
jumper selects the number of wait
inserted. This jumper controls lenQth
all waits enabled by the wait conditon
affect wait states qenerated when
forced low. -
As
shipped, the 2820 is configured for no wait
generation, and no wait states will be necessary for any CC~
system components. However, sorne non-CCS components may
require waits. In Figure 2.3, a wait of one clock cycle in
duration is selected for all ~·~l cvcles~ no other Vl~its occur
unless generated off-boara.

2-4 2820 CONFIGURATION
2.3 THE RESET JUMPER
All devices on the 2820 share acommon
reset signal: either RESET* (bus pin 75) or
EXTERNAL CLR* (bus pin 54), depending on the
Reset jumper. Both of these signals are
controlled by the motherboard in the 2220
mainfrarne~ see the 2220 manual for an
explanation of the generation of the signals.
The 2820 is hard-wired to use EXT CLR* as its
reset signal. Users who desire to reset the
2820 with the RESET* signal may cut the EXT
CLR* trace and install a jumper wire as
illustrated in Figure 2'.4.
2.4 THE POWERFAIL JUMPER
The PWRFAIL* bus line, controlled by
circuitry on the motherboard, gives the CPU
notice of an imminent power failure. The
PWRFL jumper allows this bus line to be
connected to the CPU~s NMI* (Non-Maskable
Interrupt) input. This provides for an
immediate and unconditional jump, whenever
the power is about to fail, to an' interrupt
routine which will ensure an orderly halt to
the system1s operations.
RESET
54
1 ........ 175
XCLR PRST
FIGURE 2.4
PWRFL
EJ
FIGURE 2.5
On the 2820 as shipped from the factory,
disabled~ CCS system software does not support
option. However, some users may choose to add a
routine to their systems. Figure 2.5 illustrates
option enabled.
2.5 THE REFRESH AND MREQ JUMPERS
PWRFL is
the PWRFL
Power fail
the PWRFL
The jumpers labeled RFSH and MREQ enable REFRESH* and
MREQ* signals on bus lines 66 and 65 respectively. REFRESH*
is used by a number of dynamic RAM boards including the CCS
2065, which is part of Systems 300 and 400. Because most
users wi:l1 want to enable REFRESH'·, the jumper is hard-wired
to enable the line. To de-select the REFRESH* bus line, cut
the trace between the two jumper pads.

2820 CONFIGURATION
The MREQ* bus line is less commonly
used, but is required by some memory boards.
To enable the MREQ* line, install a jumper
wire between the two jumper pads.
As shipped from the factory, the 2820
enables REFRESH* and disables MREQ*. Figure
2.6 shows REFRESH* disabled and MREQ*
enabled.
2.6 THE SIO BCLK JUMPER
2-5
I-IMREQ
RFSHI--I
AGURE 2.6
SIO Port Bls transmitter and receiver clocks share one
input. The BCLK jumper allows that input pin to be
controlled either on-board, by CTC Channel 2, or offboard,
by the peripheral via interface line TSEC (DeE). When SIO
Port B is used as shipped (as DCE), or as DTE in
asynchronous mode, the on-board (I for Internal) clock
should be used: therefore the BCLK jumper is hard-wired for
the I option. If Port B is reconfigured as DTE and used in
synchronous mode, the clock should be 'generated by the DCE,
and therefore the BCLK jumper should be wired for the E
(External) option.
To enable the external clock, cut the I
trace and install a jumper wire between the
middle and E pads, as illustrated in Figure
2 .7.
2.7 THE ADDRESS SELECT JUMPERS
BClK 1-----1
E I
FIGURE 2.7
The base addresses of the four Z-80 peripheral devices
on board the 2820 are determined by the configuration of the
Address Select Jumpers as follows: 1) all devices are
located within a 32-address block determined by address bits
A7-A5i 2) each device occupies a 4-address block determined
by A4-A2: 3) devices need not be addressed contiguously or
in any special order: and 4) unused addresses in the
32-address block may be used by off-board devices without
interference from the 2820. As shipped, the 2820 is
configured for the following addresses: PIO, 10H-13H: DMA,
14H-17H: CTC, 18H-IBH: SIO, lCH-lFH. These addresses are
all used by the system software: therefore, it is unlikely
that the user will have occasion to change the base
addresses. However, the option is available for those who
desire it.

2-6
2820 CONFIGURATION
0
PIO
DMA
2CTC
3810
4
5
6
7
FIGURE 2.8
BASE
GROUND
00000000
None
00100000
AS
01000000
A6
01100000
A6, AS
10000000
A7
10100000
A7, AS
11000000
A7, A6
11100000 A7, A6, AS
TABLE 2.1.
BASE ADDRESS SELECTION
PIO: 10000000-10000011 (80-83H)
DMA: 10000100-10000111 (84-87H)
CTC: 10001000-10001011 (88-8BH)
SIO: 10001100-10001111 (8C-8FH)
Figure 2.8 illustrates the
Address Select Jumpers. To.
select the 32-address block in
which the four peripheral
devices will reside, solder a
wire from the appropriate
address bit pad(s), labeled
A7-AS, to the GND pad as
indicated by Table 2.1 (i.e.,
ground the pad corresponding to
each digit that is a 1). To
select a 4-address block to be
occupied by a given device,
solder a jumper wire from the
header pad labeled for that
device to the appropriate pad
on the left side of the header
as indicated by Table 2.1. The
configuration illustrated in
Figure 2.8 assigns addresses to
the Z-80 peripherals as
follows:
2 . 8 THE DMA RDY PAD
The RDY input to the Z-80 DMA Controller is used by I/O
devices to signal that they are ready for a DMA operation.
The DMA RDY pad is provided so that appropriate lines from
on-board or off-board devices may be connected to the DMA
RDY input at the user~s discretion. Use of this pad is not
mandatory, as the RDY signal may be forced via software and
is not used at all in memory-to-memory operations. When the
pad is not used, the RDY input is held high. Whether the
RDY pin is active high or active low is controlled by
software.
The RDY pad is located immediately to the left of the
RESET jumper, as illustrated in Figure 2.1.

2820 CONFIGURATION
2.9 THE SID INTERFACE JUMPERS
Both SID Port Interfaces are
RS-232-C-compatible and are hard-
wired -as Data Communication Equip-
ment (DCE). However, provision has
been made for either port to be con-
figured as Data Terminal Equipment
(DTE). On the left side of the 2820
there are two sets of 14 pads each,
arranged 2 x 7 and labeled A and B
for Ports A and B. To configure a
port for DTE, cut the traces between
the bottom four pairs of pads and
install jumper wires in a criss-cross
pattern. Figure 2.9 shows Port B
configured as DCE and Port A as DTE.
If Port B is to be configured as DTE,
the DTR and DSR traces should also be
cut and criss-cross jumper wires
installed.
2.10 THE INTERRUPT DAISY CHAIN PADS
B • •
DTR
DSR
25
TxD
28
RxD
26
RTS
23
CTS
I 24
A••
••
DSR
16
TxD ~ 12
RxD ~ 15
RTS ~ 18
CTS ~ 17
FIGURE 2.9
2-7
The interrupt daisy chain of on-board Z-80 peripherals
is hard-wired as illustrated in Fiqure 2.10 but may be
altered by the user. The hard-wired priority, from highest
to lowest, is CTC, DMA, SID, PIO. To re-configure the daisy
chain, cut the necessary traces and install the necessary
jumper wires so that: 1) the lEI of the highest-priority
device is connected to a pull-up resistor: and 2) the lEO of
the first-priority device is connected to the lEI of the
second-priority device, the lEO of the second-prior1ty
device is connected to the lEI of the third-priority device,
and the the lEO of the third-priority' device is connected to
the lEI of the fourth-priority device.

2-8
2820 CONFIGURATION
The traces between higher-priority IEOs
and lower-priority lEIs, illustrated in
Figure 2.10, are on the circuit side of the
board. The lEI of" the CTC is connected to
pin 2 of resistor pack Zl on the component
side of the board. To give another device
highest priority, first cut the trace from Zl
pin 2 before it connects with the trace from
the CTC lEI pad, then jumper the lEI pad of
the new highest-priority device to pin 20f
Zl.
PIO lEO.
PIO lEI I
SIOIEO
SIO lEI I
DMA lEO
DMA lEI I
CTCIEO
CTCIEI.
FIGURE 2.10

CHAPTER 3
PROGRAMMING INFORMATION
A general guide to programming the Z-80 devices has
been included with your system. The Programming Guide
discusses the full range of programming options for each
device. However, in many cases the implementation of a
device on a given board will limit the options available to
the programmer. This chapter describes the limitations and
special features of the Z-80 devices on the 2820 from the
programmer's point of view.
3.1 THE CPU
The 2820's CPU will respond to all Z-80 instructions as
described in the General Programming Guide and other
publications treating Z-80 programming.
3.2 THE DMA CONTROLLER
In the factory configuration, the DMA's base address is
14H. It will respond to any address between 14H and 17H.
Except for the following minor limitations, the DMA
Controller on the 2820 may be programmed as described in the
General Programming Guide and other pUblications.

3-2
PROGRAMMING INFORMATION
2820-UNIQUE PROGRAMMING CHARACTERISTICS:
1. The CE*/WAIT* option is not available: the CE*
input is controlled by the address-decoding logic
only. Therefore Bit 4 of Command Register 4
should always be cleared.
2. Unless the DMA RDY pad is jumpered by the user
to the appropriate signal from an I/O device, the
Force Ready command (written to Command Register
5) must be used for all DMA operations.
3. No circuitry on the 2820 or other CCS system
board takes advantage of the pulse which may be
generated at the INT* output after every 256 bytes
are accessed. Therefore Bits 2 and 3 of the
Interrupt Control Register should be cleared.
3.3 THE PIO
As configured at the factory, the PIO resides at base
address l0H. The addresses for the four separate ports are
as follows:
Channel A Data: l0H
Channel A Command: llH
Channel B Data: l2H
Channel B Command: l3H
The PIO on the 2820 is hardware-configured as a
Centronics-type printer interface: therefore the programming
options are considerably limited.
2820-UNIQUE PROGRAMMING CHARACTERISTICS:
1. Port A is used for outputting the data to the
printer and therefore should be programmed for
Mode 0 (Bits 7-6 of Command Register 0 cleared).
Handshaking is handled by ARDY and ASTB*
automatically: neither signal is accessible to the
programmer.

PROGRAMMING INFORMATION
2. PIO Port B is used
for four printer status
inputs, and also for
SIO Port Bls DTR input,
necessary for synchro-
nousQp~:rat:J9I1 of SIO
Port B. The status byte
format is shown at the
right.
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Bit 6:
Bit 7:
FAULT *
BUSY
PAPER EMPTY
SELECT
Always 0
Always 0
Always 0
SIO B DTR*
3-3
Port B should therefore be programmed for Mode 3
operation, with all bits programmed as inputs and
the bits not being used (Bits 7-4 when the PIO is
addressed and Bits 6-0 when SIO Port B is
addressed) set to 1 in the Mask Register.
3. The printer is reset via the INPUT PRIME* line
whenever the 2820 is reset. INPUT PRIME* is not
controllable from software.
4. Use of PIO Port 2 Bit 7 is discussed in the
SIO section.
3.4 THE eTC
As
configured at the factory, the CTC resides at base
address 18H. The four channels of the CTC are addressed as
follows:
Channel 0: 18H
Channell: 19H
Channel 2: lAH
Channel 3: IBH
The CTC is implemented on the 2820 for a special purpose:
Channel 0 provides the SIO Port A receiver and transmitter
clocks~ Channel 2 does the same for SIO Port B.
2820-UNIQUE
PROGRAMMING CHARACTERISTICS:
1. All Clock/Trigger inputs are connected to the
2 MHz clock, eliminating the counter option;
unless the wiring is modified, all four channels
operate only as timers. Therefore Bit 6 of each
Command Register should always be programmed with
a 0. Bit 4 should be programmed with a 1; Bit 3
is a don't-care bit.