CIRCUIT DESIGN STD-302 User manual

OG_STD-302-419M_v10e
OPERATION GUIDE
UHF Narrow band radio transceiver
STD-302 419MHz
Operation Guide
Version 1.0 (Jan 2004)
CIRCUIT DESIGN, INC.,
7557-1 Hotaka, Hotaka-machi,
Minamiazumi, Nagano 399-8303 JAPAN
Tel: + [phone]
Fax: + [phone]
e-mail: [email protected]
http://www.circuitdesign.jp

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OPERATION GUIDE
CONTENTS
GENERAL DESCRIPTION & FEATURES ...........................3
SPECIFICATIONS STD-302 419 MHz .............................4
PIN DESCRIPTION .............................................................5
BLOCK DIAGRAM...............................................................7
DIMENSIONS......................................................................8
PLL IC CONTROL ...............................................................9
PLL IC control ....................................................................9
How to calculate the setting values for the PLL register ........10
Method of serial data input to the PLL................................. 11
TIMING CHART.................................................................12
PLL FREQUENCY SETTING REFERENCE .....................14
REGULATORY COMPLIANCE INFORMATION ................15
CAUTIONS & WARNINGS ................................................16

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OPERATION GUIDE
GENERAL DESCRIPTION & FEATURES
General Description
The UHF FM narrow band semi-duplex radio data module STD-302 is a high performance
transceiver designed for use in industrial applications requiring long range, high performance and
reliability.
All high frequency circuits are enclosed inside a robust housing to provide superior resistance
against shock and vibration. A narrow band technique enables high interference rejection and
concurrent operation with multiple modules.
STD-302, a narrowband module with 25 kHz channel steps, achieves high TX/RX switching speed,
making it an ideal RF unit for inclusion in feedback systems.
Features
 10 mW RF power, 3.0 V operation
 Programmable RF channel
 Fast TX/RX switching time (5 ms)
 High sensitivity -119 dBm
 Excellent mechanical durability, high vibration & shock resistance
Applications
 Telem e t r y
Water level monitor for rivers, dams, etc.
Monitoring systems for environmental data such as temperature, humidity, etc.
Transmission of measurement data (pressure, revolution, current, etc) to PC
Security alarm monitoring
 Telecontrol
Industrial remote control systems
Remote control systems for factory automation machines
Control of various driving motors
 Data transmission
RS232/RS485 serial data transmission

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OPERATION GUIDE
SPECIFICATIONS
STD-302 419 MHz All ratings at 25°C unless otherwise noted
Parameter Rating Conditions
General characteristics
Communication method Semi-duplex
Oscillation type PLL Controlled VCO
Operating frequency range 418.725-419.425 MHz
Channel step Programmable
Frequency stability +/- 4 ppm -10 to +55 °C
+/- 8 ppm -20 to +65 °C
Data rate 9600 bps max. Input data pulse width: Min104µs, Max 5 ms
PLL reference frequency 21.25 MHz
Operating temperature range - 10 to + 55 °C
- 20 to + 65 °C *A
Operating voltage range 3 - 5.5 V
Dimensions 30 x 50 x 9 mm
Transmitter part
RF output power 9.0 mW Antenna impedance 50 Ω
Deviation 2.5 kHz +/-0.35 kHz PN9, 9600 bps, LPF 20 kHz
Deviation frequency
characteristics +/- 3 dB 50 - 4800 Hz
Residual FM noise 0.17 kHz LPF 20 kHz
TX S/N -30 dB 1 kHz, Dev.= +/-2.4 kHz CCITT filter
Spurious emission -60 dBm < 1 GHz
-43 dBm > 1 GHz
Adjacent channel leakage
power -37 dB CH 25 kHz, BW 16 kHz, PN9, 9600 bps
Total distortion and noise 30 dB 1 kHz, Dev.+/-2.4 kHz, CCITT filter
Consumption current 40 mA
Switching time RX to TX 5 - 10 ms RX -> TX * 1
Lock time 30 - 40 ms Free Run -> TX * 2
10 - 20 ms 25 kHz channel shift * 3
Receiver part
Reception method Double superheterodyne
Sensitivity -119 dBm (AF OUT) 1 kHz, Dev.+/-2.4 kHz, CCITT filter
Bit error rate -110 dBm (Data Out) 9600 bps, PN9 (1/2556 bit error), Internal synchronous
AF output 150+/-35 mVrms fmod.+/- 2.4 kHz, fm+/-1.2 kHz (RF level -30 dBm)
140+/-35 mVrms
fmod.+/- 2.4 kHz, fm+/-2.4 kHz (RF level -30 dBm)
120+/-45 mVrms
fmod.+/- 2.4kHz, fm+/-4.8 kHz (RF level -30 dBm)
RX S/N 35 dB 1 kHz, Dev.+/-2.4 kHz, CCITT filter (RF level -30 dBm)
Distortion -30 dB
1 kHz, Dev.+/-2.4 kHz, CCITT filter (RF level -30 dBm)
Spurious emission -60 dBm
Spurious sensitivity 45 dB Two signal method, Jamming signal = FM
Intermodulation 45 dB Two signal method
Adjacent channel selectivity 45 dB Two signal method, CH 25 kHz,
Jamming signal = FM
Consumption current 26 mA
Switching time TX to RX 5 - 10 ms TX -> RX * 1
Lock Time 30 - 40 ms Free Run -> RX * 2
10 - 20 ms 25 kHz channel shift * 3
*A Under -10°C, the time required till effective data is output from DO is longer than that at normal temperature. It is
recommended to use a preamble which is twice the length of the usual preamble. Please refer to page 12.
* 1 Time required for the TX frequency or 1st local frequency to reach within +/-1.5 ppm of a stable frequency.
* 2 Time required for the TX frequency or 1st local frequency to reach within +/-1.5 ppm of a stable frequency after PLL setting
data is output.
* 3 Time required for the TX frequency or 1st local frequency to reach within +/-1.5 ppm of a stable frequency after PLL setting
data for 25kHz shift is output.

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OPERATION GUIDE
PIN DESCRIPTION
Pin name I/O Description Equivalent circuit
RF I/O
RF input terminal
Antenna impedance nominal 50 Ω
GND I
GROUND terminal
The GND pins and the feet of the shield case
shoud be connected to the wide GND
pattern.
VCC I
Power supply terminal
DC 3.0 to 5.5 V
TXSEL I
TX select terminal
GND = TXSEL active
To enable the transmitter circuits, connect
TXSEL to GND and RXSEL to OPEN or 2.8
V.
RXSEL I
RX select terminal
GND= RXSEL active
To enable the receiver circuits, connect
RXSEL to GND and TXSEL to OPEN or 2.8
V.
AF I
Analogue output terminal
There is DC offset of approx. 1 V.
Refer to the specification table for amplitude
level.
CLK I
PLL data setting input terminal
Interface voltage H = 2.8 V, L = 0 V
DATA I
PLL data setting input terminal
Interface voltage H = 2.8 V, L = 0 V
LE I
PLL data setting input terminal
Interface voltage H = 2.8 V, L = 0 V
100nH
47P
RF
GND
SAW FILTER
REG
VCC
47P
10µ
22µ47P
2.8V
2.8V
10
TXSEL
2.8V 20K
2.8V
10
RXSEL
2.8V 20K
MB15E03
CLK
2K
MB15E03
DATA
2K
MB15E03
LE
2K

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OPERATION GUIDE
LD O
PLL lock/unlock monitor terminal
Lock = H (2.8 V), Unlock = L (0 V)
RSSI O
Received Signal Strength Indicator terminal
DO O
Data output terminal
Interface voltage: H=2.8V, L=0V
DI I
Data input terminal
Interface voltage: H=Vcc, L=0V
Input data pulse width Min.104 µs Max.5 ms
2K
MB15E03
102
2.8V
LD
102
DO
2K
10K
2.8V

OPERATION GUIDE.
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BLOCK DIAGRAM <STD-302 419 MHz>

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DIMENSIONS
Reference hole position for PCB mounting (Bottom view)
419MHz

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OPERATION GUIDE
PLL IC CONTROL
 PLL IC control
OSCin
OSCout
Vp
VCC
Do
GND
Xf in
Fin
R
PSTD-302
Control pin name
ZC
PS
LE
Data
2kohm
MB15E03SL
Reference Oscillator
LPF
Voltage Controled
Oscillator
VCO
PLL
CLK
DATA
LE
LD
LD/f out
+2.8v
#:Control v oltage = +2.8v
21.25MHz
up to 1200MHz
Figure 1
CLK
2kohm
2kohm
2kohm
STD-302 is equipped with an internal PLL frequency synthesizer as shown in Figure 1. The operation of the
PLL circuit enables the VCO to oscillate at a stable frequency. Transmission frequency is set externally by the
controlling IC. STD-302 has control terminals (CLK, LE, DATA) for the PLL IC and the setting data is sent to
the internal register serially via the data line. Also STD-302 has a Lock Detect (LD) terminal that shows the
lock status of the frequency. These signal lines are connected directly to the PLL IC through a 2 kΩresistor.
The interface voltage of STD-302 is 2.8 V, so the control voltage must be the same.
STD-302 comes equipped with a Fujitsu MB15E03SL PLL IC. Please refer to the manual of the PLL IC.
The following is a supplementary description related to operation with STD-302. In this description, the same
names and terminology as in the PLL IC manual are used, so please read the manual beforehand.

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OPERATION GUIDE
 How to calculate the setting values for the PLL register
The PLL IC manual shows that the PLL frequency setting value is obtained with the following equation.
fvco = [(M x N)+A] x fosc / R -- Equation 1
fvco : Output frequency of external VCO
M: Preset divide ratio of the prescaler (64 or 128)
N: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A: Preset divide ratio of binary 7-bit swallow counter (0 ≤A ≤127 A<N))
fosc: Output frequency of the reference frequency oscillator
R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
With STD-302, there is an offset frequency (foffset) 21.7 MHz for the transmission RF channel frequency fch.
Therefore the expected value of the frequency generated at VCO (fexpect) is as below.
fvco = fexpect = fch – foffset ---- Equation 2
The PLL internal circuit compares the phase to the oscillation frequency fvco. This phase comparison
frequency (fcomp) must be decided. fcomp is made by dividing the frequency input to the PLL from the reference
frequency oscillator by reference counter R. STD-302 uses 21.25 MHz for the reference clock fosc. fcomp is one
of 6.25 kHz, 12.5 kHz or 25 kHz.
The above equation 1 results in the following with n = M x N + A, where “n” is the number for division.
fvco=n*fcomp ---- Equation 3 n = fvco/fcomp ---- Equation 4 note: fcomp = fosc/R
Also, this PLL IC operates with the following R, N, A and M relational expressions.
R=fosc/fcomp ---- Equation 5 N = INT (n / M) ---- Equation 6 A = n - (M x N) ---- Equation 7
INT: integer portion of a division.
As an example, the setting value of RF channel frequency fch 869.725 MHz can be calculated as below.
The constant values depend on the electronic circuits of STD-302.
Conditions: Channel center frequency: fch = 869.725 MHz
Constant: Offset frequency: foffset=21.7 MHz
Constant: Reference frequency: fosc=21.25 MHz
Set 25 kHz for Phase comparison frequency and 64 for Prescaler value M
The frequency of VCO will be
fvco = fexpect = fch - foffset = 869.725 –21.7 = 848.025MHz
Dividing value “n” is derived from Equation 4
n = fvco / fcomp = 848.025MHz/25kHz = 33921
Value “R” of the reference counter is derived from Equation 5.
R = fosc/fcomp = 21.25MHz/25kHz = 850
Value “N” of the programmable counter is derived from Equation 6.
N = INT (n/M) = INT(33921/64) = 530
Value “A“ of the swallow counter is derived from Equation 7.
A = n – (M x N) = 33921 – 64 x 530 = 1
The frequency of STD-302 is locked at a center frequency fch by inputting the PLL setting values N, A and R
obtained with the above equations as serial data. The above calculations are the same for the other
frequencies.
Excel sheets that contain automatic calculations for the above equations can be found on our web site
(www.circuitdesign.jp/eng/).
The result of the calculations is arranged as a table in the CPU ROM. The table is read by the channel
change routine each time the channel is changed, and the data is sent to the PLL.