Texas Instruments KCU105 User manual

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User's Guide
SLAU711–March 2017
HSDC Pro With Xilinx®KCU105
This user's guide describes the functionality, hardware, operation, and software instructions to implement
the High Speed Data Converter Pro Graphic User Interface (HSDC Pro GUI) with the KCU105, a Xilinx®
Kintex®UltraScale™ field-programmable gate array (FPGA) evaluation kit.
Contents
1 Introduction ................................................................................................................... 3
2 Functionality .................................................................................................................. 3
3 Required Hardware.......................................................................................................... 3
3.1 Xilinx®KCU105 ..................................................................................................... 3
3.2 TI ADC/DAC Evaluation Module.................................................................................. 3
3.3 Test Equipment ..................................................................................................... 3
4 Required Software........................................................................................................... 4
4.1 HSDC Pro GUI...................................................................................................... 4
4.2 Serial Terminal Emulator .......................................................................................... 4
5 DAC and ADC GUI Configuration File Changes When Using a Xilinx®Development Platform................... 5
6 KCU105 Quick Start-Up Instructions...................................................................................... 6
6.1 USB Interface and Drivers......................................................................................... 6
6.2 Programing the FPGA.............................................................................................. 7
6.3 Adjusting FPGA FMC Settings.................................................................................... 8
6.4 IP Address and Connecting to HSDC Pro....................................................................... 8
7 Board Setup Examples.................................................................................................... 10
7.1 DAC38J84EVM with KCU105 Board Setup Example ........................................................ 10
7.2 ADC12J4000EVM With KCU105 Board Setup Example..................................................... 15
7.3 ADC32RF45EVM With KCU105 Board Setup Example ..................................................... 18
7.4 ADS54J20EVM With KCU105 Board Setup Example........................................................ 22
7.5 ADS42JB49EVM With KCU105 Board Setup Example...................................................... 25
7.6 DAC38RF82EVM With KCU105 Board Setup Example ..................................................... 27
8 Eyescan Analysis........................................................................................................... 35
List of Figures
1 TI EVM With KCU105 Block Diagram..................................................................................... 6
2 Passed Calibration in Vivado®2016.3 .................................................................................... 7
3 Setting FMC VADJ in Enhanced COM Port.............................................................................. 8
4 IP Address in Standard COM Port ........................................................................................ 9
5 HSDC Pro Connecting to KCU105........................................................................................ 9
6 DAC38J84EVM Setup With KCU105.................................................................................... 10
7 DAC38J84EVM GUI Configuration ...................................................................................... 11
8 Generating a Tone With HSDC Pro GUI ............................................................................... 12
9 Analog Output by DAC38J84EVM....................................................................................... 12
10 DAC38J84EVM GUI Configuration ...................................................................................... 13
11 DAC38J84EVM GUI DCLK Divider...................................................................................... 14
12 ADC12J4000EVM Setup With KCU105................................................................................. 15
13 Configured ADC12J4000EVM GUI ...................................................................................... 16
14 HSDC Pro ADC12J4000EVM Captured Result........................................................................ 17

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15 ADC32RF45EVM Setup With KCU105 ................................................................................. 18
16 ADC32RF45EVM GUI Quick Setup ..................................................................................... 19
17 ADC32RFEVM GUI Clock Outputs ...................................................................................... 20
18 ADC32RF45 GUI Lane De-Emphasis................................................................................... 20
19 ADC32RF45EVM Capture on HSDC Pro............................................................................... 21
20 ADS54J20EVM Setup With KCU105.................................................................................... 22
21 Configuration Files for ADS54J20EVM GUI............................................................................ 23
22 HSDC Pro ADS43J20EVM Captured Result ........................................................................... 24
23 ADS42JB49EVM Setup With KCU105.................................................................................. 25
24 HSDC Pro ADS42JB49EVM Captured Result ......................................................................... 26
25 DAC38RF82EVM Setup With KCU105 ................................................................................. 27
26 DAC38RFXX EVM GUI in External Clock Mode....................................................................... 28
27 DAC38RF82EVM GUI DCLK Divider.................................................................................... 29
28 Generating a 150-MHz Tone on HSDC Pro............................................................................ 29
29 Analog Output From DAC38RF82EVM ................................................................................. 30
30 DAC38RFXX EVM GUI in PLL Mode ................................................................................... 31
31 DAC38RF82EVM GUI NCO Frequency Settings...................................................................... 32
32 HSDC Pro Configuration for PLL Mode................................................................................. 33
33 Analog Output From DAC38RF82EVM ................................................................................. 34
34 Eye Diagram Example Plot ............................................................................................... 35
List of Tables
1 Multiplier Line Rate Ranges................................................................................................ 5
Trademarks
Altera is a registered trademark of Intel Corporation.
Silicon Labs is a registered trademark of Silicon Laboratories Incorporated.
UltraScale is a trademark of Xilinx Incorporated.
Xilinx, Kintex, Vivado are registered trademarks of Xilinx Incorporated.
All other trademarks are the property of their respective owners.

www.ti.com Introduction
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1 Introduction
The Kintex UltraScale FPGA KCU105 evaluation kit is a development board created by Xilinx. The
KCU105 uses Ethernet and dual USB-to-UART capabilities to interface with a host computer and set up
the FPGA. Texas Instruments has created a platform where the KCU105 can interface with TI’s latest and
most popular JESD204B-based high speed data converter evaluation modules (EVM) as if it were
connected to a TI development board. The platform also allows users to operate the High Speed Data
Converter Pro Graphic User Interface (HSDC Pro GUI) software to capture data from an Analog-to-Digital
converter (ADC) as well as generate data for a Digital-to-Analog converter (DAC).
2 Functionality
The KCU105 has a standard FMC connector that proves an interface between FMC-based development
boards and all TI JESD204B ADC and DAC EVMs. For communicating, the KCU105 uses Ethernet to
acquire and receive data, and do register read and writes using a host PC across a Serial Peripheral
Interface (SPI). The KCU105 has a dual USB-to-UART bridge interface for system control as well as
reading necessary information such as the board IP address. The KCU105 also has an industry-standard
JTAG connection for configuring the FPGA using the Vivado®Design Suite, a design tool by Xilinx.
The firmware designed for this integration is used to support HSDC Pro, communication through SPI, and
any TI FMC-based JESD204B EVM at any line rate. This user's guide is a starting point, but the firmware
is over complicated for designing a regular system. The firmware is located at the following Xilinx web site:
https://www.xilinx.com/member/jesd204_eval/uhwd_2016_3_v1_0.zip. The zip file includes documentation
of an example design that can be generated in Vivado 2016.3. In the Vivado project, the firmware can be
stripped down and designed for a more practical system.
NOTE: Run the command set TARGET "TI" before creating the project to generate TI bitstreams.
3 Required Hardware
3.1 Xilinx®KCU105
The Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit is required to test the TI EVMs. For KCU105
configuration and descriptions, see the product page featuring the KCU105 Evaluation Kit:
https://www.xilinx.com/products/boards-and-kits/kcu105.html.
3.2 TI ADC/DAC Evaluation Module
A TI JESD204B ADC or DAC EVM is required in the example test instructions in Section 7. For TI's EVM
programmable configuration, see the product page featuring the EVM on www.ti.com.
3.3 Test Equipment
Depending on the device under test, the follow test equipment may be required:
• Low-noise RF signal generator. Recommendations:
– HP 8644B, Rohde & Schwarz SMA100A, or equivalent
• Spectrum analyzer with RF frequency ranges. Recommendations:
– Agilent E443A, Rohde & Schwarz FSP, or equivalent
• Bandpass filters for desired analog input. Recommendations:
– Trilithic 5VH-series Tunable BPF, K&L BT-series Tunable BPF, TTE KC6 or KC7-series Fixed BPF
• Signal path cables, SMA or BNC with BNC-SMA adapters

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4 Required Software
4.1 HSDC Pro GUI
Download the latest version of the HSDC Pro GUI (slwc107x.zip) to a local directory on a host PC. This
can be found on the TI website by entering “HIGH SPEED DATA CONVERTER PRO GUI INSTALLER” in
the search parameter window at www.ti.com.
Unzipping the software package generates a folder called High Speed Data Converter Pro - Installer
vx.xx.exe, where x.xx is the version number. Run this program to start the installation.
Follow the on-screen instructions during installation.
NOTE: If an older version of the GUI has already been installed, make sure to uninstall it before
loading a newer version.
Click on the Install button. A new window opens. Click the Next button.
Accept the License Agreement. Click on Next to start the installation. After the installer has finished, click
on Next one last time.
The installation is now complete. The GUI executable and associated files will reside in the following
directory.
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro
When new TI high speed data converter EVMs or JESD204B interface modes become available that are
not currently supported by the latest release of HSDC Pro GUI, the HSDCProv_xpxx_Patch_setup
executable, available on the TI website under the High Speed Data Converter Pro Software product folder
(http://www.ti.com/tool/dataconverterpro-sw), will allow the user to add these to the GUI device list. After
the patch has been downloaded, follow the on-screen instructions to run the patch. The software displays
the files that will be added. After running the patch, open HSDC Pro and the new parts and modes will
appear in the ADC and DAC device drop-down selection box. The patch is always specific to a core GUI
version and will not work for a GUI version for which the patch was not explicitly created.
4.1.1 Xilinx®Vivado®Design Suite
The Vivado Design Suite by Xilinx, is required in order to load firmware to the FPGA. See the Vivado
Design Suite on Xilinx.com: https://www.xilinx.com/products/design-tools/vivado for more details. The
latest build that supports this integration is Vivado 2016.3.
4.2 Serial Terminal Emulator
A serial terminal emulator is required to establish a serial port connection through the KCU105 dual UART
interface. Any sort of serial terminal software, such as TeraTerm, PuTTY, or Hercules, can be used. For
this user's guide, TeraTerm is used as the main terminal emulator. See the TeraTerm web page for more
details.

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5 DAC and ADC GUI Configuration File Changes When Using a Xilinx®Development
Platform
The configuration files that come with the TI ADC and DAC EVM GUIs are set up to operate with the
Altera®based, TI TSW14J56EVM. With the latest firmware, some GUIs can be configured as if they were
connected to the TSW14J56EVM. If that is not the case, then the EVM may be configured with Xilinx-
specified configuration files or a couple of changes to the settings of the LMK0482x registers. See
Section 7 for details.
The firmware for the Xilinx Development Platforms use a separate clock input for REFCLK and core clock
to give maximum flexibility and support all line rates and subclasses with a single programmable design.
The Xilinx IP used in the firmware can be driven by a single clock in many circumstances (see the
clocking section of the Xilinx IP product guide for more details). THE REFCLK and core clock are
determined by the line rate conditions shown in Table 1.
Table 1. Multiplier Line Rate Ranges
Max Lr (Gbps) 1.2 1.6 1.9 2 2.4 3.2 3.9 4 4.9 6.5 7.9 8.1 8.2 9.8 12.512.5
Min Lr (Gbps) 1 1.20 1.60 1.90 2.00 3.20 3.01 3.90 4.00 4.90 6.50 7.90 8.10 8.20 9.80
Multiplier
2 X X
10 XXXXXXXXXXXX
20 XXXXXXXXXXXX
40 XXXXXXXX
Line rate switching is supported across the entire speed range supported by transceivers. The ratio of
REFCLK to line rate multipliers is also programmable. The multiplier is programmed by the .ini files
located in HSDC Pro. Note: REFCLK = line rate / Multiplier
Example: A line rate of 5.0G is in the range between 4.90 Gbps and 6.5 Gbps and is supported by the
multiplier values of 10, 20, and 40. Therefore, the possible values for REFCLK are:
5.0G / 10 = 500 MHz, 5.0G / 20 = 250 MHz, 5.0G / 40 = 125 MHz

Texas Instruments
ADC/DAC Evaluation Module
FMC CONNECTOR
FMC CONNECTOR
Xilinx Kintex Ultrascale
KCU105
Host Computer
Local Network
JESD204B
Interface
Serial Interface (USB)
Serial Interface (Ethernet)
UART
Interface
(USB)
JTAG
Interface
(USB)
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J4
J1
P3
J22
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6 KCU105 Quick Start-Up Instructions
The following instructions are steps to starting the Xilinx KCU105 board. These instructions are required
to establish a connection for any EVM being used.
6.1 USB Interface and Drivers
1. Connect the EVM to FMC HPC connector J22 on the KCU105.
2. Connect the power cable to the KCU105 and turn the power switch to "ON".
3. Connect the two USB cables between the KCU105 and a host computer: one between the USB to
JTAG interface J1, and the other between the dual USB-UART port J4. Ensure that Silicon Labs®
drivers are installed. See the KCU105 user guide on Xilinx.com for details about the Silicon Labs
CP2105GM dual USB-to-UART Bridge interface on the KCU105.
4. Connect a USB cable between the EVM and host computer.
5. Open a serial port connection with any serial terminal emulator.
6. Initialize a serial port communication to Silicon Labs Dual CP210x USB to UART Bridge: Enhanced
COM Port. Set the baud rate of this serial connection to "115200", and leave all other defaults as set.
7. Open another serial port connection and connect to Silicon Labs Dual CP210x USB to UART Bridge:
Standard COM Port. Ensure the baud rate of this serial connection is "9600", leaving all other defaults
as set.
8. Connect an Ethernet cord from the KCU105 to a port such as an Ethernet switch or router that is in the
same local network as the host computer. Other Ethernet interfaces are shown in the UltraScale
Hardware Demonstration user guide on Xilinx.com.
Figure 1 shows a block diagram of the set up.
Figure 1. TI EVM With KCU105 Block Diagram

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6.2 Programing the FPGA
Complete the following steps to program the FPGA:
1. Open the Xilinx Vivado 2016.3 design tool.
2. Double click on “Open Hardware Manager”.
3. Click on “Open Target” (located on the green bar), and select “Open New Target" (also at Tools →
Open New Target).
4. Click on “Next” twice. Select the Hardware Target, and click “Next” again.
5. Click on “Finish”.
6. Click on “Program device” (located on the green bar). Select "xcku040_0" (also at Tools →Program
device).
7. Select the proper bit stream file. The firmware is found in: “C:\Program Files (x86)\Texas
Instruments\High Speed Data Converter Pro\KCU105 Details\Firmware\KCU105_TI_DHCP.bit".
NOTE: If there is an error regarding ASCII characters, drag the bit file to the desktop and target the
file there.
8. Click on “Program.”
9. A new window will open showing the status of the programming. Once this reaches 100%, the FPGA is
programmed. Make sure the calibration passes and that there are no errors.
Vivado 2016.3 should look similar to Figure 2 after programming the KCU105 correctly.
Figure 2. Passed Calibration in Vivado®2016.3

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6.3 Adjusting FPGA FMC Settings
The FMC VADJ voltage must be set to 1.8V in order for the platform to work. This is set in the Enhanced
COM Port terminal.
1. Navigate to the Enhanced COM Port window. Return to the main menu by entering "0" in the terminal.
2. Enter 4to "Adjust FPGA Mezzanine Card (FMC) settings".
3. Enter 4again to "Set FMC VADJ to 1.8V".
4. Enter 0to return to the main menu.
5. To check this voltage, enter 2to "Get the Power Systems Voltages".
6. Enter 7to "Get VADJ1D8 voltage". The voltage should appear above the menu.
7. Enter 0to return to the main menu.
Figure 3 highlights setting the FMC VADJ to 1.8V in the Enhanced COM Port terminal.
Figure 3. Setting FMC VADJ in Enhanced COM Port
6.4 IP Address and Connecting to HSDC Pro
Once the firmware has been loaded and the FPGA is programmed, the board IP address and port number
will be available on the Standard COM port, shown in Figure 4.
This is required to establish a connection between the KCU105 and HSDC Pro. To connect to HSDC Pro,
do the following steps:
1. Open the HSDC Pro GUI as administrator.
2. In the "Select Board" pop up, check "Connect to KCU105". Enter the IP address followed by a colon
and port number. There is also an option to select from the drop-down menu. Both IP address and port
number can be found in the Standard COM port terminal.
3. Press "OK" to connect to the KCU105.

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Figure 4. IP Address in Standard COM Port
Figure 5 is a screenshot of HSDC Pro connecting to the KCU105.
Figure 5. HSDC Pro Connecting to KCU105

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7 Board Setup Examples
This section provides examples using the Xilinx KCU105 development platform with various JESD204B TI
EVMs. Based on the EVM, the example will show what needs to be modified in order for the integration to
work. The instructions in Section 6 must be completed before continuing with the following examples.
7.1 DAC38J84EVM with KCU105 Board Setup Example
The following section provides an example of testing the DAC38J84EVM using a KCU105 development
platform. With the updated firmware, users can use the DAC38J84 GUI as if it was connected to TI’s
TSW14J56. Make sure the instructions in Section 6 are completed before testing the EVM. Figure 6
shows a setup between the DAC38J84EVM and KCU105.
Figure 6. DAC38J84EVM Setup With KCU105

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Set up the hardware as follows:
1. Connect the power cable to the DAC38J84EVM and open the DAC3XJ8X GUI. The GUI is found
under "Software" on www.ti.com featuring the DAC38J84EVM.
2. Configure the GUI as done in the following:
(a) EVM Clocking Mode – "Onboard"
(b) DAC Data Input Rate – "1228.8" MSPS
(c) Number of SerDes Lanes per DAC – "8"
(d) Interpolation – "2"
Figure 7 is a screenshot of a configured GUI for a DAC38J84EVM 8411 JESD204B mode.
Figure 7. DAC38J84EVM GUI Configuration
3. Press the 1. Program LMK04828 and DAC3XJ8X button.
4. Open HSDC Pro, press on the DAC tab, and select "DAX3XJ84_LMF_841" from the drop-down menu.
5. Add the Data Rate (SPS) and change the DAC Option to "2’s Complement". Make sure the number of
samples is set to at least 8192, but do not exceed 32,768. Figure 8 shows a configured GUI for a
169.35-MHz tone.

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Figure 8. Generating a Tone With HSDC Pro GUI
6. Click the Create Tones button and press the Send button.
7. The new lane rate (12.288 GHz) and FPGA Clock (307.2 MHz) settings should be shown.
8. Go back to the DAC38J84 GUI and press 2. Reset DAC JESD Core and 3. Trigger LMK04828
SYSREF.
9. Connect channel one of the DAC38J84EVM to a spectrum analyzer and verify the signal.
Figure 9 shows the analog output generated by the DAC38J84EVM.
Figure 9. Analog Output by DAC38J84EVM

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7.1.1 DAC38J84EVM Second Example
In this example, the same mode is used, but a different configuration that shows the limitations of the
KCU105.
1. Configure the GUI as shown in Figure 10:
(a) EVM Clocking Mode – "Onboard"
(b) DAC Data Input Rate – "368.64" MSPS
(c) Number of SerDes Lanes per DAC – "8"
(d) Interpolation – "4"
Figure 10. DAC38J84EVM GUI Configuration

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By default, the DAC GUI is configured to generate an FPGA reference clock as line rate/40. Since the
linerate is shown to be 3.6G the valid Multiplier line rate is only supported by x10 and x20 (refer to
Table 1). In order to support this mode, the settings of the LMK04828 registers needs to be changed.
From the GUI, navigate to the LMK04828 Controls tab. Under Clock Outputs, update the DCLK Divider to
"16" in the DAC GUI as shown in Figure 11.
Figure 11. DAC38J84EVM GUI DCLK Divider
Follow the procedure in Section 7.1 beginning with step number 4 to configure HSDC Pro and produce a
tone. Note that the data rate has changed to 1474.56 MSPS.

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7.2 ADC12J4000EVM With KCU105 Board Setup Example
The following section provides an example testing the ADC12J4000EVM in bypass mode using a KCU105
development platform.
NOTE: There is a jumper "KC705 JTAG" on the ADC12J4000EVM that will prevent the firmware
from downloading if it is not shunted. By default, the board will have this jumper OPEN. The
jumper is required to be shunted in order for this integration to work. The jumper is located
on the top of the board near the FMC connector.
Make sure the instructions in Section 6 are completed before testing the EVM. Figure 12 shows a setup
between the ADC12J4000EVM and KCU105.
Figure 12. ADC12J4000EVM Setup With KCU105

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Set up the hardware as follows:
1. Connect the power supply cables and power up the ADC12J400.
2. Open the ADC12J4000 GUI. The GUI is found under "Software" on www.ti.com featuring the
ADC12J4000EVM.
3. Choose "On-board" as the Clock Source, set On-board Fs Selection to "Fs = 4000 Msps", and set
Decimation and Serial Data Mode to "Bypass Mode; DDR".
4. Click Program Clocks and ADC.Figure 13 shows a screenshot of the configured GUI.
Figure 13. Configured ADC12J4000EVM GUI

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5. Open HSDC Pro, select the ADC tab, and select "ADC12J4000_BYPASS" using the device drop-
down menu.
6. Enter "4G" in the ADC Output Data Rate window. Verify the number of samples do not exceed 32,768.
7. Click the Capture button, and the new line rate (8G) and JESD reference clock (200M) should show.
Figure 14 shows a captured result sending a 170-MHz single tone through Vin at –1 dBFS.
Figure 14. HSDC Pro ADC12J4000EVM Captured Result

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7.3 ADC32RF45EVM With KCU105 Board Setup Example
The following section provides an example testing the ADC32RF45EVM in 8224 mode using an external
clock in Bypass mode. Make sure the instructions in Section 6 are completed before testing the EVM.
Figure 15 shows a setup between the ADC32RF45EVM and KCU105.
Figure 15. ADC32RF45EVM Setup With KCU105

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Set up the hardware as follows:
1. Connect an external 2 GHz at 12-dBm source to ADC_CLK_IN (J5) of the ADC32RF45EVM.
2. Connect an external 2 GHz at 12-dBm source to LMK_CLKIN (J7) of the ADC32RF45EVM. This
source must be synchronized with the ADC_CLK_IN source.
3. Connect the power supply cable to the EVM and open the ADC32RFxx EVM GUI. The GUI is found
under "Software" on www.ti.com featuring the ADC32RF45EVM.
4. Go to the Quick Setup tab and configure the GUI as shown in Figure 16:
(a) Clock Source to ADC – "External Clocking"
(b) ADC32RF45 Mode – "Bypass"
(c) BYPASS – "14 bit"
Figure 16. ADC32RF45EVM GUI Quick Setup
5. Click on PROGRAM EVM.
6. Go to the Clock Outputs tab under the LMK04828 tab.
7. Verify CLKout 0 and 1 divider is set to "8" as shown in Figure 17.

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Figure 17. ADC32RFEVM GUI Clock Outputs
8. Click on the SYSREF and SYNC tab. Verify the SYSREF Divider is set to "1024".
9. In the ADC Configuration tab under ADC32RFxx, set the JESD204b Lane De-emphasis setting to "0"
dB for all lanes, as shown in Figure 18.
Figure 18. ADC32RF45 GUI Lane De-Emphasis