DRAM optimization feature: If a memory read is addressed to a location whose latest write is being
held in a buffer before being written to memory, the read is satisfied through the buffer contents, and
the read is not sent to the DRAM.
3.4.8 System BIOS Cacheable
Allows the system BIOS to be cached for faster system performance.
3.4.9 Video RAM Cacheable
Enabled allows caching of the video RAM, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
3.4.10 AGP Aperture Size
Choose 4, 8, 16, 32, 64, 128MB. Memory-mapped, graphics data structures can reside in the
Graphics Aperture.
3.4.11 AGP-4X Mode
Set to Enabled if your AGP card supports the 4X mode, which transfers video data at 1066MB/s.
3.4.12 AGP Driving Control
This item is use for control AGP drive strength.
Auto: Setup AGP drive strength by default setting.
Manual: Setup AGP drive strength by manual setting.
3.4.13 AGP Driving Value
Key in a HEX number to control AGP output buffer drive strength. Min = 00, Max = FF.
3.4.14 OnChip USB
If your system contains a Universal Serial Bus controller and you have a USB peripheral, select
Enabled. The next option will become available.
3.4.15 USB Keyboard Support
This item lets you enable or disable the USB keyboard driver within the onboard BIOS.
3.4.16 OnChip Sound/Modem
Allows the motherboard's BIOS to detect whether you are using any sound/modem device. If a
sound/modem device is detected, the onboard sound/modem controller will be enabled; if no sound
/modem is detected, the onboard sound /modem controller will be disabled. If you want to use
different controller cards to connect sound and modem connectors, set these fields to Disabled.
3.4.17 CPU to PCI Write Buffer
When enabled, up to four D words of data can be written to the PCI bus without interrupting the CPU.
When disabled, a write buffer is not used and the CPU read cycle will not be completed until the PCI
bus signals that it is ready to receive the data.
3.4.18 PCI Dynamic Bursting
When enabled, data transfer on the PCI bus, where possible, make use of the high-performance PCI
bust protocol, in which greater amounts of data are transferred at a single command.
3.4.19 PCI Master 0 WS Write
When enabled, writes to the PCI bus are command with zero wait states.
3.4.20 PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select
Enabled to support compliance with PCI specification version 2.1.