Commodore C-128 User manual

SERVICE MANUAL
MODEL C-128 COMPUTER
Preliminary
AUGUST 1985
PN-314001-07
Commodore Business Machines, Inc.
1200 Wilson Drive, West Chester, Pennsylvania 19380 U.S.A.
Commodore makes no expressed or implied war-
ranties with regard to the information contained
herein. The information is made available solely on
an as is basis, and the entire risk as to quality and
accuracy is with the user. Commodore shall not be
liable for any consequential or incidental damages
in connection with the use of the information con-
tained herein. The listing of any available refJlace-
ment part herein does not constitute in any c:;>se
a recommendation, warranty or guaranty as .,'C'"
quality or suitability of such replacement part.
Reproduction or use without expressed permission,
of editorial or pictorial content, in any matter is
prohibited.
This manual contains copyrighted and proprietary information. No part
of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, electronic, mechanical,
photocopying, recording or otherwise, without the prior written permis-
sion of Commodore Electronics Limited.
Copyright © 1985 by Commodore Electronics Limited.

CONTENTS
Title
Page
SPECIFICATIONS 1
2
3
PARTS LIST ........................................................................................................ ..
BLOCK DIAGRAM
................................................................................................ .
THEORY
BUS ARCHITECTURE ................................................................................... 4
8502 MICROPROCESSOR ............................................................................ 6
Z-80 MICROPROCESSOR ............................................................................. 8
MEMORY ARCHITECTURE
............................................................................ 11
READ ONLY MEMORY ................................................................................. 15
RANDOM ACCESS MEMORY ........................................................................ 17
MEMORY MANAGEMENT UNIT .................................................................... 20
PROGRAMMED LOGIC ARRAy...................................................................... 28
8701 CLOCK GENERATOR ........................................................................... 30
VIDEO INTERFACE ....... .................................................................. ............. 31
8564 VIDEO INTERFACE CHIP ...................................................................... 33
8563 VIDEO CONTROLLER ............................ .............................................. 36
I/O -INPUT/OUTPUT CIRCUITS ................................................................... 39
CASSETTE INTERFACE ................................................................................ 39
KEYBOARD ................................................................................................. 41
EXPANSION BUS ......................................................................................... 42
SERIAL BUS ................................................................................................ 44
TROUBLESHOOTING
COMMON
LINE DEFINITIONS........................................................................ 46
COMMON I.C.'S (PIN ASSIGNMENTS & LOGIC) .................. ........................... 47
INITIAL SERVICE POLICY ............................................................................. 53
PCB
PCB ASSEMBLY #310379 REV. 6
BOARD
LAyOUT................................................................................... 54
PARTS LIST ......................................................................................... 55
SCHEMATIC DRAWINGS
....................................................................... 57
PCB ASSEMBLY #310379 REV. 7
BOARD LAYOUT
................................................................................... 61
PARTS LIST ......................................................................................... 62
SCHEMATIC DRAWINGS ....................................................................... 64
RF MODULATOR NTSC ................................................................................ 68

COMMODORE 128
GENERAL FEATURES
64 MODE
128 MODE
CP/M MODE
KEYBOARD
INPUTS/OUTPUTS
RECOMMENDED
PERIPHERALS
POWER REQUIREMENTS
PERSONAL COMPUTER
• Advanced Styling • 100% Compatible with Commodore 64
• Built-in, Easy to Use DOS support • RAM Expandable up to 512K
RAM Using RAM Disk Option • Upper and Lower Case Character
Set
• Built-in BASIC • 3 Separate Modes
of Operation
•
8502 Microprocessor (6502/6510 Compatible) • 6581 Sound
Interface Chip •
64K RAM • 16K ROM • BASIC 2.0 • 40 x 25
Lines (320 x 200 resolution) • 16 Colors + 8 Sprites
•
8502 Microprocessor (6502/6510 Compatible)
• 6581 Sound Interface Chip •
128K RAM (Expandable to 512K
Using RAM Disk Option) • 48K ROM + 16K ROM for DOS
Support
• BASIC
7.0 • Machine Language Monitor • 40 x 25 Lines (320 x
200 resolution) • 80 x 25 Lines (640 x 200 resolution) • 16
Colors + 8 Sprites (40 Column Only)
•
Z80 Microprocessor • CP/MTM Plus Version 3.0
• 128K RAM (Expandable to 512K Using RAM Disk Option)
•
40 x 25 Lines (320 x 200 resolution) • 80 x 25 Lines
(640 x
200 resolution) • 16 Colors
•
Full Size Typewriter Style • 92 Keys • 14 Key Numeric Keypad
• 8 Programmable Function Keys • 6 Cursor Keys • Help Key
•
40/80 Column Key • No Scroll • Line Feed • Escape • Tab
•
Cap Lock • Alt (Not all accessible in 64 Mode)
• User Port • Serial Port
• Cassette Port • 2
Game Ports
• RF/TV Port • Cartridge Port
• Audio Input • Audio Output
• Composite Video • Digital
RGBI Video
•
MPS 802, MPS 803, MPS 1000 Printers
• 1
541, 1571 Single Disk Drive
• 1901 Monochrome Monitor •
1902 Digital RGBI Color Monitor
•
1660 and 1670 Modems • Fully Compatible with Commodore 64
Software and Accessories in 64 Mode
• 117 Volts AC,
60 Hz, 15 Watts
tSpecifications subject to change without notice
'CP/M is a registered trademark of Digital Research. Inc.
1

PARTS LIST
C-128
PLEASE NOTE: Commodore part numbers are provided for reference only and do not
indicate the availability of parts from Commodore. Industry standard parts (Resistors,
Capacitors, Connectors) should be secured locally. Approved cross-references for
TTL chips,
Transistors, etc. are available in manual
form through the Service Department. Unique or
non-standard parts will be stocked by Commodore and are indicated on the parts list by a
"C".
TOP CASE ASSY
Top Case C
251987-01
Keyboard C
310401-01
Nameplate C
310400-01
Lamp Holder Set C
252013-01
LED Assembly C
250754-01
BOTTOM CASE ASSY
Bottom Case C
251988-01
Foot, Self-Adhesive C
251993-01
PCB Top Shield C 252015-01
PCB Bottom Shield C 252016-01
PCB Insulation Sheet C 252017-01
ACCESSORIES
Users Manuals
Introductory Guide C
319773-01
System Guide C
310638-01
Power Supply C
310416-01
RF Cable C
326189-01
Switch Box C
904778-01
Tutorial Diskette C
317667-01
CP/M Diskette # 1 C
317430-01
CP/M Diskette # 2 C
317431-01
2

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E'

BUS ARCHITECTURE
FOLD OUT SCHEMATIC PAGES 64-67 FOR EASY REFERENCE.
The Processor Bus
The Processor Bus is
the data and address buses that are directly connected to the 8502 processor.
These buses are designated
DO - 07 for the eight bit data bus and AO -A 15 for the sixteen bit address
bus. These buses tie
the processor to most of the system ROM and 1/0 devices, including at least
part
of all System ROM, all built-in Function ROM, the MMU, the PLA, the 8563 Video Processor,
the SID, and both CIA chips.
The Processor Bus is
in direct communication with the Z-80 co-processor as well. All address lines
are shared
directly by both processors. In order to allow the Z-80 to operate on a 6502 family bus,
it is necessary to latch data going into the Z-80 and gate the data leaving the Z-80. Thus, the Z-80
has a small local data bus, designated ZOO -ZD7. During a write cycle, when AEC is high, Z-80 data
is gated
to the Processor Bus. During a read cycle, Processor Bus data is gated to the Z-80 data bus.
This read data is
transparently latched by the 1 MHz system clock.
The read and
write cycles referred to are, unless otherwise specified, 8502 type bus cycles. The
Z-80 Read Enable and Write Enable outputs are conditioned using logic to interface with an 8502
bus cycle, so no distinction is made as to the differences between cycles of the different processors.
As mentioned above,
the Z-80 is not in direct communication with the Processor Data Bus, due
to the necessity of adapting the Z-80 to 8502 bus protocol. Note, however, that every other device
and
the translated bus (except two that will be explained later) shares the Processor Data Bus as a
common data bus.
The Translated Address Bus
Another C 128 system bus is the Translated Address Bus, which is produced by the MMU during
AEC high. This bus consists
of only high order addressing lines, designated TAS - TA15. These lines
reflect the action of the MMU on the normal high order address lines, which mayor may not include
some sort
of translation. The MMU can translate the address of page zero or page one in normal opera-
tion, and it translates the Z-80 address from $0000 thru $OFFF in order to direct it to read the Z-80
BIOS. A more complete description of MMU translations can be found in the MMU section. Normally
the Translated Address Bus indirectly drives the DRAMs and the VIC chip by driving the Multiplexed
Address Buses. It directly drives System ROM 4 address line 12 to allow the Z-80 ROM relocation.
Finally,
this bus becomes address lines S thru 15 of the C64 compatible expansion port.
During a VIC cycle or a
DMA, the MMU pulls TA12 - TA15 high, while TAS - TA1l are tri-stated.
This allows the VIC chip to drive TAS - TA 11 as VIC addresses VAS - VA 11.
The Multiplexed Address Bus
This section actually describes
two related address buses, the Multiplexed Address Bus and the
VIC Multiplexed Address Bus, known respectively as MAO - MA 7 and VMAO - VMA 7. The VIC
Multiplexed Address Bus is created during AEC high by multiplexing the high order Translated Ad-
dress Bus (T AS -TA15) with the low order Processor Address Bus (AO -A7), controlled via the MUX
signal. This bus, driven though series resistors, is called the Multiplexed Address bus. The VIC Multi-
plexed Address Bus is used in addressing the VIC chip registers while the Multiplexed Address Bus
is the processor's DRAM address
for both 64K banks of DRAM.
4

BUS ARCHITECTURE (Continued)
During a VIC cycle, AEC low, the VIC chip address lines must be asserted. There is no completely
separate address bus for the VIC addresses, so it shares the VMAO - VMA 7 and TAS - TAll address
lines
that are otherwise tri-stated during AEC low. Most of the VIC addresses come out of the VIC
chip already multiplexed, but two of them, VA6 and VA7. They do not supply column information,
as the VIC chip supplies only fourteen bits of addressing. The higher order address bits VA 14 and
VA15 come from CIA 2, as in the C64. Thus, the VIC supplies complete VMAO - VMA7 for a VIC
DRAM access or DRAM refresh. The T A8 - TAll supplied by VIC are used in conjunction with another
addressing bus for non-multiplexed VIC cycle addresses, such as Character ROM and Color RAM
accesses.
The Shared Address Bus
The Shared Address Bus is a non-multiplexed address bus used by both the processor and the VIC
chip.
This is necessary to communicate with common resources, namely the Character ROM and
Color
RAM. During AEC high, the Shared Address Bus, designated SAO - SA7, is driven by AO - A7,
the lower order Processor Address bits. The higher order bits needed are supplied by the Translated
Address Bus, which is also a shared address bus. Thus, the processor is able to access both shared
items.
During AEC low, the VIC addresses VAO - VA7 (VMAO - VMA7) must come onto the Shared Ad-
dress Bus. Since VAO - VA6 are actually multiplexed, the row address only must be sent to the Shared
Address Bus. Thus, the Multiplexed VIC addresses are transparently gated when either RAS or MUX
are low, but latched when both are high, which would indicate that a column address is about to
be presented. The high order address bits, as well, are supplied by the shared Translated Address
Bus. Note that the Shared Address Bus provides the lower eight bits of the expansion port address,
allowing VIC access to cartridges and some additional drive capability by way of the TTL chips used
to drive the Shared Address Bus.
The Color Data Bus
The Color RAM is written to or read from by a nybble data bus called the Color Data Bus. During
AEC high, the Color Data Bus is connected to the lower half of the Processor Data Bus via an analog
switch, allowing the Processor full access to the Color RAM. During AEC low, that switch is opened,
effectively isolating the Color Data Bus from the Processor Data Bus. In this state, it is driven by the
VIC extended data bus DS -D11·
The Display Bus
The Display Bus is a bus local to the 8563 Video Controller VIC chip, consisting of the Display Ad-
dress, DAO - DA7, and the Bus Display Data Bus, DDO -DD7. This local bus supports the 8563 display
RAM, which is completely isolated from the rest of the C128 system. The Display Address Bus is
a mUltiplexed address bus providing addressing to the display DRAM. The Display Data Bus provides
communication between this DRAM and the 8563. The 8563 also provides row and column strobes
and dynamic refresh to this DRAM.
5

THE 8502 MICROPROCESSOR
FOLD OUT SCHEMATIC SHEET 2, PAGE 65, FOR EASY REFERENCE.
The 8502 is an HMOSII Technology microprocessor similar to the 6510/6502. It is the normal
operating processor and is used in
the C64 and the C128 modes. Fully software compatible with the
6510, hence the 6502, the 8502 also features a zero page port used in memory management and
cassette implementations. The
8502 is also specified for operation at 2 MHz. The 2 MHz operation
is made possible by removing
the VIC from the system. The VIC chip is never completely removed
from the C128 system, as it continues to function as clock generator and bus arbitrator. However,
the VIC is removed as a display chip and co-processor, thus the full clock cycle can be devoted to
processor functioning instead of sharing the cycle with the VIC. The task of video display processor
is
then taken over by the 8563, which can function without the need for bus sharing that the VIC
required. Since
the liD devices, SID, etc., are rated at 1 MHz only, stretching of the 2 MHz clock
is used to allow these parts to be directly accessed by the 2 MHz processor, and still keep throughput
to a maximum. The liD devices are not affected by the 2 MHz operation as they are still driven by
a 1 MHz source (and as such, all timer operations remain unchanged), and clock stretching is only
used to synchronize the 2 MHz machine cycle to the 1 MHz 1>0 high time. The clock sources and
clock stretching capabilities are generated by the VIC chip.
CLOCK STRETCHING
When running in 2 MHz mode, the processor clock sometimes must be stretched. This is handled
by
the VIC chip, the processor, and the PLA working together. When an liD operation is decoded
during a 2
MHz cycle, the phase relationship between the 2 MHz and the 1 MHz clocks must be con-
sidered.
If the 2 MHz access occurs during 1 MHz 1>1, the access to a clocked liD chip would be out
of synchronization with the 1 MHz clock that drives all 110 chips. Thus, during this phase relationship,
10ACC,
from the PLA, signals the VIC chip to extend the 2 MHz clock. Should the 2 MHz cycles take
place during the 1 MHz 1>2 cycle, no special attention is necessary.
Clock Stretching in 2 M Hz Mode
Please take note to consider the speed implications of this. In 2 MHz mode, half of the liD accesses
given
will occur at an effective speed of 1 MHz. For time critical operations, then, accesses to liD
chips are kept at a minimum.
6

THE 8502 MICROPROCESSOR (Continued)
e.l0
2 ROY
315020
8502 MICROPROCESSOR
3 IRQ
00 (IN) 1 40
RES
ROY 2 39 R/W
IRQ
3 38
00
NMI
4 37 01
AEC 5 36
02
VOO 6
35
03
AO
7
34
04
A1
8
33
05
4 NMI
A2 9
32
06
A3
10 8502
31 07
A4
11
jlPRO-
30
PO
A5
12 CESSOR
29
P1
A6 13 28
P2
A7
14 27
P3
A8
15
26 P4 5 AEC
A9 16
25
P5
A10 17
24 P6
A 11 18
23
A15
A12 19
22
A14
A13
20
21 VSS
6
VDD
7~20
AO~A 15
22,23
21 VSS
24~30 PO~P6
31~38 DO~D7
39 R/W
40 RES
Phase 0 clock input. This is the dual speed
system clock for the 128.
Ready. TTL level input, used to DMA the
8502. The processor operates normally while
ROY is high. When ROY makes a transition to
the low state, the processor will finish the
operation it is on, and any subsequent opera~
tion if it is a write cycle. On the next occur~
rence of read cycle the processor will halt,
making it possible to tri~state the processor
to gain complete access to the system bus.
The
Interrupt Request input is a request that
the processor initiate an interrupt sequence.
The processor will complete execution of the
current instruction before recognizing the re~
quest. At that time, the interrupt mask in the
Status Code Register will be examined. If the
interrupt mask is not set, the processor will
begin an interrupt sequence. The Program
Counter and the Processor status register will
be stored on the stack and the interrupt
disable flag is set so that no other interrupts
can occur. The processor will then load the
program counter from the memory location
$FFFE and $FFFF.
The Non~Maskable Interrupt Request is a
negative~edge sensitive request that the pro~
cessor initiate an interrupt sequence. The pro~
cessor will complete execution of the current
instruction before recognizing the request.
The
Program Counter and the processor
status register will be stored on the stack.
The processor will then load the program
counter from the memory locations $FFFA
and $FFFB.
The Address Enable Control. The Address
Bus is only valid when the AEC line is high.
When low, the address bus is in a high
impedance state. This allows DMA's for dual
processor systems.
5VDC input.
Address bus outputs. Unidirectional bus
used
to address memory and I/O devices. The
address
bus can be disabled by controlling
the AEC input.
DC ground.
Bidirectional 1/0 port used for transferring
data to and from the processor directly. The
Data Register is located at location $0001
and the Data Direction Register is located at
location $0000.
Bi~directional bus for transferring data to and
from the device and the peripherals.
The
readlwrite line is a TTL level output from
the processor to control the direction of data
transfer between the processor and memory,
peripherals, etc. This line is high for reading
memory and low for writing.
The Reset input is used to reset or start the
I,processor from a power down condition.
During the time that this line is held low,
writing to or from the "processor is inhibited.
When a positive edge is detected on the in~
put, the "processor will immediately begin
the reset sequence. After a system initializa~
tion time of 6 cycles, the mask interrupt flag
will be set and the processor will load the
program counter from the contents of the
memory locations $FFFC and $FFFD. This is
the start location for program control. After
VCC reaches 4.75 volts in a power up
routine, reset must be held low for at least 2
cycles. At this time the R/W line will become
valid.
7

THE Z-80 MICROPROCESSOR
FOLD OUT SCHEMATIC SHEET 2, PAGE 65, FOR EASY REFERENCE.
The 2-80 microprocessor is used as a secondary processor in the C128 to run CP/M based pro-
grams. The
2-80 is interfaced to the 8502 bus and can access all of the devices that the 8502 can
access.
Bus Interface
Since a 2-80 bus cycle is much different than a 65xx family bus cycle, a certain amount of interfac-
ing is required for a 2-80 to control a 65xx type bus. Since the 2-80 has built-in bus arbitration con-
trol lines, it is possible to isolate the 2-80 by tri-stating its address line. Thus, the 2-80 and 8502
both share common address lines.
The data lines do
not interface quite as easily. Due to the shared nature of the bus during 2-80
mode, it is necessary to isolate the 2-80 from the bus during AEC low. Thus, a tri-stable buffer must
drive the Processor bus during 2-80 data writes. The reverse problem occurs during a 2-80 read -
the 2-80 must not read things that are going on during AEC low. It must latch the data that was pre-
sent during AEC high. Thus, a transparent latch drives
the data input to the 2-80. It is gated by the
2-80 Read Enable output, and latched when the 1 MHz clock is low. It will be seen that the 2-80
actually runs during AEC low, but that the data bus interfaces with it only during AEC high.
Control Interface
The 2-80 control interfacing must provide useful clock pulses to the 2-80 and must tailor the 2-80
Read and Write Enable signals for the 8502 type bus protocol. The 2-80 clock is provided by the VIC
chip, and is basically a 4
MHz clock that only occurs during CPO low, as seen in the 2-80 bus timing
diagram. This insures that the 2-80 is only clocked when it is actively on the bus. One additional pro-
blem
that arises in clocking the 2-80 is that while all of the 8502 levels, and most of the 2-80 levels,
are TTL compatible,
the 2-80 clock input expects levels very close to five volts. For that reason, the
ouptut from the VIC chip is processed by a transistor switching circuit to give a full amplitude clock.
This
circuit uses the nine volt supply, thus, the nine volt circuit must be operational for the 2-80 to
function.
I:
l,'
.'\
Z-80 Bus Timing
8

THE Z-80 MICROPROCESSOR (Continued)
The Z-80 is designed to have explicit Read, Write and liD cycles, where an liD cycle is distinct
from a memory cycle. The 65xx family uses only memory mapped liD and thus, for a 65xx bus, all
liD devices appear as memory locations, and all non-write cycles appear as read cycles. The Z-80
communicates cycle information via two control lines, the Read Enable and Write Enable lines. The
C128 uses the Read Enable line of the Z-80 to gate the Processor Bus data to the Z-80 data bus.
The
Write Enable interfacing is somewhat more complicated.
The
Write Enable Circuitry consists of a rising-edge triggered 0- Type flip-flop and an SR flip-flop.
The O-flop is triggered by
the rising-edge of the 1 MHz clock. The positive output of the SR drives
the O-input, and
the Q output gated with AEC drives an open collector inverter, which in turn drives
the R/W line
of the 8502 bus. The S input is driven by the Z-80 WE, and the R input is driven by
the Q output of the O-flop. Normally the O-input is low, resulting in an 8502 read cycle. When the
Z-80 WE signal falls, it sets the SR flop, causing the O-input to rise. This line remains high, even if
the Z-80 wt. should rise again. When the 1 MHz clock rises, this high level is clocked, causing an
8502 write cycle that will last one complete 1 MHz cycle. When the Write signal is passed by the
O-flop, the Q output will reset the SR flop. If no more WE signals come, the O-flop will once again
set
8502 Read mode.
Processor Switching
It is important in normal operation for the Z-80 and 8502 to operate as co-processors, communicating
between each other. This is, however, only serial co-processing, not to be considered parallel co-
processing or mUltiprocessing. Only one processor
may have the bus at anyone time. This is impor-
tant in several ways. First, the C 128 system must power up with the Z-80 as the master processor.
This is because
the Z-80 will not power up cleanly, and may accidently access the bus when power-
ing up. Thus, it is made master on powerup and can do anything it likes to the bus. Also, the Z-80
can start up certain C64 applications that would cause the 8502 to crash, thus again it is the logical
choice
for startup processor. After some initializations, the Z-80 will start up the 8502 in either C128
or C64 mode, depending upon if a cartridge is present.
The second reason
for processor switching is to allow the Z-80 to access 8502 Kernal routines.
For standardized programs, or
for any I/O operation not supported in the Z-80 BIOS, the Z-80 can
pass on the
task of liD to the 8502. Since the Z-80 sees BIOS ROM where the 8502 sees its pages
o through F, the Z-80 can operate without fear of disrupting any 8502 pointers or the stack in RAM
Bank
O.
The Z-80 can receive a bus grant request from the MMU, via Z80EN, or from the VIC chip, via BA.
Since
the VIC control line is used for OMAs, that is not of immediate concern. The Z80EN action,
however, is, since it is the mechanism by which processors swap control. When the Z80EN line goes
high,
it triggers a Z-80 BUSRQ. The Z-80 will relinquish the bus by pulling BUSACK low. This action
drives
the 8502 AEC high and, providing VIC does not request a OMA, will also drive the 8502 ROY
line high, enabling the 8502. To switch back, a low on the Z-80 BUSRQ will result in Z-80 BUSACK
going high,
tri-stating and halting the 8502.
9

THE Z-80 MICROPROCESSOR (Continued)
906150
Z-80 MICROPROCESSOR
A 11
A12
A13
A14
A15
PHI
04
03
05
06
vee
02
07
00
01
INT
NMI
HALT
MEMREQ
lORQ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1-5, AO-A15
3040
6 PHI
7-10, DO-D7
12-15
11
VCC
16
INT
17 NMI
40
-A10
39
-A9
38
-A8
37 -A7
36
-A6
35
-A5
34
-A4
33
-A3
32
-A2
Z-80
31
-A1
p. Pro-
30
-AO
cessor
29 -VSS
28 -RFSH
27 -M1
26
-RESET
25 -BUSRQ
24
-WAiT
23 -BUSAK
22 -WR
21 -RO
16 Bit tri-stating Address Bus. Used for
16 bit memory address during memory
cycles, used for 8 bit 1/0 address dunng 110
cycles. This allows up to 256 input or 256
output ports. During refresh time, the lower 7
bits contain a valid refresh address.
Single phase
system clock.
Input/Output Data Bus, capable of tri-stating,
used for 8-bit data exchanges with memory
and I/O devices.
5VDC input.
Interrupt Request. Active low input, driven by
external devices. If the interrupt flag IFF is
enabled, and
the BUSRO line is not active,
the processor will honor the requested inter-
rupt at the end of the current instruction.
When the Z-80 acknowledges an interrupt, it
generates an Interrupt acknowledge signal
(IORO
during M 11 at the beginning of the
next instruction cycle. There are three
different modes of response to a given
mterrupt.
Non-Maskable Interrupt. Active low input.
This interrupt is edge triggered and cannot be
masked against. It IS always recognized at
the end of the current Instruction, forCing the
Z-80 to take a restart at location $0066. The
program counter IS automatically saved in the
stack to allow a return from the interrupted
program. Not~t continuous WAIT cycles
can delay an NMI by preventing the end of
the current cycle, and that BUSRO will over-
ride iiiMi.
18 HALT
Halt State. Active low output indicating that
the Z-80 has executed a HALT instruction
and is awaiting some kind of interrupt before
execution can continue. While in the HALT
state, the CPU continuously executes NOPs
to continue refresh activity.
19 MEMREO Memory Request. Active low, tri-state output
that indicates that the address bus holds a
valid address for a
memory read or write
operation.
20 10RO Input/Output~uest. Active low, tri-state
output. The 10RO signal indicates that the
lower half of the address bus holds a valid
~ss for an 1/0 read or write operat!£!!. An
10RO signal is also
generated with an M 1
signal
when an interrupt is being acknowl-
edged to indicate that an interrupt response
vector can be placed on the data bus. An
interrupt can be acknowledged du~ M1:
I/O operations never occur during M 1.
21
RD Memory Read. Active low, tri-state output.
RD indicates that the CPU wants to read data
from memory or from an I/O device. This
signal is generally used to gate read data
onto the data bus.
22
WR ~mory Write. Active low, tri-state output.
WR indicates that the data bus holds valid
data to be processed by memory or by an 1'0
device.
23
BUSAK Bus
Acknowledge. Active low output, used
to indicate to any device taking over the bus
that the Z-80 has gone into tri-state and the
bus has been granted. While in this mode it
cannot refresh dynamic memory.
24 WAIT
Wait. Active low input, used to drive the
Z-80 into wait states. As long as this signal
is
low, the Z-80 will execute wait states,
allowing this signal to be used to access
slow memor~ liO devices. While the
Z-80 is in a WAIT state, it cannot refresh
dynamic memory.
25
BUSRO Bus Request.
Active low input that is used to
request the CPU address, data, tn-statable
output control signals to all go tri-state for
bus sharing and DMAs. The lines go tri-state
upon terminatIon of the current machine
cycle.
26
RESET
Reset. Active low Input which forces the pro-
gram counter to zero and initializes the 2-80,
which will set interrupt mode 0, disable inter-
rupts, and set registers I and R to zero.
Dunng J!rrSEI. address and data buses tri-
state and all other signals go inactive.
27
M1
Machine Cycle One. Output, active low. This
signal indicates that the current machine
cycle is the OP code fetch of an Instruction
execution. During execution of a two byte
op-code,.M.L is generated as each byte IS
fetched. M 1 also occurs with iCi1iQ to in-
dicate an interrupt acknowledge cycle.
28
RFSH Refresh. Active low output used to indicate
that the address bus holds a refresh address
in Its lower seven bits. Thus, the current
MREO signal should be used to do a refresh
read
to all dynamiC memories not refreshed
from an alternate source. A7 IS set to zero
and the upper eight bits contain the I register
at thiS
time.
29
VSS Ground.
10

MEMORY ARCHITECTURE
FOLD OUT SCHEMATIC PAGES 64-67 FOR EASY REFERENCE.
$FCOO
$FOOO
$i:: 00
$0000
:5S GCJ __
c)< te""''-'c:
p ~,.j s
~======. , '=-~--:---~-----n-"-~
1
I
l
I
L~~gl--"~ge
o-d
~!- ~ ~i -
I " "RNRL I,
I -" ~
I' - 1 l.Je CO].. .. "'" Ed 1 tor i I - -
i! I i
f1
I'
[fC !'Ind CHRROM i:
'--- ____ --.lL
- ...::.-
iExtensionli
I Cd r d i!
i!
I,
C/
$ S80 _________________ _
[-12
M::J:) e
3R : C !' I
.f.Lc!:
__ - - - - - - - - __ - - - - - __ - - L _______ -'"-:
C128 ROM Memory Organization
"-'.ceol ~ ,
"":'101'121
I
b'.ceol_ /
_OROM)
C128 Memory Map
rlHt"1 ~,~'i~ 5
S~ K
RRM
C
I
I
...
) sp~c~
) SP;::C::
/
The memory map is an important consideration in maintaining C64 compatibility. The standard map
is shown for the C64 mode. The C128 basically becomes a C64 when in C64 mode.
11

MEMORY ARCHITECTURE (Continued)
C128 mode is achieved at system reset, and is controlled by a bit in the MMU configuration register
(See
MMU Circuit Theory, page 20). In C128 mode, the MMU asserts itself in the C128 memory map
at
$FFOO and in the I/O space starting at $0500. Use of MMU registers, located at $FFOO, allows
memory management without actually having the I/O block banked in at the time and with a minimum
loss of contiguous RAM. The MMU is removed from the memory map in C64 mode but is still used
by hardware to manage memory.
The ROMs in C64 mode, both internally and externally, look just like C64 ROMs. The internal BASIC
and KERNAL
provide the C64 mode with the normal C64 operating system in ROM. This ROM actual-
ly duplicates some of the ROM used in C 128 mode, but is necessary, as it is not accessible from
C128 mode. In C 128 mode, up to 48K of Operating System is present, with the exact amount being
set by software control. This allows quicker access to underlying RAM by turning off unneeded sec-
tions of the Operating System.
The External ROMs represented on the memory map are those used in the C64 mode, and obey
the
C64 rules for mapping, i.e., cartridges assert themselves in hardware via the EXROM and GAME
lines. External ROMs in C128 mode are mapped as banked ROMs, such that when the system is in-
itialized, all ROM
slots are polled for the existance of a ROM and the ROM's priority if one exists.
This
allows much more flexibility than the hardwire ROM substitution method, since the Kernal and
Basic ROMs can be
swapped out for an application program, swapped out for external program con-
trol,
or turned off all together. This banking manipulation is accomplished by writing to the Configura-
tion Register at location $0500 or $FFOO, in the MMU.
The hardware also features the ability to store preset values for the configuration and force a load
of the Configuration Register by writing to one of the LCR (Load Configuration Register) registers.
C128 RAM Memory Organization
Refer again to the C128 Memory Map. The RAM present in the system is actually composed of
two 64K by 8 bytes of contiguous DRAM. The RAM is accessed by selecting one of the two banks
of 64K according to the RAM banking rules set in the RAM Configuration Register of the MMU. The
area
shown as RAM is representative of what the ItProcessor would see if all ROM were disabled.
Bank
switching can be accomplished in one of two ways.
The bank in use is a function of the value stored in the Configuration Register. A store to this register
will always take effect immediately. An indirect store to this register, using preprogrammed bank con-
figuration values, can be accomplished by writing to one of the indirect load registers, known as LCRs
(Load
Configuration Register), located in the $FFOO region of memory. By writing to an LCR the con-
tents of its corresponding PCR (PreConfiguration Register) will be latched into the configuration register.
Refer
to the MMU section on page 20 and the Alternate Memory Configurations on the following page.
When dealing with 64K banks of memory at once, it may be desirable to bank in bank 1 but still
retain
the system RAM (Stack, Zeropage, Screen, etc.). The MMU has provisions for what is referred
to as common RAM. This is the RAM that does not bank, and is programmable in size and as to whether
it appears at the top, bottom, or both in the memory map. The size is set by bits 0 and 1 in the RAM
Configuration Register (RCR). If the value of the bits is zero, 1K will be common. Values of one, two,
and three produce common areas of 4K, 8K, and 16K respectively. If bit 2 of the RCR is set, bottom
memory is held common, if bit 3 is set, then top memory is common. In all cases, common RAM
is physically located in bank O.
12

MEMORY ARCHITECTURE (Continued)
-----~
~~ ___ .. _=;::;::I,A '"
i .... ;;:;'" ... =
2;, "\::-t:l\t=l_ ;:):~: :~~E 0:;
, • :: '(RC~ "
---~---~
r'_...: '" ~~:J . S _ - a
::e';~'J 1: ~e~,-::"~ y~c
f----- .... JP,:lo.! =
I H: O:l"" ;;
I "ir.. "'\;:" .... r::;L Q::;",: I '~~~E -"
, ~ Xq,::", = X
'6:::::C'J_ I ____ ~-:
.~. S "'~8 _ se:j 0:-::_
• : "'I::l _ '!".., ~ _ ~;"" s
,,'" ~'::''<I ; _
~'_'~:::L ~ ___ ~~
f,; _~' __ ~_" ____ --"
-------,:
fE-'~~ ---t.~
$::::,:; --- ---~-----'
4~. q;:;~ ':' :>::-:-q;' "
S:===--- ______ ...-/
!~GJl _-l ____ ~
:J,;' "IC~ ":;
.... cte r~: :~e
S8': 2"0 S9 t... ,e'"' J"es
:r,e ::;",~r"'lC: r r<u~.
, 7"r: S ""00 _'5'3': "":;-
~ .. :j~.~ ?.~q-l-s
::!'J -(; ~ - 8':::; _: r"
~-----------~
,
si3::~ ____ ~_~
C64 Alternate Memory Configurations
- - .~..::'~ =
3 v~:::
- ~. . ':' .. '; -
"-"!.
Zero page and page one can be located (or relocated) independently of the RCR. When the pro-
cessor accesses an address that falls within zeropage or page one, the MMU adds to the high order
Jl.Processor address,
the contents of the PO register pair or the P1 register pair, respectively, and puts
this new address on the bus, including the extended addressing bit A 16. RAM banking will occur as
appropriate
to access the new address. Writes to the PO and P1 registers will be stored in a prelatch,
until a
write to the respective PXL register occurs. This prevents a PXH register from affecting the
translated address until both high and low bytes have been written.
At the same time, the contents of the PO and P1 registers are applied to a digital comparator, and
a reverse substitution occurs if the address from the 8502 falls within the page pointed to by the
register. This results in not just relocating the zero or one page but swapping the zero or one page
with the memory that it replaced. Swapping only occurs if the swapped area is defined as RAM, i.e.,
System or Function ROM must always be at their assigned addresses and thus should not be back-
substituted. Note that upon system reset, the pointers are set to true zero and true one page.
For VIC
chip access, one bit in the MMU status register is substituted for extended address line
A 16, selecting the proper CAS enable to make it possible to steer the VIC to anywhere in the 128K
range. Note that AEC is the mechanism that the MMU uses to steer a VIC space address, i.e., when
AEC is Iowa VIC access is assumed. This results in the VIC bank being selected as well for an outside
DMA, since this too will pull the AEC line low.
13

MEMORY ARCHITECTURE (Continued)
MMU and 1/0 Memory Organization
The block of memory represented by the I/O Block is an expanded view of the memory block entitled
I/O + CHAROM,
as shown in the C128 memory map. When the I/O block exists, access to VIC, SID,
and I/O, as
well as the addition of the MMU can be accomplished. All I/O functions remain as they
were previously on the C64 with the exception that the MMU and the 80 Column chip have been
added.
With the exception of four registers that are asserted in the zero page in C128 mode, all new
MMU registers appear in an unused slot in the 110 Memory block, though they will only appear in
C128 mode. Detailed descriptions of the MMU registers can be found in the MMU section on page 20 .
$[J8CO
$0700
. ~~~~~----:
/ i
T •
I /
- .~- - !-----------'
I
- - - - i
1
I
I
____ f--
T " I, •
1 / 1,_1 +-
I T ,'-', -,
l~lH)::c:.
r T ,~
iJ1Ht:
=i RRM
/]
-----t
'"
~
i /1
;/
I
~ -- - - f----------!
C' .,.- II
J l_1
- ----c-I----
\/ :c
I/O Block
14

READ ONLY MEMORY
FOLD OUT SCHEMATIC SHEETS 3 AND 4, PAGES 66 AND 67, FOR EASY REFERENCE.
In C64 mode, the operating system resides in 16K of ROM, which includes approximately 8K for
Kernal and 8K for Basic. In C128 mode, the operating system resides in 48K of ROM and includes
advanced Kernal and Basic features. The Kernal,
by definition, is the general operating system of
the computer, with fixed entry points into usable subroutines. The entry table for the Kernal is located
in
memory at addresses $FF40 -$FFF9, exluding of course the MMU registers at $FFOO -$FF04.
There is also a CHARACTER ROM,
8K x 8, which resides on the Shared Bus, shared by the VIC chip
and the processor. The C64 OS ROM is wired so as to appear as two chunks of non-contiguous
ROM, copying the actual C64 ROM memory map. Provision is included to handle system ROM as
either
four 16K x 8 ROMs or as two 32K x 8 ROMs. All internal C 128 function ROMs will be the
32K x 8 variety.
Rom Banking
Refer to the MMU Register Map on page 20. Note that the Configuration Register (CR) controls
the type of ROM or RAM seen in a given address location. Dependent on the contents of the CR,
ROM may be enabled and disabled to attain the most useful configuration for the application at hand.
ROM is enabled in
three memory areas in C128 mode, each consisting of 16K of address space. The
lower ROM may be defined as RAM or System ROM, the upper two ROMs may be System ROM,
Function ROM, Cartridge ROM, or RAM.
In C64 mode the C64 memory mapping rules apply, which
are primitive compared to those used in C 128 mode. C64 ROM is banked as two 8K sections, BASIC
and KERNAL,
according to the page zero port and the cartridge in place at the time. No free banking
can
take place when a cartridge is in place.
In
the C 128, if an address falls into the range of an enabled ROM, the MMU will communicate the
status of ROM to the PLA decoder via the Memory Status lines. Essentially, the MMU looks up in
the Configuration Register which ROM or RAM is set. The various combinations possible are shown
on the C128 Memory Map found on page 11. The banking scheme, the way it is implemented, allows
up to 32K of internal, bankable ROM for use such as Function Key Applications programs, and will
support 32K of external bankable ROM. Various combinations of ROM are possible, and can be noted
by studying the configurations for the Configuration Register.
8K x 8
A7 1 24
Vee
1-8,
A6 2
23 A8
18,19, AO-A 12
Address Bus Inputs.
A5 3
22 A9
21-23
A4
4 21
A 12
12
vSS
Ground.
A3 5
20
CS1
9-11,
DO-D7
Data Outputs.
13-17
A2 6
2364
19 Al0
20
CSl
Chip Select.
Al 7 ROM
18
A 11
24
VCC
5VDC Input.
AO 8
17 07
DO 9
16 06
01 10
15 05
02
11
14
04
VSS
12
13 03
15

READ ONLY MEMORY (Continued)
Ne
A12
A7
A6
A5
A4
A3
A2
A1
A~
O~
01
02
GNO
Ne
A 12
A7
A6
A5
A4
A3
A2
A1
A~
O~
01
02
GNO
PIN
CONFIGURATION
1
28
2
27
3
26
4
25
5
24
6
23128
23
7 ROM
22
8
21
9
20
10
19
11
18
12 17
13 16
14 15
16K X 8 ROM
PIN
CONFIGURATION
1
28
2
27
3
26
4
25
5
24
6
23
7
23256
22
8
ROM
21
9
20
1~
19
11
18
vee
e5
3
A13
A8
A9
A
11
C5"CE
A1~
C5
2
07
06
05
04
03
vee
A14
A13
A8
A9
A
11
C5, ,CE
A1~
e5
2
07
06
12 17
-05
13
16 -04
14
15
03
32K X 8 ROM
1
NC
Not Connected.
2-10,
21,
AO-A 13 Address Bus Inputs.
23-26
11-13,
DO-D7 Data Outputs.
15-19
14 GND Ground.
20
CS2 Chip Select.
22
CS" CE
Output Enable.
27
CS3 Program Enable.
28
VCC 5VDC Input.
1
NC
Not Connected.
2-10,
21, AO-A14 Address
Bus Inputs.
23-27
11-13, DO-D7 Data Outputs.
15-19
14 GND Ground.
20
CS2
Chip Select.
22 CS"
CE
Output Enable.
28
VCC 5VDC Input.
16

RANDOM ACCESS MEMORY
FOLD OUT SCHEMATIC SHEETS 3 AND 4, PAGES 66 AND 67 FOR EASY REFERENCE.
The C128 System contains 128K of processor-addressable 4164 DRAMs in the 64K x 1 configura-
tion, organized into two individual 64K banks. Additionally, the system contains 16K of video display
4416 DRAMs (16K x 4) local to the 8563 CRT Controller, and 8K of STATIC RAM used as VIC
COLOR
RAM.
RAM banking, described in detail in the MMU section, is controlled by several MMU registers: the
Configuration Register, the RAM Configuration Register, and the Page Zero and Page One Pointers.
Simply put, the Configuration register controls which 64K bank of RAM is selected, the RAM Con-
figuration Register controls if and how much RAM is kept in common between banks, and the Pointer
registers redirect the zero and one pages to any page in memory, overriding the effect of the two
configuration registers. In the system, RAM bank select is achieved via gated CAS control.
2016
2K x 8 STATIC RAM
A7
A6
A5
A4
A3
A2
A1
AO
1/
00
1/
01
1/02
VSS
-
-
-
-
-
-
-
-
-
-
-
-
1
2
3
4
5
6
7
8
9
10
11
12
24
-VCC
23
-A8
22
-A9
21
-WE
20
-OE
19
-A10
18
-CS
17
-1/07
16
-1/06
15
-1/
05
14
-1/04
13
-1/03
1-8,
19, 22
AO-Al0
Address Bus Inputs.
23
9-11,
1/00-1 /07
Common Data Input/Output Lines.
13-17
12
VSS Ground.
18
CS
Chip Select Enable, Low Active.
20 OE
Output Enable, Low Active.
21
WE
Write (Input) Enable, Low Active.
24
VCC
5VDC Input.
0-----
- t-
~Vcc
~v ..
·
.
BUFFER
· ROW .
~EMORY MATRIX
·
DEC
. 128.1.
16.1. 8
0----
-
t-
-• I i
I CEa
r
·3
c:---
BUFFER 110 GA fE & COL DEC
6--
·0
t CEa
i . . I
i
0-----
CEa
BuFFER
BUFFER
--
0-----
tCEa
~
6
r-. ~~_~ 1/°0
EE~
Functional Diagram
17

RANDOM ACCESS MEMORY (Continued)
4164
64K x 1 DYNAMIC RAM
NC
DIN
WE
-
-
-
-
-
-
1
2
3
4
5
6
16
-VSS
15
-CAS
14 -DOUT
13
-A6
12 -A3
11
-A4
1
2
3
4
5-7,
9-13
8
14
NC
Unused.
DIN Data Input.
WE Write Enable. Low active control input.
RAS
Row Address Strobe Input. Low active.
AO-A7 Address Bus Inputs.
VCC 5VDC Input.
DOUT Data
Output.
RAS
A(J)
A2
A1
-7
10
-A5
15 CAS Column Address Strobe Input. Low active.
VCC
-8 9
-A7
16 VSS Ground.
WE
R/W CLOCK:~
0- GENERATOR
I R/W SWITCH I
t t
t i i t
RAS
RAS CLOCK
(J
'-+
DATA IN
0-
~ W
~
GENERATOR
MEMORY
0
MEMORY
BUFFER
DIN
ARRAY
...i
ARRAY
C
CAS
(J
ROW DEC.
~
:;c
F,;
ROW DEC.
V)
-
CAS CLOCK
V)
DATA OUT
0-
0.. --.- 0..
~
GENERATOR
~
:IE
(J
:IE
BUFFER
w
0(
0(
MEMORY
0
MEMORY
V)
CI)
ARRAY
X
li
X
ARRAY w
~
w
V)
V)
CI)
C
CI)
w
~
w
CI)
~
CI)
a:
A7o-
a:
;:)
~
;:)
"-
- - "-
CD
(J
CD
W
-4-----0
W W
a:
a:
c e
V) " A6o-
V)
MEMORY
-.. 0
MEMORY
w
--
a:
w
...i
ARRAY
V)
--1VBB GENERA
w
V) ARRAY
V)
w C Z
"- Z
V)
"- w
~
w
w
;:)
CI)
r;
~
V)
a:
CD
ROW DEC.
~
ROW DEC.
0
0
V)
U
0(
V)
w
w
MEMORY
C
MEMORY
X
a:
CI)
0
ARRAY
...i
ARRAY
DOUT
VCC
VSS
w 0 C
a:
0(
(J
"-
jJ
w
a:
A0o--
-. .
Functional Diagram
18