Crystal CDB5471 User manual

Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright  Cirrus Logic, Inc. 2001
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com
LK\ CDB5471
CDB5471 Evaluation Board and Software
FEB ‘01
DS480DB1
Features
lDirect Shunt Sensor and Current
Transformer Interface for 3-Phase
Power
lOn-Board Voltage Reference
lOn-board crystal for XIN
lDigital Interface to PC
lLab Windows/CVI Evaluation
Software
-“Real-Time” RMS calculation
-FFT Analysis
-Time Domain Analysis
-Noise Histogram Analysis
General Description
The CDB5471 is an inexpensive tool designed to evalu-
ate the functionality/performance of the CS5471 2-
channel A/D Converter. In addition to this data sheet, the
CS5471 Data Sheet is required in conjunction with the
CDB5471 Evaluation Board.
Two terminal-block connectors serve as inputs to the
CS5471’s two analog input pairs. The CDB5471 in-
cludes an optional voltage reference source for CS5471.
A 4.096MHz crystal is provided as a source for CS5471’s
XIN pin, or an external clock source can be supplied by
the user. Digital output data from the CS5471 is trans-
ferred to the user’s IBM-compatible PC via the included
25-pin parallel port cable.
The CDB5471 includes PC software, allowing the user to
perform data capture (includes option for time domain
analysis, histogram analysis, and frequency domain
analysis). The software also allows real-time RMS calcu-
lation/analysis to be performed simultaneously on the
instantaneous data from both channels.
ORDERING INFORMATION
CDB5471 Evaluation Board
VA-
VA+
GAIN
OWRS
SE
RESET
FSO
SDO
CLK
CPD
VREF
IN OUT
CS5451
VIN1+
VIN1-
IIN1+
IIN1-
VIN2+
VIN2-
IIN2+
IIN2-
VIN3+
VIN3-
IIN3+
IIN3-
Voltage
Reference
VREF
Charge
Pump
Circuitry
3 V
Regulator
Reset Circuit
Control Switches
Crystal
4.096 MHz
+5 VINVA+
VA- VD+GND
XIN
Serial-to-
Parallel
Interface
DB25
To PC
(Not Populated)
Header

CDB5471
2DS480DB1
TABLE OF CONTENTS
1. INTRODUCTION .......................................................................................................................4
1.1 CS5471 ..............................................................................................................................4
1.2 Data Flow on Evaluation Board .........................................................................................4
2. HARDWARE .............................................................................................................................5
2.1 Evaluation Board Description .............................................................................................5
2.2 Power Supply Connections ................................................................................................5
2.2.1 Analog Power Supply ............................................................................................5
2.2.2 Digital Power Supply .............................................................................................5
2.2.3 Charge Pump Options ...........................................................................................6
2.3 Eval Board Control - Headers/Switches .............................................................................6
2.3.1 Analog Inputs ........................................................................................................8
2.3.2 Voltage Reference Input .......................................................................................9
2.3.3 Clock Source for XIN .............................................................................................9
2.3.4 S1 DIP Switch .......................................................................................................9
2.3.5 Reset Circuit ..........................................................................................................9
2.3.6 External Signal In/Out Header ..............................................................................9
2.3.7 Serial-to-Parallel Interface .....................................................................................9
2.3.8 Connecting the Eval Board to PC .......................................................................10
3. SOFTWARE ............................................................................................................................14
3.1 Installing the Software ......................................................................................................14
3.2 Running the Software ......................................................................................................14
3.2.1 Getting Started ....................................................................................................14
3.2.2 The Start-Up Window ..........................................................................................15
3.2.3 The Conversion Window .....................................................................................15
3.2.4 Data Collection Window ......................................................................................17
3.2.5 Config Window ....................................................................................................18
3.2.6 Analyzing Data ....................................................................................................19
3.2.7 Time Domain Information ....................................................................................19
3.2.8 Frequency Domain Information ...........................................................................20
3.2.9 Histogram Information .........................................................................................21
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IBM, AT and PS/2 are trademarks of International Business Machines Corporation.
Windows is a trademark of Microsoft Corporation.
Lab Windows and CVI are trademarks of National Instruments.
SPI
TM
is a trademark of Motorola.
Microwire
TM
is a trademark of National Semiconductor.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
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marks and service marks can be found at http://www.cirrus.com.

CDB5471
DS480DB1 3
LIST OF FIGURES
Figure 1. Power Supply, CS5471, and Oscillator ..............................................11
Figure 2. Analog Inputs .....................................................................................12
Figure 3. Digital Circuitry ...................................................................................13
Figure 4. Start-Up Window................................................................................ 15
Figure 5. Conversion Window ...........................................................................16
Figure 6. Data Collection Window (Time Domain) ............................................17
Figure 7. Configuration Window........................................................................ 19
Figure 8. Data Collection Window (FFT)........................................................... 20
Figure 9. Data Collection Window (Histogram) .................................................21
Figure 10.Silkscreen ...........................................................................................22
Figure 11.Circuit Side .........................................................................................23
Figure 12.Solder Side......................................................................................... 24

CDB5471
4DS480DB1
1. INTRODUCTION
The CDB5471 Evaluation Board demonstrates the
performance of the CS5471 6-channel A/D con-
verter.
The CDB5471 evaluation board provides a quick
means of evaluating the CS5471. Analysis soft-
ware supplied with the CDB5471 allows the user to
observe the CS5471’s digital output data on the us-
er’s PC monitor. The PC software allows the user
to quantify the device’s performance in the time-
domain and frequency domain. The user can save
raw data from the CS5471 to a data file, which al-
lows to user to analyze performance with other
tools that may be preferable to the user.
1.1 CS5471
The CS5471 is a highly integrated Two-Channel
Delta-Sigma Analog-to-Digital Converter (ADC)
developed for power measurement/metering appli-
cations. However the CS5471 has other potential
uses in various data acquisition applications, par-
ticularly in motor/servo control applications which
require very high precision. The CS5471 combines
two delta-sigma modulators with decimation fil-
ters, along with a master-mode serial interface on a
single chip device. The CS5471 was designed for
the purpose of performing the A/D conversion op-
erations required at the front-end of a digital single-
phase metering system. The six ADC channels can
be thought of as a pair of voltage/current-channel
ADC’s in a digital single-phase power metering ap-
plication.
The CS5471 contains one programmable gain am-
plifier (PGA) for the current input. The PGA sets
the maximum input level of the current channel at
±800 mV DC (for gain = 1x) or ±40 mV DC (for
gain = 20x). The voltage channel has only the 1x
gain setting, and so the range of input levels on the
voltage channel is ±800 mV DC.
Additional features of CS5471 include a charge
pump driver, on-chip 1.2 V reference, and a digital
input that can select between two different output
word rates. (The two output word rates are equal to
XIN/2048 and XIN/1024.)
The CS5471 requires a 1.2 V reference input on
VREFIN. The ∆Σ modulators and high rate digital
filters allow the user to measure instantaneous volt-
age and current at an output word rate of 4 kHz (or
2000 kHz, depending on the state of the OWRS
pin) when a 4.096 MHz clock source is used.
1.2 Data Flow on Evaluation Board
The output serial bit-stream from the CS5471 is
shifted into an 8-bit latch circuit so that it can be
quickly ported to the DB25 connector. From this
connector, the data can be sent through the provid-
ed 25-pin printer cable to the parallel port of the us-
er’s IBM-compatible PC (the PC must run under
Windows ‘95/’98/2000 operating system).
Once the 8-bit segments of data are ported to the
user’s PC, the LabWindows software (included
with this kit) will re-segment the data into the ap-
propriate 16-bit word format for both of the
CS5471’s two data channels. The data is sent
quickly to the user’s PC, which allows the software
to perform various data processing and graphical il-
lustrations on the digital output data. This includes
real-time RMS, variance, and standard deviation
calculations for both channels. The output data
from each channel can be plotted on-screen in the
time domain or in the frequency domain. A histo-
gram function is also included to help the user to
evaluate the noise characteristics of each channel.
The software can also calculate the mean and stan-
dard deviation of the output codes both channels.
This feature allows the user to scrutinize the varia-
tion of the A/D converters if the user applies con-
stant DC voltage levels to the inputs. RMS
calculation is also provided to assist in the quick
analysis AC input signals.

CDB5471
DS480DB1 5
2. HARDWARE
2.1 Evaluation Board Description
The CDB5471 board contains circuitry that will:
• Accept appropriate DC voltage levels from the
user’s +3V and/or +5V power supplies, and
direct this power to the VA+, VD+, VA- and
DGND pins of the CS5471.
• Direct the six analog input signals to the six
input pairs of the CS5471.
• Supply necessary voltage reference input for the
CS5471’s VREFIN pin.
• Supply appropriate crystal/oscillator stimulus to
the CS5471’s XIN pin.
• Direct the output driver signal from the
CS5471’s charge-pump driver pin (CPD) which
is used produce the negative power supply
source for the CS5471’s VA- pin.
• Provide a reset switch that allows the user to set
the CS5471’s RESET pin from logic “1” to logic
“0”.
• Provide two DIP switches which allow the user
to set the logic levels on the CS5471’s GAIN and
OWRS input pins.
• Detect and receive the data frame signal and dig-
ital serial output data signals from the CS5471’s
FSO and SDO pins, and send this output data
through the included parallel cable, and up to
user’s PC.
Several areas of blank proto-board space are pro-
vided so that, if desired, the user can interface their
own electronic sensor equipment onto the board.
The output from these sensors can be wired to the
two nearby analog input terminal block connectors,
which is then fed to the two analog input channels
of the CS5471. Examples of such sensors would
include voltage and current transformers, shunt re-
sistors, and resistor divider networks.
The next section of this document describes the
various sections of the board. After this, operation
of the PC software is described in detail.
2.2 Power Supply Connections
The CDB5471 can be used in several different
power supply configurations. Table 1 shows the
various possible power connections with the re-
quired jumper settings. There are various +3 V and
+5 V options. The user must supplythe +3V, +5V,
GND, and sometimes -2V voltage levels needed to
power the evaluation board.
2.2.1 Analog Power Supply
Referring to Figure 1, the A+ post supplies power
to the positive analog power input pin (VA+) of the
CS5471. This post also supplies power to the
LT1004 voltage reference (D3) and the optional
+3V regulator (U5). If HDR9 is set to the “A-” set-
ting, the A- post can supply the required negative
voltage to the VA- pin of the CS5471.
Note that the evaluation board contains the foot-
prints and connectivity which allows the user to in-
stall a LM317 voltage regulator (U5), which can be
used to create +3 V from a +5 V supply. This op-
tion is useful if the user wants to interface the eval-
uation board to another board that can only operate
from a +5V supply. With HDR17 set to “+5V_IN”,
one single +5 V supply can be used to provide both
a +5V to various microcontrollers and/or other pe-
ripheral devices, as well as +3 V for the CS5471.
The included schematic diagram shows the circuit-
ry for the +5V regulator circuitry inside a box with
dashed lines. These components are not populated
when the board is shipped from the factory, but the
user can install these components if desired.
2.2.2 Digital Power Supply
The A+ post can be used to supply both the analog
power (to CS5471 VA+ pin) as well as the digital
power (to CS5471 VD+ pin). However if a sepa-
rate supply voltage is desired for the digital power

CDB5471
6DS480DB1
supply, the “VD+” banana connector post can be
used to independently supply a separate digital
power supply to the input of the CS5471 (VD+
pin), the 4.096 MHz oscillator (U1), and circuitry
for the parallel port interface. This is controlled by
the setting on HDR18.
The user should note that the CS5471 can operate
with a digital supply voltage of either +3V or +5V.
This voltage is defined as the voltage presented
across VD+ and DGND.
2.2.3 Charge Pump Options
The output from CS5471’s charge-pump driver pin
(CPD) can be used to generate a -2V supply when
the proper jumper settings are selected on HDR9.
This -2V supply can be used as the negative power
supply connection for the CS5471’s VA- pin. Re-
ferring to Figure 1, circuitry for a charge-pump cir-
cuit is included on-board. The charge pump circuit
consists of capacitors C11, C12, and C36, and di-
odes D1 and D2.
As an alternative to using the charge pump circuit,
the user can supply an off-board -2V DC power
source to the “A-” banana connector. This option
is controlled by the setting on HDR9.
2.3 Eval Board Control - Headers/Switches
Table 2 lists the various adjustable headers and
switches on the CDB5471 Evaluation Board, as
well as their default settings (as shipped from the
factory). The header settings can be adjusted by the
user to select various options on the evaluation
board. These options are described further in the
following paragraphs.
Power Supplies Power Post Connections
Analog Digital A+ A- GND D+ +5 V_IN HDR9 HDR17 HDR18
+3 +3 +3 -2 0 +3 NC
+3 +3 +3 -2 0 NC NC
+3 +3 +3 NC 0 +3 NC
+3 +3 +3 NC 0 NC NC
+3 +3 NC -2 0 NC +5
+3 +3 NC NC 0 NC +5
+3 +5 +3 -2 0 +5 NC
+3 +5 +3 NC 0 +5 NC
+3 +5 NC -2 0 +5 +5
+3 +5 NC NC 0 +5 +5
+5 +3 +5 0 +2 +5 NC
Table 1. Power Supply Connections
O O
O O
A-
CPD O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
O O
A-
CPD O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
A-
CPD O O O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
A-
CPD O O O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
O O
A-
CPD O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
A-
CPD O O O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
O O
A-
CPD O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
A-
CPD O O O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
O O
A-
CPD O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
A-
CPD O O O O
+5V_IN
A+ O O O O
O O
VD+
V+
O O
O O
A-
CPD O O+5V_IN
A+ O O O O
O O
VD+
V+

CDB5471
DS480DB1 7
Name Function Description Default Setting Default Jumpers
HDR1 Used to switch IIN3+ on the CS5471 between J2
and AGND. IIN3+ Set to BNC J2
HDR2 Used to switch VIN3- on the CS5471 between J3
and AGND. VIN3- Set to BNC J3
HDR3 Used to switch VIN3+ on the CS5471 between J1
and AGND. VIN3- Set to BNC J1
HDR4 Used to switch IIN3- on the CS5471 between J4
and AGND. IIN3- Set to BNC J4
HDR5 Used to switch VIN2- on the CS5471 between J6
and AGND. VIN2- Set to BNC J6
HDR6 Used to switch IIN2+ on the CS5471 between J7
and AGND. IIN2+ Set to BNC J7
HDR7 Used to switch IIN2- on the CS5471 between J5
and AGND. IIN2+ Set to BNC J5
HDR8 Used to switch VIN2+ on the CS5471 between J8
and AGND. VIN2+ Set to BNC J8
HDR9 Used to switch between external VA- and on-board
CS5471 charge-pump circuit, CPD CPD active
HDR10 Used to switch VIN1+ on the CS5471 between J9
and AGND. VIN1+ Set to BNC J9
HDR11 Used to switch IIN1- on the CS5471 between J12
and AGND. IIN1- Set to BNC J12
HDR12 Used to switch IIN1+ on the CS5471 between J10
and AGND. IIN1- Set to BNC J10
SW1 S1-1 sets logic level on CS5471 GAIN input pin
S1-2 sets logic level on CS5471 OWRS input pin SW1-2 Open (GAIN=x1)
SW1-1 Open (XIN/1024)
HDR13 Used to switch VIN1- on the CS5471 between J11
and AGND. VIN1- Set to BNC J11
HDR14
Used to switch the VREFIN from external VREF
post connector, to the on board LT1004 reference,
or to the on-chip reference VREFOUT. Refer to
Table 3.
VREFIN Set to on-
chip reference
VREFOUT
Table 2. Default Header Settings
O O IIN3+
O O AGND
O O VIN3-
O O AGND
O O VIN3+
O O AGND
O O IIN3-
O O AGND
O O VIN2-
O O AGND
O O IIN2+
O O AGND
O O IIN2-
O O AGND
O O VIN2+
O O AGND
O O
O O
A-
CPD
O O VIN1+
O O AGND
O O IIN1-
O O AGND
O O IIN1+
O O AGND
23
OPEN
O O VIN1-
O O AGND
O O LT1004
O O VREFOUT
O O EXT VREF

CDB5471
8DS480DB1
2.3.1 Analog Inputs
Refer to Figure 2. The settings on the 14 analog in-
put headers (2 headers per channel) which are des-
ignated as HDR10 through HDR13, determine
which of the input lines will carry a signal, and
which input lines may be grounded. They can be
configured to accept either a single-ended or differ-
ential signal. Using the voltage channel as an ex-
ample (see Figure 2), note that HDR10 sets the
input to the positive side of the first voltage channel
input (VIN1+ pin). HDR13 sets the input to the
negative side of the first voltage channel input
(VIN1- pin). In a single-ended input configuration,
HDR13 would be set to the “AGND” setting, and
HDR10 would be set to “VIN1+” and would con-
duct the single-ended signal. In a differential input
configuration, HDR13 would be set to “VIN1-”
and HDR10 would be set to “VIN1+” and this pair
of inputs would form the differential input pair into
the VIN1+ and VIN1- pins of the CS5471.
WARNING: DANGER! One of the possible ap-
plications for the CS5471 includes data acquisition
for a power metering system. However, the user
should not attempt to directly connect any leads
from a high-voltage power line to the evaluation
board inputs, even if the current/voltage levels are
gain reduced by resistive dividers and/or shunts.
Because the ground terminal of the parallel cable
(from the PC) is near or at earth ground potential,
the ground node on the evaluation board will also
be forced to earth ground potential. Serious dam-
age and even personal injury can occur if a “hot”
voltage main is connected to any point on the eval-
uation board, including the analog input connec-
tors. Such power line signals must be isolated by
current/voltage transformers and reduced in mag-
nitude before they can be safely applied to the eval-
uation board.
Several patch-circuit areas are provided near the
voltage/current input headers, in case the user
wants to connect special sensor circuitry to the an-
alog inputs (such as transformers, shunt resistors,
etc., for sensory the voltage/current on a single-
phase power line). For the input channel, a Shunt
Resistor or Current Transformer can be mounted in
these areas and connections can be made to current-
channel input pair. Likewise, the three channels, a
Voltage Divider or Voltage Transformer can be
connected to the CS5471’s voltage input pair. Note
from Figure 2 that a simple R-C network filters
each sensor’s output to reduce any interference
picked up by the input leads. The 3 dB corner of the
filter is approximately 50 kHz differential and
common mode.
Note that the CDB5471 Evaluation Board is also
used as the evaluation board for the CS5451 A/D
converter, which is a 6-channel version of the
CS5471. The user can use this board to the evalu-
HDR15 Controls the source for the CS5471 XIN clock input. Set to on-board 4.000
MHz crystal (U1).
HDR16 This header should always be shorted. Short this header
HDR17 Determines whether the main analog supply will be powered from the A- post, or from the regulated 3V
voltage (generated from the +5V_IN) post input. Set to A-
HDR18 Choose whether the digital circuitry will be powered by main analog supply, or powered by separate dig-
ital supply (through VD+ post).
Set to main analog
supply
Name Function Description Default Setting Default Jumpers
Table 2. Default Header Settings (Continued)
O O EXT XIN
O O DGND
O O 4.0096 MHz
OSC
O O
O O +5V_IN
O O A+
O O
O O
VD+
V+

CDB5471
DS480DB1 9
ate CS5451 by obtaining a CS5451 sample and
connect it in place of the CS5471 device. Then the
remaining four input channels serve as the inputs to
the CS5451’s four additional input pairs.
Other header options listed in Table 2 allow the
user to set the source of the input clock signal and
the source of the voltage reference (VREFIN) in-
put, etc. The voltage reference options and clock
input options are discussed next.
2.3.2 Voltage Reference Input
To supply theCS5471 with a suitable 1.2 V voltage
reference input at the VREFIN pin, the evaluation
board provides three voltage reference options: on-
chip, on-board, and external. See HDR14 as shown
in Figure 1. Table 3 illustrates the available voltage
reference settings for HDR14. With HDR14’s
jumpers in position “VREFOUT,” the CS5471’s
on-chip reference provides 1.2 volts. With HDR14
set to position “LT1004,” the LT1004 provides
1.23 volts (the LT1004 temperature drift is typical-
ly 50 ppm/°C). By setting HDR14’s jumpers to po-
sition “EXT VREF,” the user can supply an
external voltage reference to J16 connector post
(VREF) and AGND inputs.
2.3.3 Clock Source for XIN
A 4.000 MHz crystal is provided to drive the XIN
input of the CS5471. (See Figure 1.) However, the
user has the option to provide an external oscillator
signal for XIN, by switching the setting of HDR15.
2.3.4 S1 DIP Switch
Referring to Figure 3, the two single-pole single-
throw switches on SW1 DIP switch should be used
to control the logic settings on the CS5471’s
OWRS pin and GAIN pin. When these SW1
switches are set to “OPEN” the corresponding pin
on CS5471 is set to D+ potential, which creates a
logic-high state. When the user closes either of
these SW1 switches, the corresponding pin on
CS5471 is grounded, which creates a logic-low
state on the pin.
2.3.5 Reset Circuit
Circuitry has been provided which allows the user
to execute a hardware reset on the CS5471. (See
Figure 3). By pressing on the S1 switch, the RE-
SET pin on the CS5471 will be held low until the
switch is released.
2.3.6 External Signal In/Out Header
Note that HDR16 is included on the CDB5471
Evaluation Board as a header that is normally left
unconnected. This header provides a way for the
user to interface the CDB5471 Evaluation Board to
other prototype boards, calibrators, logic analyzers,
other peripherals, etc. in order to further evaluate
the CS5471 device and/or to use the evaluation
board as a platform for the prototype development
of a digital power metering solution. However,
note that the CDB5471 Evaluation Board is not in-
tended to be integrated directly into a commercial
digital power meter. The layout of the board is not
optimized for practical power metering situations.
2.3.7 Serial-to-Parallel Interface
Glue-logic on the evaluation board converts the
CS5471 serial data into 8-bit segments (bytes).
The bytes are sent to the DB25 connector (J17), and
then through the standard printer cable to the user’s
PC. This section briefly describes the operation of
the digital circuitry on the CDB5471 that provides
the 8-bit parallel data to the PC. Refer to Figure 3.
Reference Description HDR14
LT1004 Select on board
LT1004 Reference
(5 ppm/°C)
VREFOUT Select reference sup- plied from CS5471
VREFOUT pin
EXTVREF Select external
reference
Table 3. Reference Selection
O O LT1004
O O VREFOUT
O O EXT VREF
O O LT1004
O O VREFOUT
O O EXT VREF
O O LT1004
O O VREFOUT
O O EXT VREF

CDB5471
10 DS480DB1
The user should recall from CS5471 Data Sheet
that the serial interface on the CS5471 device is a
“master-mode” interface, which means that the de-
vice provides the clock. Once the CS5471 is pow-
ered on, the SCLK pin produces a clock signal, and
data is sent out on the SDO pin of the device. When
the evaluation software is instructed (by the user) to
acquire data through the parallel interface, a two-
step process is performed: First the software syn-
chronizes itself to the frame rate of the CS5471,
then the software acquires multiple frames of data
from the CS5471.
2.3.7.1. Synchronization
When the software is commanded to acquire data,
the software will first synchronize itself to the
frame rate of the CS5471 (see CS5471 Data Sheet).
This is done by measuring the amount of time be-
tween rising and falling edges of the “BUSY” sig-
nal. (BUSY will change state every time the
CS5471 issues eight SCLKs--See next section for a
more detailed description.) By measuring this time
period, the software can determine the idle period
of the frame, which allows it to be prepared to col-
lect a complete frame’s worth of data when the next
CS5471 frame is received. This acquisition se-
quence is described next.
2.3.7.2. Acquisition
Referring to Figure 3, the CS5471’s SCLK line is
used to clock the 8-bit serial-in/parallel-out shift-
register (U7) which accepts the serial data on SDO
and shifts it into the 8 output bits QA-QG. The
SCLK signal is also fed into the up/down counter
U6 and after every 8 SCLKs, the “QC” pin of U6
will latch the QA-QG output bits of U6 into the 8-
bit D-Flip-Flop (U3). While this is happening, the
software monitors the “BUSY” signal (from the
“QD” pin of U6). BUSY is the critical handshake
signal. A rising or falling transition on BUSY in-
dicates to the software that it is now time to collect
another byte of data from the latched output on U3.
After sixteen SCLKs, the PC software has acquired
two bytes (16 bits) which represents one data sam-
ple. The 4-bit up/down counter (U6) will roll over
after every 16 SCLKs. (Note that U6 is cleared by
the CS5471’s FSO signal at the beginning of each
frame, which insures that the counter begins the
frame in the correct state--cleared). This sequence,
which lasts for 16 SCLKs, is performed a total of
six times, although only the first two repetitions of
this sequence are relevant. In the first two sequenc-
es, the two 16-bit words from the CS5471 are ac-
quired by the PC. The data contained in the
remaining four sequence executions will be mean-
ingless, as the state of the CS5471’s SDO pin is be
undefined during the last 64 clocks of each data
frame.
After the sixth 16-bit word is acquired, the software
recognizes that the end of a data frame has been
reached, and it will continue to wait for the next
transition on the “BUSY” line. This will not occur
until the first 8 SCLKs of the next frame are sent
from the CS5471. Various other signals in Figure
3 (STRB, FEED, ACK, etc.) are not used during
data capture and are only used for testing (internal
use only).
2.3.8 Connecting the Eval Board to PC
The CDB5471 connects to the user’s IBM-compat-
ible PC with the included 25-pin parallel port cable.
The user should not connect this cable between
the CDB5471 and theparallel port on the PC until
all of the header options in Table 2 have been set
to appropriate settings and the user has applied
power to the CDB5471. The parallel cable at-
tached to the CDB5471 Evaluation Board at J17.
After connecting the parallel port cable between
the PC and CDB5471, the user should always actu-
ate (press down on) the “RESET” switch (S1) at
least one time before performing any other evalua-
tion activities.

CDB5471
DS480DB1 11
IN3-
IN3+
VIN3-
VIN3+
/GAIN
SE
FSO
SDO
SCLK
XIN
OWRS
VIN1+
VIN1-
IIN1+
IIN1-
VIN2+
VIN2-
IIN2+
IIN2-
/RESET
Do Not Populate
+3V
3.0V
+5V_IN
+5V
TP77
TP40
TANT
.33UF
C38
GND
140
R30 100
R31
22UF
C41
1K
R29
GND
C40
.1UF
CON_BANANA
J21
.1UF
C39
P6KE6V8P
Z4
10UF
C42
GND
OUT
ADJ
IN
2
1
3
LM317LZ
U5
TP78TP79
1.2V
TP76
TP40
A-
TP74 TP75
TP73
TANT
C37 4.7UF
IIN2-
IIN2+
VIN2-
VIN2+
IN3-
IN3+
VIN3-
VIN3+
J20
CON_BANANA
J18
CON_BANANA
TP62 TP63
TP60 TP61
TP58 TP59
TP56 TP57
TP54 TP55
TP52 TP53
TP50 TP51
TP48 TP49
TP46 TP47
TP44 TP45
TP42 TP43
TP40 TP41
TP38 TP39
TP37TP36
TP34TP35 TP32TP33 TP30TP31 TP28TP29 TP26TP27 TP24TP25 TP22TP23 TP20TP21 TP18TP19 TP16TP17
EXT VREF
J13
BNC_RA
SCLK
SDO
FSO
SE
/GAIN
AGND
VREFIN
VREFOUT
VA+
VA-
VIN3+
VIN3-
IN3+
IN3-
VD+
DGND
CPD
XIN
/RESET
OWRS
VIN1+
VIN1-
IIN1+
IIN1-
VIN2+
VIN2-
P6KE6V8P
Z1
TP1
TP40
2
3
LT1004
D3
4.99K
R3
10R2 FERRITE_BEAD
L1
Z2
P6KE6V8P
.039UF
C11
BAT85
D1
12
34
56
HDR15
HDR3X2
EXT_IN
XIN
J16
CON_BANANA
TP14 TP15
SCLK
SDO
FSO
SE
/GAIN
IN3+
IN3-
CON_BANANA
J15
.1UF
C14
.1UFC2
.1UF
C16
C19
.1UF
.1UF
C15
C18
.1UF
SCLK
SDO
FSO
SE
/GAIN
AGND
VREFIN
VREFOUT
VA+
VA-
VD+
DGND
CPD
XIN
/RESET
OWRS
VIN1+
VIN1-
IIN1+
IIN1-
VIN3-
VIN3+
XIN
/RESET
OWRS
VIN1+
IIN2-
IIN2+
VIN2-
VIN2+
IIN1-
IIN1+
VIN1-
IIN2+
IIN2-
J14
CON_BANANA
VD+
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
13
12
11
10
9
8
7
6
5
4
3
2
1
SSOP28_200_P65MM
U4
TANT
C36
4.7UF
43 21
HDR9
HDR2X2
V+
C23
47UF
47UF
C1
Z3
P6KE6V8P
C20
.1UF
47UF
C13
.1UF
C17
10UF
C21
.1UF
C22
A+
43
21
HDR2X2
HDR18
65
43
21
HDR14
HDR3X2
BAT85
D2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TANT
C12
2.2UF
10R32
D+
TP72
GND
21
HDR1X2
HDR16
D+ V+
GND
TP2
TP40
GND
VCC
8
14
7
4.0960MHZ
U1
43
21
HDR2X2
HDR17
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
13
12
11
10
9
8
7
6
5
4
3
2
1
SKT_SSOP28_ENP
U2
+3V
Figure 1. Power Supply, CS5471, and Oscillator

CDB5471
12 DS480DB1
GND
1 2 3 4
J27
4 3 2 1
J26
1 2 3 4
J25
IN3-
IN3+
VIN3-
VIN3+
VIN1+
VIN1-
IIN1+
IIN1-
VIN2+
VIN2-
IIN2+
IIN2-
TP68
TP69
TP70
TP71
TP64
TP65
TP66
TP67
BNC_RA
J9
R25 301
0.1%
12
34
HDR2X2
HDR10
BNC_RA
J10
J11
BNC_RA
BNC_RA
J12
0.1%
301R26
12
34
HDR11
HDR2X2
43
21
HDR12
HDR2X2
0.1%
301R27
43
21
HDR2X2
HDR13
R28 301
0.1%
R21 301
0.1%
12
34
HDR2X2
HDR5
0.1%
301R22
12
34
HDR6
HDR2X2
43
21
HDR7
HDR2X2
0.1%
301R23
BNC_RA
J5
J6
BNC_RA
BNC_RA
J7
43
21
HDR2X2
HDR8
R24 301
0.1%
0.1%
301R17
43
21
HDR1
HDR2X2
R18 301
0.1%
43
21
HDR2X2
HDR2
12
34
HDR2X2
HDR3
R19 301
0.1%
J1
BNC_RA
BNC_RA
J2
J3
BNC_RA
12
34
HDR4
HDR2X2
0.1%
301R20
J4
BNC_RA
J8
BNC_RA
TP4
TP5
TP6
TP3
4 3 2 1
J22
1 2 3 4
J23
1 2 3 4
J24
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C5
4700PF
.01UF
C33
C34
.01UF
C35
.01UF
4700PF
C6 .01UF
C32
C10
4700PF
.01UF
C29
C30
.01UF
C31
.01UF
.01UF
C28
4700PF
C9
C8
4700PF
C7
4700PF
C24
.01UF
.01UF
C25
C26
.01UF
C27
.01UF
GND
Figure 2. Analog Inputs

CDB5471
DS480DB1 13
SDO
SCLK
FSO
SE
/GAIN
/RESET
OWRS
GND
SW_B3W_1100
S1
R35 10K
R34 10K
D+
D+
470
R11
10KR5
4.7KR14
R8 470
GND
GND
.1UFC43
GND
1Y4
1Y3
1Y2
1Y1
1A4
1A3
1A2
1A1
VCC 1/G
20
18
16
14
12
10
8
6
4
2
1
SN74HC240N
U8
B
A
CLK
/CLR
GND
QG
QF
QE
QD
QC
QB
QA
VCC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SN74HC164N
U7
.1UF
C4
2Y4
2Y3
2Y2
2Y1
2A4
2A3
2A2
2A1
2/G
17
15
13
11 9
7
5
3
19
U8
SN74HC240N
D+
GND
COG
C45
220PF
QB
DATA B
QA
CD
CU
QC
QD
GND
VCC
DATA A
CLR
BORROW
CARRY
LOAD
DATA C
DATA D
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MM74HC193N
U6
GND
D+
FSO
4.7KR12
10KR4
GND
SE
4.7K
R15
470
R7
GND
GND
R9 470
SDO
470
R10
SCLK
D+
GND
8Q
7Q
8D
7D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q6D
5D
4D
3D
2D
1D
CLK
/OC
2
5
6
9
12
15
16
19
20
10
18
17
14
13
8
7
4
3
11
1
SN74HC374N
U3 4.7K
R13
10KR1
D+
D+
C44.1UF
2
1
OPEN
SW_DIP_2
SW1
R16 10K
GND
D+
10KR33
/GAIN
OWRS
.1UFC3
.1UFC46
20K
R36
GND
/RESET
D+
GND
1413 1211 109 87 65 43 21
HDR7X2
HDR19
49.9
R37
GND
D+
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DB25M_RA
J17
GND
ACK
SEL
BUSY
INIT
10KR6
STRB
FEED
Figure 3. Digital Circuitry

CDB5471
14 DS480DB1
3. SOFTWARE
The evaluation software was developed with Lab
Windows/CVI, a software development package
from National Instruments. The software is de-
signed to run under Windows 95or later, and re-
quires about 3 MB of hard drive space (2 MB for
the CVI Run-Time Engine, and 1 MB for the eval-
uation software). After installing the software, read
the readme.txt file for any last minute updates or
changes. More sophisticated analysis software can
be developed by purchasing the development pack-
age from National Instruments (512-794-0100).
3.1 Installing the Software
Installation Procedure:
1) Turn on the PC, running Windows 95or later.
2) Insert the Installation Diskette #1 into the PC.
3) Select the Run option from the Start menu.
4) At the prompt, type: A:\SETUP.EXE <enter>.
5) The program will begin installation.
6) If it has not already been installed on the PC,
the user will be prompted to enter the directory
in which to install the LabWindows CVI Run-
Time Engine. The Run-Time Enginemanag-
es executables created with Lab Win-
dows/CVI. If the default directory is
acceptable, select OK and the Run-Time En-
ginewill be installed there.
7) After the Run-Time Engineis installed, the
user is prompted to enter the directory in which
to install the CDB5471 software. Select OK to
accept the default directory.
8) Once the program is installed, it can be run by
double clicking on the EVAL5451 icon, or
through the Start menu.
Note: The software is written to run with 640 x 480
resolution; however, it will work with 1024 x 768
resolution.Iftheuserinterfaceseemstobealittle
small, the user might consider setting the
display settings to 640 x 480. (640x480 was
chosen to accommodate a variety of
computers).
3.2 Running the Software
3.2.1 Getting Started
The CDB5471 Evaluation software allows the user
to obtain, display, and save data that is acquired by
the CS5471 chip. Before running the software, the
first step is to make sure that all of the headers that
are listed in Table 2 are set to an appropriate set-
ting, the exact setting should be determined by the
user. Next, with the user’s DC power supplies still
turned off, the user should connect the necessary
power leads to the banana jack power connectors
on the evaluation board. Refer to Table 1 for vari-
ous acceptable power supply connection configura-
tions. Then at this time the user should turn on their
DC power supplies, which should apply power to
the CDB5471. Several test point locations are
available on the evaluation board. The user can
check these test points with a voltmeter, to make
sure that the voltages at these test points are at the
expected levels. When the user has verified that the
power supply levels are constant, the user should
connect the included 25-pin cable between J17 of
the evaluation board and the parallel port on the us-
er’s PC. The user should then press down on the S1
“RESET” switch, and make sure to hold it down for
at least ~0.5 seconds before releasing. Finally, the
user can start the PC software. To start the soft-
ware, double click on the EVAL5451 icon, or ini-
tiate through the Start menu.

CDB5471
DS480DB1 15
3.2.2 The Start-Up Window
When the software first executes, the user should
see the Start-Up Window appear on the user’s PC
monitor. This window is shown in Figure 4. From
this window, the user can navigate to three other
main windows: the Conversion Window, the Data
Collection Window, and CS5471 Pinout Diagram.
(The CS5451 Pinout Diagram is also included in a
fourth window.) To navigate to these windows, use
the mouse to click on the “Menu” item, which is lo-
cated towards the upper left corner of the Start-Up
Window. “Menu” is a pull-down menu which con-
tains four options. From this pull-down menu, the
user can select any of the three windows mentioned
above, and once this is done, the new window
should appear. A fourth option called “Exit”
should be selected when the user wants to terminate
execution of the evaluation board software pro-
gram.
If the user selects the “CS5471 Pinout Diagram”
option in the “Menu” pull-down, the software will
display a window which contains the pin diagram
of the CS5471. This pin diagram is included for the
user’s reference. Note that this window has no ac-
tual functionality.
The functionality of the Conversion Window and
the Data Collection Window is described next.
3.2.3 The Conversion Window
Refer to Figure 5. After the user presses on the
green-colored “START” button in this window, the
software will beginto collect data for both channels
of the CS5471. For each channel, a certain number
of instantaneous data samples from the CS5471 are
bundled together. The period over which each bun-
dle of samples is taken is called a “computation cy-
cle.” The user controls the number of
instantaneous data samples that will be taken (per
channel) during one computation cycle by adjust-
ing the number in the box labeled “Evaluation Soft-
ware Cycle Count:.” Note that the default value for
this is set to 4000. Thus during every computation
cycle, the PC software will acquire 4000 samples
Figure 4. Start-Up Window

CDB5471
16 DS480DB1
(from both channels) and it will update the on-
screen results of both channels after calculating the
results on each successive set of 4000 samples.
The results that are displayed on this screen are
therefore updated after each computation cycle.
Note that the results in the very first computation
cycle (after the “START” button has been activat-
ed) will not be valid. Accuracy of the Mean, Std.
Dev. and RMS results will increase as the “Sam-
ples to Average” value is increased.
The user should understand how to interpret the
values that are displayed in the array of number
boxes in the Conversion Window. For CDB5471,
only the results displayed inthe “Voltage 1” and
“Current 1” rows are valid. The result values
that are displayed in these numeric output boxes are
all expressed on a normalized scale. The highest
value (0.999...) represents the highest digital output
code that can be issued from the CS5471 (which is
+32767), while the lowest value -0.999... repre-
sents the most negative output code that can be is-
sued from the CS5471 (which is -32768). This is
because the CS5471 issues instantaneous output
codes as two’s complement 16-bit words. There-
fore, the range of values that can be returned from
the CS5471 are between -32768 and +32767. The
CS5471 issues instantaneous data, and every com-
putation cycle, the software computes/displays the
quantities which are described below:
Figure 5. Conversion Window

CDB5471
DS480DB1 17
3.2.3.1. Last Value
The first column is labelled as “Last Value.” The
value in this box represents the value of the very
last instantaneous sample that was taken (for both
channels) in the most recently-completed computa-
tion cycle. If the user’s analog input waveforms are
AC in nature, then this column of results will rarely
have any meaning. But if the user applies a con-
stant DC input signal to any of the analog input
channels, then the Last Value column for that chan-
nel should display an output code that is relatively
constant from one conversion cycle to the next.
3.2.3.2. Mean
The values in this column represent the simple average
of the sample values in the latest computation cycle.
3.2.3.3. Std Dev.
The values in this column represent the computed
standard deviation over the set of values in the most
recent computation cycle.
3.2.3.4. RMS
The values in this column represent the computed
RMS value over the most recently-completed com-
putation cycle.
3.2.4 Data Collection Window
The Data Collection Window (Figs 6, 8, and 9) al-
lows the user to collect samples sets of data from
CS5471 and analyze them using time domain, FFT,
and histogram plots. The Data Collection Window
is accessible through the Menu option, or by press-
ing F4.
3.2.4.1. Collect Button
This button will collect data from the CS5471, to be
analyzed in the plot area. See the section on Col-
lecting Data Sets for more information.
Figure 6. Data Collection Window (Time Domain)

CDB5471
18 DS480DB1
3.2.4.2. Time Domain / FFT / Histogram
Selector
This selector button is located just to the right of the
Collect Button. The label on this button will
change as the user selects which analysis is to be
performed (“Time Domain” or “FFT” or “Histo-
gram”). When the software is first started, the de-
fault mode on this selector button is Time Domain.
This user should click on this button to select which
type of data processing to perform on the collected
data and display in the plot area. Refer to the sec-
tion on Analyzing Data for more information.
3.2.4.3. “Crystal” Value Indicator Box
The value in this box reflects the frequency of the
CS5451’s clock input (at the XIN pin). Since the
XIN frequency affects the sampling rate (the output
word rate) of the CS5451, this information must be
specified to the software so that it can accurately
depict the frequency-content of the sampled data
(in Hz) when performing an FFT analysis. The
user can enter the crystal frequency that is used on
the CDB5451 board into this box. The default val-
ue of this box is set for the on-board 4.096MHz os-
cillator.
3.2.4.4. OWRS Pin Setting:
This switch should be adjusted whenever the user
toggles the S1-1 DIP switch (on the evaluation
board). The default setting of this switch is HI, cor-
responding to the default setting on S1-1 (default
setting is “OPEN”). S1-1 drives the CS5471’s
OWRS pin to logic “1”. A logic “1” on OWRS sets
the sampling frequency of both CS5471 input
channels to XIN/1024. To toggle the state of the
on-screen switch, simply click on the switch with
the mouse.
3.2.4.5. Config Button
This button will bring up the configuration window
(shown in Fig 7) in which the user can modify the
data collection specifications. See the discussion
of the Config Window in this document.
3.2.4.6. Save Button
The red-colored SAVE button will save the data in
the current plot to a file. The exact path and filena-
me can be specified by the user in the text window
located just to the left of the SAVE button. The
data collected for both channels will be saved to a
text file.
3.2.4.7. Load Button
The green colored LOAD button will load any data
file that was previously generated by clicking on
the red SAVE button. The exact path and filename
must be specified by the user in the text window lo-
cated just to the left of the LOAD button.
3.2.4.8. Channel Selector Buttons
Clicking on buttons labeled as “V1” and “I1” will
display a certain channel of data. “V1” refers to the
voltage data taken across the Vin1+/Vin1- pins of
the CS5471. In a similar manner, clicking on the
“I1” button will display the data representing the
voltage level across the current channel input pins
(Iin1+/Iin1-).
3.2.5 Config Window
See Figure 7. Clicking on the Config button will
bring up a small pop-up window called the Config
Window. The Config Window allows the user to
set up the data collection and analysis parameters,
which are described next.
3.2.5.1. Number of Samples
This box allows the user to select the number of
samples to collect. The user can choose any whole-
number power of 2 between 16 and 32768.
3.2.5.2. Average
When performing FFT processing, this box will de-
termine the number of FFTs to average. FFTs will
then be collected and averaged when the user clicks
on the Collect Button.

CDB5471
DS480DB1 19
3.2.5.3. FFT Window
This box allows the user to select the type of win-
dowing algorithm for FFT processing. Windowing
algorithms include the Blackman, Black-Harris,
Hanning, 5-term Hodie, and 7-term Hodie. The 5-
term Hodie and 7-term Hodie are windowing algo-
rithms developed at Cirrus Logic.
3.2.5.4. Histogram Bin Width
This box allows for a variable “bin width” when
plotting histograms of the collected data. Each ver-
tical bar in the histogram plot will contain the num-
ber of output codes contained in this box.
Increasing this number may allow the user to view
histograms with larger input ranges.
3.2.5.5. Samples to Discard
This number represents the number of CS5471
sample periods that will be ignored before the soft-
ware starts to collect samples (when the user press-
es on the Collect Button). After the software has
skipped over this many data samples, the software
will then begin to save samples from the device (for
all six channels). The number of samples that are
actually saved is equal to the number specified in
the Number of Samples box.
3.2.5.6. Ready Button
After the user has adjusted the parameters in the
Config Window to the desired settings, the user
must click on the READY button to close the Con-
fig Window and return to the Data Collection Win-
dow.
3.2.6 Analyzing Data
The evaluation software provides three types of
analysis tests - Time Domain, Frequency Domain,
and Histogram. The Time Domain analysis pro-
cesses acquired conversions to produce a plot of
Output Code versus Conversion Sample Number.
The Frequency Domain analysis processes ac-
quired conversions to produce a magnitude versus
frequency plot using the Fast-Fourier transform
(results up to Fs/2 are calculated and displayed).
The Histogram analysis test processes acquired
conversions to produce a histogram plot. Statistical
noise calculated are also calculated and displayed.
3.2.7 Time Domain Information
The following controls and indicators are associat-
ed with the Time Domain Analysis. Time domain
data can be plotted in the Data Collection Window
by setting the Time Domain / FFT / Histogram se-
lector to “Time Domain.”
3.2.7.1. Count
Displays current x-position of the cursor on the
time domain display.
3.2.7.2. Magnitude
Displays current y-value of the cursor on the time
domain display.
3.2.7.3. Maximum
Indicator for the maximum value of the collected
data set.
Figure 7. Configuration Window

CDB5471
20 DS480DB1
3.2.7.4. Minimum
Indicator for the minimum value of the collected
data set.
3.2.8 Frequency Domain Information
The following section describes the indicators as-
sociated with FFT (Fast-Fourier Transform) analy-
sis. Refer to Figure 8. FFT data can be plotted in
the Data Collection Window by setting the Time
Domain / FFT / Histogram selector button to
“FFT.”
3.2.8.1. Frequency
Displays the x-axis value of the cursor on the FFT
display.
3.2.8.2. Magnitude
Displays the y-axis value of the cursor on the FFT
display.
3.2.8.3. S/D
Indicator for the Signal-to-Distortion Ratio, 4 har-
monics are used in the calculations (decibels).
3.2.8.4. SINAD
Indicator for the Signal-to-Noise + Distortion Ratio
(decibels).
3.2.8.5. SNR
Indicator for the Signal-to-Noise Ratio, first 4 har-
monics are note included (decibels).
3.2.8.6. S/PN
Indicator for the Signal-to-Peak Noise Ratio (deci-
bels).
3.2.8.7. FS-PdB
Not using windowing, how far down from zero the
peak voltage input value is (decibels).
Figure 8. Data Collection Window (FFT)