Terasic de10-nano User manual

DE10-Nano
User Manual
1
www.terasic.com
May 31, 2017

DE10-Nano
User Manual
1
www.terasic.com
May 31, 2017
Chapter 1 DE10-Nano Development Kit 3
1.1 Package Contents 3
1.2 DE10-Nano System CD 4
1.3 Getting Help 4
Chapter 2 Introduction of the DE10-Nano Board 5
2.1 Layout and Components 5
2.2 Block Diagram of the DE10-Nano Board 8
Chapter 3 Using the DE10-Nano Board 11
3.1 Settings of FPGAConfiguration Mode 11
3.2 Configuration of Cyclone V SoC FPGAon DE10-Nano 13
3.3 Board Status Elements 20
3.4 Board Reset Elements 21
3.5 Clock Circuitry 22
3.6 Peripherals Connected to the FPGA 24
3.6.1 User Push-buttons, Switches and LEDs 24
3.6.2 2x20 GPIO Expansion Headers 27
3.6.3 Arduino Uno R3 Expansion Header 30
3.6.4 A/D Converter and Analog Input 32
3.6.5 HDMI TX Interface 34
3.7 Peripherals Connected to Hard Processor System (HPS) 36
3.7.1 User Push-buttons and LEDs 36
3.7.2 Gigabit Ethernet 36
3.7.3 UART 38
3.7.4 DDR3 Memory 39
3.7.5 Micro SD Card Socket 42
3.7.6 USB 2.0 OTG PHY 43
3.7.7 G-sensor 44
3.7.8 LTC Connector 45
Chapter 4 DE10-Nano System Builder 46
4.1 Introduction 46
4.2 Design Flow 47
4.3 Using DE10-Nano System Builder 48

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Chapter 5 Examples For FPGA 54
5.1 DE10-Nano Factory Configuration 54
5.2 ADC Reading 55
5.3 HDMI TX 58
5.4 DDR3_VIP 62
5.5 DDR3_RTL 68
5.6 Nios IIAccess HPS DDR3 73
Chapter 6 Examples for HPS SoC 79
6.1 Hello Program 79
6.2 Users LED and KEY 82
6.3 I2C Interfaced G-sensor 89
6.4 Setup USB Wi-Fi Dongle 92
6.5 Query Internet Time 95
Chapter 7 Examples for using both HPS SoC and FGPA 97
7.1 Required Background 97
7.2 System Requirements 98
7.3 AXI bridges in Intel SoC FPGA 98
7.4 GHRD Project 100
7.5 Compile and Programming 101
7.6 Develop the C Code 102
Chapter 8 Programming the EPCS Device 108
8.1 Before Programming Begins 108
8.2 Convert .SOF File to .JIC File 109
8.3 Write JIC File into the EPCS Device 114
8.4 Erase the EPCS Device 116
8.5 EPCS Programming via nios-2-flash-programmer 117
Chapter 9 Appendix A 118
9.1 Revision History 118

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Chapter 1
DE10-Nano
Development Kit
he DE10-Nano Development Kit presents a robust hardware design platform built
around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core
Cortex-A9 embedded cores with industry-leading programmable logic for ultimate
design flexibility. Users can now leverage the power of tremendous re-configurability paired
with a high-performance, low-power processor system. Intel’s SoC integrates an
ARM-based hard processor system (HPS) consisting of processor, peripherals and
memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth
interconnect backbone. The DE10-Nano development board is equipped with high-speed
DDR3 memory, analog to digital capabilities, Ethernet networking, and much more that
promise many exciting applications.
The DE10-Nano Development Kit contains all the tools needed to use the board in
conjunction with a computer that runs the Microsoft Windows XP or later.
1.1 P Pa ac ck ka ag ge e C Co on nt te en nt ts s
Figure 1-1 shows a photograph of the DE10-Nano package.
Figure 1-1 The DE10-Nano package contents
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The DE10-Nano package includes:
The DE10-Nano development board
DE10-Nano Quick Start Guide
USB cable Type A to Mini-B for FPGA programming or UART control
USB cable Type A to Micro-B for USB OTG connect to PC
5V DC power adapter
microSD Card (Installed)
Four Silicon Footstands
1.2 D DE E1 10 0- -N Na an no o S Sy ys st te em m C CD D
The DE10-Nano System CD contains all the documents and supporting materials
associated with DE10-Nano, including the user manual, system builder, reference designs,
and device datasheets. Users can download this system CD from the link:
http://de10-nano.terasic.com/cd.
1.3 G Ge et tt ti in ng g H He el lp p
Here are the addresses where you can get help if you encounter any problems:
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: [email protected]
Tel.: [phone]
Website: DE10-Nano.terasic.com

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Chapter 2
Introduction of the
DE10-Nano Board
his chapter provides an introduction to the features and design characteristics of the
board.
2.1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s
Figure 2-1 and Figure 2-2 shows a photograph of the board. It depicts the layout of the
board and indicates the location of the connectors and key components.
Figure 2-1 DE10-Nano development board (top view)
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Figure 2-2 DE10-Nano development board (bottom view)
The DE10-Nano board has many features that allow users to implement a wide range of
designed circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
FPGA
Cyclone® V SE 5CSEBA6U23I7 device
Serial configuration device –EPCS128
USB-Blaster II onboard for programming; JTAG Mode
2 push-buttons
4 slide switches
8 green user LEDs
Three 50MHz clock sources from the clock generator
Two 40-pin expansion header
One Arduino expansion header (Uno R3 compatibility), can connect with Arduino
shields.
One 10-pin Analog input expansion header. (shared with Arduino Analog input)
A/D converter, 4-wire SPI interface with FPGA
HDMI TX, compatible with DVI v1.0 and HDCP v1.4

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HPS (Hard Processor System)
800MHz Dual-core ARM Cortex-A9 processor
1GB DDR3 SDRAM (32-bit data bus)
1 Gigabit Ethernet PHY with RJ45 connector
port USB OTG, USB Micro-AB connector
Micro SD card socket
Accelerometer (I2C interface + interrupt)
UART to USB, USB Mini-B connector
Warm reset button and cold reset button
One user button and one user LED
LTC 2x7 expansion header

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2.2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e D DE E1 10 0- -N Na an no o B Bo oa ar rd d
Figure 2-3 is the block diagram of the board. All the connections are established through
the Cyclone V SoC FPGA device to provide maximum flexibility for users. Users can
configure the FPGA to implement any system design.
Detailed information about Figure 2-3 are listed below.
Figure 2-3 Block diagram of DE10-Nano

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F
FP PG GA A D De ev vi ic ce e
Cyclone V SoC 5CSEBA6U23I7 Device
Dual-core ARM Cortex-A9 (HPS)
110K programmable logic elements
5,570 Kbits embedded memory
6 fractional PLLs
C
Co on nf fi ig gu ur ra at ti io on n a an nd d D De eb bu ug g
Serial configuration device –EPCS128 on FPGA
Onboard USB-Blaster II (Mini-B USB connector)
M
Me em mo or ry y D De ev vi ic ce e
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD card socket on HPS
C
Co om mm mu un ni ic ca at ti io on n
One USB 2.0 OTG (ULPI interface with USB Micro-AB connector)
UART to USB (USB Mini-B connector)
10/100/1000 Ethernet
C
Co on nn ne ec ct to or rs s
Two 40-pin expansion headers
Arduino expansion header
One 10-pin ADC input header
One LTC connector (one Serial Peripheral Interface (SPI) Master ,one I2C and one
GPIO interface )
D
Di is sp pl la ay y
HDMI TX, compatible with DVI v1.0 and HDCP v1.4
A
AD DC C
12-Bit Resolution, 500Ksps Sampling Rate. SPI Interface.
8-Channel Analog Input. Input Range : 0V ~ 4.096V.

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S
Sw wi it tc ch he es s, , B Bu ut tt to on ns s, , a an nd d I In nd di ic ca at to or rs s
3 user Keys (FPGA x2, HPS x1)
4 user switches (FPGA x4)
9 user LEDs (FPGA x8, HPS x 1)
2 HPS reset buttons (HPS_RESET_n and HPS_WARM_RST_n)
S
Se en ns so or rs s
G-Sensor on HPS
P
Po ow we er r
5V DC input

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Chapter 3
Using the DE10-Nano
Board
his chapter provides an instruction to use the board and describes the peripherals.
3.1 S Se et tt ti in ng gs s o of f F FP PG GA A C Co on nf fi ig gu ur ra at ti io on n M Mo od de e
When the DE10-Nano board is powered on, the FPGA can be configured from EPCS or
HPS.
The MSEL[4:0] pins are used to select the configuration scheme. It is implemented as a
6-pin DIP switch SW10 on the DE10-Nano board, as shown in Figure 3-1.
Table 3-1 shows the relation between MSEL[4:0] and DIP switch (SW10).
Figure 3-1 DIPswitch (SW10) setting of FPPx32 mode.
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Table 3-1 FPGA Configuration Mode Switch (SW10)
Board Reference
Signal Name
Description
Default
SW10.1
MSEL0
Use these pins to set the FPGA
Configuration scheme
ON (“0”)
SW10.2
MSEL1
OFF (“1”)
SW10.3
MSEL2
ON (“0”)
SW10.4
MSEL3
OFF (“1”)
SW10.5
MSEL4
ON (“0”)
SW10.6
N/A
N/A
N/A
Table 3-2 shows MSEL[4:0] setting for FPGA configure, and default setting is FPPx32
Mode on DE10-Nano Board.
When the board is powered on and MSEL[4:0] set to “10010”, the FPGA is configured from
EPCS, which is pre-programmed with the default code. If developers using the "Linux
LXDE Desktop" SD Card image, the MSEL[4:0] needs to be set to “01010” before the board
is powered on.
Table 3-2 MSEL Pin Settings for FPGA Configure of DE10-Nano Board
Configuration
SW10.1
MSEL0
SW10.2
MSEL1
SW10.3
MSEL2
SW10.4
MSEL3
SW10.5
MSEL4
SW10.6
Description
AS
ON
OFF
ON
ON
OFF
N/A
FPGA configured
from EPCS
FPPx32(1) /
Compression
Enabled / Fast
POR
(Default)
ON
OFF
ON
OFF
ON
N/A
FPGA configured
from HPS software:
U-Boot, with image
stored on the SD
card, like LXDE
Desktop (default)
FPPx16 /
Compression
Disabled / Fast
POR
ON
ON
ON
ON
ON
N/A
FPGA configured
from HPS software:
U-Boot, with image
stored on the SD
card
(1): Please refer to the following link:
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclon
e-v/cv_5v4.pdf , See Table 4-1: Configuration Schemes for FPGA Configuration by the
HPS

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3.2 C Co on nf fi ig gu ur ra at ti io on n o of f C Cy yc cl lo on ne e V V S So oC C F FP PG GA A o on n D DE E1 10 0- -N Na an no o
There are two types of programming method supported by DE10-Nano:
1. JTAG programming: It is named after the IEEE standards Joint Test Action Group.
The configuration bit stream is downloaded directly into the Cyclone V SoC FPGA. The
FPGAwill retain its current status as long as the power keeps applying to the board; the
configuration information will be lost when the power is off.
2. AS programming: The other programming method is Active Serial configuration.
The configuration bit stream is downloaded into the serial configuration device
(EPCS128), which provides non-volatile storage for the bit stream. The information is
retained within EPCS128 even if the DE10-Nano board is turned off. When the board is
powered on, the configuration data in the EPCS128 device is automatically loaded into
the Cyclone V SoC FPGA.
JTAG Chain on DE10-Nano Board
The FPGA device can be configured through JTAG interface on DE10-Nano board, but the
JTAG chain must form a closed loop, which allows Quartus II programmer to the detect
FPGA device. Figure 3-2 illustrates the JTAG chain on DE10-Nano board.
In addition, the DE10-Nano has one external JTAG Header (J8) reserved for users to
connect to JTAG chain of the DE10-Nano via external blaster. The J8 header is not installed,
so users need to solder a 2.54mm 2x7 male pin header if it is necessary.
Figure 3-2 Path of the JTAG chain

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Configure the FPGA in JTAG Mode
There are two devices (FPGA and HPS) on the JTAG chain. The following shows how the
FPGA is programmed in JTAG mode step by step.
Open the Quartus II programmer, please Choose Tools > Programmer. The Programmer
window opens. Please click “Hardware Setup”, as circled in Figure 3-3.
Figure 3-3 Programmer Window

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If it is not already turned on, turn on the DE-SoC [USB-1] option under currently selected
hardware and click “Close” to close the window. See Figure 3-4.
Figure 3-4 Hardware Setting
Return to the Quartus II programmer and click “Auto Detect”, as circled in Figure 3-5
Figure 3-5 Detect FPGA device in JTAG mode

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If the device is detected, the window of the selection device is opened, Please select
detected device associated with the board and click “OK” to close the window, as circled in
Figure 3-6.
Figure 3-6 Select 5CSEBA6 device
Both FPGA and HPS are detected, as shown in Figure 3-7.
Figure 3-7 FPGAand HPS detected in Quartus programmer

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Right click on the FPGA device and open the .sof file to be programmed, as highlighted in
Figure 3-8.
Figure 3-8 Open the .sof file to be programmed into the FPGA device
Select the .sof file to be programmed, as shown in Figure 3-9.
Figure 3-9 Select the .sof file to be programmed into the FPGA device

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Click “Program/Configure” check box and then click “Start” button to download the .sof file
into the FPGA device, as shown in Figure 3-10.
Figure 3-10 Program.sof file into the FPGA device

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Configure the FPGA in AS Mode
The DE10-Nano board uses a serial configuration device (EPCS128) to store
configuration data for the Cyclone V SoC FPGA. This configuration data is
automatically loaded from the serial configuration device chip into the FPGA when the
board is powered up.
Users need to use Serial Flash Loader (SFL) to program the serial configuration device
via JTAG interface. The FPGA-based SFL is a soft intellectual property (IP) core within
the FPGA that bridge the JTAG and Flash interfaces. The SFL Megafunction is
available in Quartus II. Figure 3-11 shows the programming method when adopting
SFL solution.
Please refer to Chapter 8: Steps of Programming the Serial Configuration Device for
the basic programming instruction on the serial configuration device.
Figure 3-11 Programming a serial configuration device with SFL solution