Dallas Semiconductor DS2154 User manual

DS2154
Enhanced E1 Single Chip Transceiver
DS2154
071498 1/71
FEATURES
•CompleteE1(CEPT)PCM–30/ISDN–PRItransceiver
functionality
•Onboard long and short haul line interface for clock/
data recovery and waveshaping
•32–bit or 128–bit crystal–less jitter attenuator
•Generateslinebuildoutsforboth120Ωand75Ωlines
•Frames to FAS, CAS, and CRC4 formats
•Dualonboardtwo–frameelasticstore slipbuffersthat
can connect to asynchronous backplanes up to
8.192 MHz
•8–bit parallel control port that can be used directly on
either multiplexed or non–multiplexed buses
•Extracts and inserts CAS signaling
•Detects and generates Remote and AIS alarms
•Programmable output clocks for Fractional E1, H0,
and H12 applications
•Fully independent transmit and receive functionality
•Full access to both Si and Sa bits aligned with CRC
multiframe
•Four separate loopbacks for testing functions
•Largecounters forbipolar andcode violations, CRC4
codeword errors, FAS errors, and E bits
•Pin compatible with DS2152 T1 Enhanced Single–
Chip Transceiver
•5V supply; low power CMOS
•100–pin 14mm2body LQFP package
PACKAGE OUTLINE
100
1
ORDERING INFORMATION
DS2154L (0°C to 70°C)
DS2154LN (–40°C to +85°C)
DESCRIPTION
The DS2154 Enhanced Single–Chip Transceiver
(ESCT) contains all of the necessary functions for con-
nectiontoE1lines. Thedeviceisanupwardcompatible
version of the DS2153 Single–Chip Transceiver. The
onboard clock/data recovery circuitry coverts the AMI/
HDB3 E1 waveforms to a NRZ serial stream. The
DS2154 automatically adjusts to E1 22AWG (0.6 mm)
twisted–pair cables from 0 to over 2km in length. The
devicecangeneratethe necessaryG.703 waveshapes
forboth 75 ohm coax and120ohm twisted cables. The
onboard jitter attenuator (selectable to either 32 bits or
128 bits) can be placed in either the transmit or receive
data paths. The framer locates the frame and multi-
frame boundaries and monitors the data stream for
alarms. It is also used for extracting and inserting
signaling data, Si, and Sa bit information. The device
contains a set of internal registers which the user can
accesstocontroltheoperationoftheunit. Quickaccess
via the parallel control port allows a single controller to
handle many E1 lines. The device fully meets all of the
latest E1 specifications including ITU G.703, G.704,
G.706,G.823,G.932,andI.431aswellasETS300011,
300 233, 300 166, TBR 12 and TBR 13.

TABLE OF CONTENTS
DS2154
071498 2/71
I.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.0 PARALLEL PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.0 CONTROL, ID, AND TEST REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYNC/RESYNC Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Framers Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Alarm Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power–up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.0 STATUS AND INFORMATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC 4 SYNC Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alarm Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0 ERROR COUNT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BPV or Code Violation Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC4 Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–bit Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FAS Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.0 DSO MONITORING FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.0 SIGNALING OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Based Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Based Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.0 PER–CHANNEL CODE GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Side Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Side Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.0 CLOCK BLOCKING REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.0 ELASTIC STORES OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Register Scheme Based on Double–Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Register Scheme Based on CRC4 Multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS2154
071498 3/71
12.0 LINE INTERFACE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Waveshaping and Line Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.0 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Data Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.0 CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS2154
071498 4/71
1.0 INTRODUCTION
The DS2154 is a super–set version of the popular
DS2153 E1 Single–Chip Transceiver offering the new
features listed below. All of the original features of the
DS2153 have been retained and software created for
the original devices is transferrable into the DS2154.
NEW FEATURES SECTION
Option for non–multiplexed bus operation 1 and 2
Crystal–less jitter attenuation 12
Additional hardware signaling capability including:
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing
Interrupt generated on change of signaling data
7
Improved receive sensitivity: 0 dB to –43 dB 12
Per–channel code insertion in both transmit and receive paths 8
Expanded access to Sa and Si bits 11
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state 4
8.192 MHz clock synthesizer 1
Per–channel loopback 8
Addition of hardware pins to indicate carrier loss and signaling freeze 1
Line interface function can be completely decoupled from the framer/formatter to
allow:
Interface to optical, HDSL, and other NRZ interfaces
“tap” the transmit and receive bipolar data streams for monitoring purposes
Be able corrupt data and insert framing errors, CRC errors, etc.
1
Transmit and receive elastic stores now have independent backplane clocks 1
Ability to monitor one DS0 channel in both the transmit and receive paths 6
Access to the data streams in between the framer/formatter and the elastic stores 1
AIS generation in the line interface that is independent of loopbacks 1 and 3
Transmit current limiter to meet the 50 mA short circuit requirement 12
Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233 3
Automatic RAI generation to ETS 300 011 specifications 3

DS2154
071498 5/71
DS2154 ENHANCED E1 SINGLE–CHIP TRANSCEIVER Figure 1–1
8
VCO/ PLL
7
4 3
4
RCL RCLK RLOS 8MCLK RLINK RLCLK RCHBLK RCHCLK RSIGF RSIG RSER RSYSCLK RSYNC RMSYNC RFSYNC RDATA TSYNC TDATA TESO TSSYNC TSYSCLK TSER TSIG TCLK TCHBLK TCHCLK TLINK TLCLK
SIGNALING
BUFFER
8.192 MHz CLOCK
SYNTHESIZER
TIMING
CONTROL
Sa EXTRACTION
ELASTIC
STORE
SYNC CONTROL
HARDWARE
SIGNALING
INSERTION
ELASTIC
STORE
TIMING CONTROL
Sa INSERTION
LOTCMUX
SYNC
CLOCK DATA
SYNC
CLOCK DATA
RECEIVE SIDE
FRAMER
TRANSMIT
SIDE
FORMATTER
FRAMER LOOPBACK
REMOTE LOOPBACK
PER–CHANNEL CODE INSERT
FAS WORD INSERTION
SI BIT INSERTION
E–BIT INSERTION
SA INSERTION
PER–CHANNEL LOOPBACK
SIGNALING INSERTION
CRC4 GENERAITON
HDB3 ENCODE
AIS GENERAITON
PER–CHANNEL CODE INSERT
SAAND SI EXTRACTION
SIGNALING EXTRACTION
E–BIT COUNTER
FAS ERROR COUNTER
CRC ERROR COUNTER
ALARM DETECTION
SYNCHRONIZER
BPV COUNTER
HDB3 DECODER
LIUC
MUX
JITTER ATTENUATION
(CAN BE PLACED IN EITHER
TRANSMIT OR RECEIVE PATH)
16.384 MHz
LOCAL LOOPBACK
POWER
CONNECTIONS
CLOCK/DATA
RECOVERY
PEAK
EQUALIZER
DETECT
LIU AIS
GENERATION
WAVE–
SHAPING
LINE
DRIVERS
PARALLEL AND TEST CONTROL PORT
(ROUTED TO ALL BLOCKS) MUX
CLOCK/
CRYSTAL
INTERFACE
2.048
MHz
32.768 MHz
LIUC
TPOSO
TCLKO
TNEGO
TNEGI
TCLKI
TPOSI
MUX
D0 to D7/
AD0 to AD7
A0 to A6
ALE(AS)/A7
RD(DS)
WR(R/W)
BTS
CS
TEST
INT
RPOSI
RCLKI
RNEGI
RNEGO
RCLKO
RPOSO
8XCLK
XTALD
MCLK
RVDD
DVDD
TVDD
RVSS
DVSS
TVSS
RRING
RTIP
TRING
TTIP
LOTC

DS2154
071498 6/71
FUNCTIONAL DESCRIPTION
The analog AMI/HDB3 waveform off of the E1 line is
transformer coupled into the RRING and RTIP pins of
the DS2154. The device recovers clock and data from
theanalogsignal andpasses itthroughthe jitterattenu-
ation mux to the receive side framer where the digital
serial stream is analyzed to locate the framing/multi-
framepattern. TheDS2154containsanactivefilterthat
reconstructs the analog received signal for the non–lin-
earlosses thatoccur in transmission. Thedevice has a
usablereceivesensitivityof0dBto–43dBwhichallows
thedevicetooperateoncablesover2kminlength. The
receivesideframerlocatestheFASframeandCRCand
CASmultiframeboundariesaswellasdetectsincoming
alarms including, carrier loss, loss of synchronization,
AIS, and Remote Alarm. If needed, the receive side
elastic store can be enabled in order to absorb the
phase and frequency differences between the recov-
ered E1 data stream and an asynchronous backplane
clock which is provided at the RSYSCLK input. The
clock applied at the RSYSCLK input can be either a
2.048MHz clock or a1.544 MHz clock. The RSYSCLK
canalsobeaburstyclockwithspeedsupto8.192MHz.
The transmit side of the DS2154 is totally independent
fromthereceivesideinboththeclockrequirementsand
characteristics. Data off of a backplane can be passed
through a transmit side elastic store if necessary. The
transmitformatterwillprovidethenecessaryframe/mul-
tiframe data overhead for E1 transmission. Once the
data stream has been prepared for transmission, it is
sent via the jitter attenuation mux to the waveshaping
and line driver functions. The DS2154 will drive the E1
linefrom theTTIP and TRINGpins via acoupling trans-
former. The line driver can handle both 75Ωand
120Ωlines and it has options for high return loss
applications. The line driver contains a current limiter
that will restrict the maximum current into a 1Ωload to
less than 50 mA (rms).
READER’S NOTE
This data sheet assumes a particular nomenclature of
the E1 operating environment. There are 32 eight–bit
timeslots in an E1 systems which are number 0 to 31.
Timeslot 0 is transmitted first and received first. These
32timeslotsarealsoreferredtoaschannelswithanum-
beringschemeof1to32. Timeslot0isidenticaltochan-
nel 1, timeslot 1 is identical to Channel 2, and so on.
Eachtimeslot(orchannel)ismadeupofeightbitswhich
are numbered 1 to 8. Bit number 1 is the MSB and is
transmitted first. Bit number 8 is the LSB and is trans-
mitted last. Throughout this data sheet, the following
abbreviations will be used:
FAS Frame Alignment Sig-
nal CRC4 Cyclical Redundancy Check
CAS Channel Associated
Signaling CCS Common Channel Signaling
MF Multiframe Sa Additional bits
Si International bits E–bit CRC4 Error bits
PIN LIST Table 1–1
PIN SYMBOL TYPE DESCRIPTION
1 RCHBLK O Receive Channel Block.
2 NC – No Connect.
3 8MCLK O 8.192 MHz Clock.
4 NC – No Connect.
5 NC – No Connect.
6 RCL O Receive Carrier Loss.
7 NC – No Connect.
8 NC – No Connect.

DS2154
071498 7/71
PIN DESCRIPTIONTYPESYMBOL
9 NC – No Connect.
10 NC – No Connect.
11 BTS I Bus Type Select.
12 LIUC I Line Interface Connect.
13 8XCLK O Eight Times Clock.
14 TEST I Test.
15 NC – No Connect.
16 RTIP I Receive Analog Tip Input.
17 RRING I Receive Analog Ring Input.
18 RVDD – Receive Analog Positive Supply.
19 RVSS – Receive Analog Signal Ground.
20 RVSS – Receive Analog Signal Ground.
21 MCLK I Master Clock Input.
22 XTALD O Quartz Crystal Driver.
23 NC – No Connect.
24 RVSS – Receive Analog Signal Ground.
25 INT O Interrupt.
26 NC – No Connect.
27 NC – No Connect.
28 NC – No Connect.
29 TTIP O Transmit Analog Tip Output.
30 TVSS – Transmit Analog Signal Ground.
31 TVDD – Transmit Analog Positive Supply.
32 TRING O Transmit Analog Ring Output.
33 TCHBLK O Transmit Channel Block.
34 TLCLK O Transmit Link Clock.
35 TLINK I Transmit Link Data.
36 NC – No Connect.
37 TSYNC I/O Transmit Sync.
38 TPOSI I Transmit Positive Data Input.
39 TNEGI I Transmit Negative Data Input.
40 TCLKI I Transmit Clock Input.
41 TCLKO O Transmit Clock Output.
42 TNEGO O Transmit Negative Data Output.
43 TPOSO O Transmit Positive Data Output.

DS2154
071498 8/71
PIN DESCRIPTIONTYPESYMBOL
44 DVDD – Digital Positive Supply.
45 DVSS – Digital Signal Ground.
46 TCLK I Transmit Clock.
47 TSER I Transmit Serial Data.
48 TSIG I Transmit Signaling Input.
49 TESO O Transmit Elastic Store Output.
50 TDATA I Transmit Data.
51 TSYSCLK I Transmit System Clock.
52 TSSYNC I Transmit System Sync.
53 TCHCLK O Transmit Channel Clock.
54 NC – No Connect.
55 MUX I Bus Operation.
56 D0/AD0 I/O Data Bus Bit 0 / Address/Data Bus Bit 0.
57 D1/AD1 I/O Data Bus Bit 1 / Address/Data Bus Bit 1.
58 D2/AD2 I/O Data Bus Bit 2 / Address/Data Bus Bit 2.
59 D3/AD3 I/O Data Bus Bit 3 / Address/Data Bus Bit 3.
60 DVSS – Digital Signal Ground.
61 DVDD – Digital Positive Supply.
62 D4/AD4 I/O Data Bus Bit 4 / Address/Data Bus Bit 4.
63 D5/AD5 I/O Data Bus Bit 5 / Address/Data Bus Bit 5.
64 D6/AD6 I/O Data Bus Bit 6 / Address/Data Bus Bit 6.
65 D7/AD7 I/O Data Bus Bit 7 / Address/Data Bus Bit 7.
66 A0 I Address Bus Bit 0.
67 A1 I Address Bus Bit 1.
68 A2 I Address Bus Bit 2.
69 A3 I Address Bus Bit 3.
70 A4 I Address Bus Bit 4.
71 A5 I Address Bus Bit 5.
72 A6 I Address Bus Bit 6.
73 A7/ALE I Address Bus Bit 7 / Address Latch Enable.
74 RD (DS) I Read Input (Data Strobe).
75 CS I Chip Select.
76 NC – No Connect.
77 WR (R/W) I Write Input (Read/Write).
78 RLINK O Receive Link Data.

DS2154
071498 9/71
PIN DESCRIPTIONTYPESYMBOL
79 RLCLK O Receive Link Clock.
80 DVSS – Digital SIgnal Ground.
81 DVDD – Digital Positive Supply.
82 RCLK O Receive Clock.
83 DVDD – Digital Positive Supply.
84 DVSS – Digital Signal Ground.
85 RDATA O Receive Data.
86 RPOSI I Receive Positive Data Input.
87 RNEGI I Receive Negative Data Input.
88 RCLKI I Receive Clock Input.
89 RCLKO O Receive Clock Output.
90 RNEGO O Receive Negative Data Output.
91 RPOSO O Receive Positive Data Output.
92 RCHCLK O Receive Channel Clock.
93 RSIGF O Receive Signaling Freeze Output.
94 RSIG O Receive Signaling Output.
95 RSER O Receive Serial Data.
96 RMSYNC O Receive Multiframe Sync.
97 RFSYNC O Receive Frame Sync.
98 RSYNC I/O Receive Sync.
99 RLOS/LOTC O Receive Loss Of Sync / Loss Of Transmit Clock.
100 RSYSCLK I Receive System Clock.
NOTE:
Leave all no connect (NC) pins open circuited.
DS2154 PIN DESCRIPTION Table 1–2
TRANSMIT SIDE DIGITAL PINS
Transmit Clock [TCLK]. A 2.048 MHz primary clock.
Used to clock data through the transmit side formatter.
Must be present for the parallel control port to operate
properly. If not present, the Loss Of Transmit Clock
(LOTC) function can provide a clock.
Transmit Serial Data [TSER]. Transmit NRZ serial
data. Sampled on the falling edge of TCLK when the
transmit side elastic store is disabled. Sampled on the
fallingedge ofTSYSCLK when the transmitside elastic
store is enabled.
TransmitChannelClock[TCHCLK]. A256KHzclock
whichpulseshighduringtheLSBofeachchannel. Syn-
chronous with TCLK when the transmit side elastic
store is disabled. Synchronous with TSYSCLK when
thetransmitsideelasticstoreisenabled. Usefulforpar-
allel to serial conversion of channel data.
TransmitChannelBlock[TCHBLK]. Auser program-
mableoutputthatcanbeforcedhighorlowduringanyof
the 32 E1 channels. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous
with TSYSCLK when the transmit side elastic store is

DS2154
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enabled. Useful for blocking clocks to a serial UART or
LAPD controller in applications where not all E1 chan-
nels are used such as Fractional E1, 384 Kbps (H0),
768 Kbps, 1920 Kbps (H12) or ISDN–PRI. Also useful
for locating individual channels in drop–and–insert
applications,forexternalper–channelloopback,andfor
per–channel conditioning. See Section 9 for details.
Transmit System Clock [TSYSCLK]. 1.544 MHz or
2.048 MHz clock. Only used when the transmit side
elastic store function is enabled. Should be tied low in
applications that do not use the transmit side elastic
store. Can be burst at rates up to 8.192 MHz.
Transmit Link Clock [TLCLK]. 4 KHz to 20 KHz
demandclock(Sabits)fortheTLINKinput. SeeSection
11 for details.
TransmitLinkData[TLINK]. Ifenabled,thispinwillbe
sampled on the falling edge of TCLK for data insertion
into any combination of the Sa bit positions (Sa4 to
Sa8). See Section 11 for details.
Transmit Sync [TSYNC]. Apulseat this pinwill estab-
lisheitherframe or multiframe boundaries for the trans-
mit side. This pin can also be programmed to output
eitheraframeormultiframepulse. Alwayssynchronous
with TCLK.
TransmitFrameSync[TSSYNC]. Onlyusedwhenthe
transmitsideelasticstoreisenabled. Apulse atthispin
will establish either frame or multiframe boundaries for
thetransmitside. Shouldbetiedlowinapplicationsthat
do not use the transmit side elastic store. Always syn-
chronous with TSYSCLK.
Transmit Signaling Input [TSIG]. When enabled, this
input will be sample signaling bits for insertion into out-
going PCM E1 data stream. Sampled on the falling
edgeofTCLKwhenthetransmitsideelasticstoreisdis-
abled. Sampled on the falling edge of TSYSCLK when
the transmit side elastic store is enabled. See Section
13 for timing examples.
Transmit Elastic Store Data Output [TESO].
Updatedon therising edge ofTCLK with dataoutof the
the transmit side elastic store whether the elastic store
is enabled or not. This pin is normally tied to TDATA.
Transmit Data [TDATA]. Sampled on the falling edge
of TCLK with data to be clocked through the transmit
side formatter. This pin is normally tied to TESO.
TransmitPositiveDataOutput[TPOSO]. Updatedon
therisingedgeofTCLKOwiththebipolardataoutofthe
transmit side formatter. Can be programmed to source
NRZ data via the Output Data Format (TCR1.7) control
bit. This pin is normally tied to TPOSI.
Transmit Negative Data Output [TNEGO]. Updated
onthe risingedgeof TCLKO withthe bipolar dataout of
the transmit side formatter. This pin is normally tied to
TNEGI.
Transmit Clock Output [TCLKO]. Buffered clock that
isused toclockdata throughthetransmit sideformatter
(i.e.either TCLK orRCLKO if Loss OfTransmitClock is
enabled and in effect or RCLKI if remote loopback is
enabled). This pin is normally tied to TCLKI.
Transmit Positive Data Input [TPOSI]. Sampled on
the falling edge of TCLKI for data to be transmitted out
ontotheE1line. CanbeinternallyconnectedtoTPOSO
by tying the LIUC pin high.
Transmit Negative Data Input [TNEGI]. Sampled on
the falling edge of TCLKI for data to be transmitted out
ontotheE1line. CanbeinternallyconnectedtoTNEGO
by tying the LIUC pin high.
Transmit Clock Input [TCLKI]. Line interfacetransmit
clock. Can be internally connected to TCLKO by tying
the LIUC pin high.
RECEIVE SIDE DIGITAL PINS
Receive Link Data [RLINK]. Updated with the full
recovered E1 data stream on the rising edge of RCLK.
Receive Link Clock [RLCLK]. 4 KHz to 20 KHz clock
(Sa bits) for the RLINK output. See Section 11 for
details.
Receive Clock [RCLK]. 2.048 MHz clock that is used
to clock data through the receive side framer.