Dallas Semiconductor DS21354L User manual

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FEATURES
Complete E1 (CEPT) PCM-30/ISDN-PRI
transceiver functionality
Onboard long and short haul line interface
for clock/data recovery and waveshaping
32-bit or 128-bit crystal-less jitter attenuator
Frames to FAS, CAS, CCS, and CRC4
formats
Integral HDLC controller with 64-byte
buffers configurable for Sa Bits, DS0 or sub
DS0 operation
Dual two–frame elastic store slip buffers that
can connect to asynchronous backplanes up
to 8.192 MHz
Interleaving PCM Bus Operation
8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Extracts and inserts CAS signaling
Detects and generates remote and AIS alarms
Programmable output clocks for Fractional
E1, H0, and H12 applications
Fully independent transmit and receive
functionality
Full access to Si and Sa bits aligned with
CRC-4 multiframe
Four separate loopback functions for testing
functions
Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E bits
IEEE 1149.1 JTAG-Boundary Scan
Architecture
 Pin compatible with DS2154/52/352/552 SCTs
3.3V (DS21354) or 5V (DS21554) supply;
low power CMOS
100–pin LQFP package (14mm X 14mm)
ORDERING INFORMATION
DS21354L (00C to 700C)
DS21354LN (-400C to +850C)
DS21554L (00C to 700C)
DS21554LN (-400C to +850C)
DESCRIPTION
The DS21354/554 Single–Chip Transceiver (SCT) contains all of the necessary functions for connection to E1
lines. The device is an upward compatible version of the DS2153 and DS2154 SCTs. The onboard clock/data
recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21354/554
automatically adjusts to E1 22AWG (0.6 mm) twisted–pair cables from 0 to over 2km in length. The device can
generate the necessary G.703 waveshapes for both 75 ohm coax and 120 ohm twisted cables. The onboard jitter
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The
framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for
extracting and inserting signaling data, Si, and Sa bit information. The onboard HDLC controller can be used
for Sa bit links or DS0s. The device contains a set of internal registers which the user can access and control
the operation of the unit. Quick access via the parallel control port allows a single controller to handle many E1
lines. The device fully meets all of the latest E1 specifications including ITU-T G.703,G.704, G.706, G.823,
G.732, and I.431, ETS 300 011, 300 233, and 300 166, as well as CTR12 and CTR4.
DS21354 (3.3V) and DS21554 (5V)
E1 Single Chip Transceivers (SCT)
www.dalsemi.com
1
100

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TABLE OF CONTENTS
1 LIST OF FIGURES...................................................................................................................... 5
2 LIST OF TABLES........................................................................................................................ 6
3 INTRODUCTION......................................................................................................................... 7
3.1 Functional Description.............................................................................................................. 8
3.2 Document Revision History...................................................................................................... 9
4 PIN DESCRIPTION................................................................................................................... 11
4.1 Pin Function Description ........................................................................................................ 15
4.1.1 Transmit Side Pins.........................................................................................................15
4.1.2 Receive Side Pins ..........................................................................................................18
4.1.3 Parallel Control Port Pins.............................................................................................. 20
4.1.4 JTAG Test Access Port Pins.......................................................................................... 22
4.1.5 Interleave Bus Operation Pins....................................................................................... 23
4.1.6 Line Interface Pins......................................................................................................... 23
4.1.7 Supply Pins.................................................................................................................... 24
5 PARALLEL PORT..................................................................................................................... 24
5.1 Register Map........................................................................................................................... 25
6 CONTROL, ID, AND TEST REGISTERS.............................................................................. 29
6.1 Power-Up Sequence................................................................................................................ 30
6.1.1 Synchronizatrion and Re-synchronization .................................................................... 31
6.2 Framer Loopback.................................................................................................................... 34
6.3 Automatic Alarm Generation.................................................................................................. 35
6.4 Remote Loopback ................................................................................................................... 37
6.5 Local Loopback....................................................................................................................... 34
7 STATUS AND INFORMATION REGISTERS....................................................................... 39
7.1 CRC4 Sync Counter................................................................................................................ 41
8 ERROR COUNT REGISTERS................................................................................................. 44
8.1 BPV or Code Violation Counter............................................................................................. 44
8.2 CRC4 Error Counter ............................................................................................................... 45
8.3 E-Bit Counter.......................................................................................................................... 45
8.4 FAS Error Counter.................................................................................................................. 46
9 DS0 MONITORING FUNCTION............................................................................................. 46

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10 SIGNALING OPERATION....................................................................................................... 48
10.1 Processor Based Signaling............................................................................................................ 48
10.2 Hardware Based Signaling...................................................................................................... 51
10.2.1 Receive Side.................................................................................................................. 51
10.2.2 Transmit Side................................................................................................................. 51
11 PER-CHANNEL CODE GENERATION AND LOOPBACK............................................... 52
11.1 Transmit Side Code Generation.............................................................................................. 52
11.1.1 Simple Idle Code Insertion and Per-Channel Loopback............................................... 52
11.1.2 Per-Channel Code Insertion .......................................................................................... 53
11.2 Receive Side Code Generation ............................................................................................... 54
12 CLOCK BLOCKING REGISTERS......................................................................................... 54
13 ELASTIC STORES OPERATION........................................................................................... 56
13.1 Receive Side............................................................................................................................ 56
13.2 Transmit Side.......................................................................................................................... 56
14 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .............................. 56
14.1 Hardware Scheme ................................................................................................................... 57
14.2 Internal Register Scheme Based on Double-Frame................................................................ 57
14.3 Internal Register Scheme Based on CRC4 Multiframe .......................................................... 59
15 HDLC CONTROLLER FOR THE SA BITS OR DS0 ........................................................... 60
15.1 General Overview ................................................................................................................... 60
15.2 HDLC Status Registers........................................................................................................... 61
15.3 Basic Operation Details .......................................................................................................... 62
15.3.1 Receive a HDLC Message............................................................................................. 62
15.3.2 Transmit an HDLC Message......................................................................................... 62
15.4 HDLC Register Description.................................................................................................... 63
16 LINE INTERFACE FUNCTIONS............................................................................................ 68
16.1 Receive Clock and Data Recovery.......................................................................................... 69
16.2 Transmit Waveshaping and Line Driving............................................................................... 69
16.3 Jitter Attenuator....................................................................................................................... 71
16.4 Protected Interfaces................................................................................................................. 74
16.5 Receive Monitor Mode ........................................................................................................... 76
17 JTAG-VOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.................... 77
17.1 Description.............................................................................................................................. 77
17.2 TAP Controller State Machine................................................................................................78
17.3 Instruction Register................................................................................................................. 81
17.4 Test Registers.......................................................................................................................... 83

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18 INTERLEAVED PCM BUS OPERATION............................................................................. 86
18.1 Channel Interleave .................................................................................................................. 87
18.2 Frame Interleave...................................................................................................................... 87
19 FUNCTIONAL TIMING DIAGRAMS.................................................................................... 88
19.1 Receive.................................................................................................................................... 88
19.2 Transmit .................................................................................................................................. 94
20 OPERATING PARAMETERS ............................................................................................... 103
21 AC TIMING PARAMETERS AND DIAGRAMS ................................................................ 104
21.1 Multiplexed Bus AC Characteristics..................................................................................... 104
21.2 Non-Multiplexed Bus AC Characteristics ............................................................................ 107
21.3 Receive Side AC Characteristics .......................................................................................... 110
21.4 Transmit AC Characteristics................................................................................................. 114
22 MECHANICAL DESCRIPTION............................................................................................ 117

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1 LIST OF FIGURES
Figure 3-1 DS2135/554 BLOCK DIAGRAM................................................................................ 10
Figure 16-1 BASIC EXTERNAL ANALOG CONNECTIONS...................................................... 71
Figure 16-2 OPTIONAL CRYSTAL CONNECTION..................................................................... 72
Figure 16-3 JITTER TOLERANCE ................................................................................................. 72
Figure 16-4 JITTER ATTENUATION............................................................................................. 73
Figure 16-5 TRANSMIT WAVEFORM TEMPLATE .................................................................... 73
Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21554 ................................... 74
Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR THE DS21354 ................................... 75
Figure 16-8 TYPICAL MONITOR PORT APPLICATION............................................................ 76
Figure 17-1 JTAG FUNCTIONAL BLOCK DIAGRAM................................................................ 78
Figure 17-2 TAP CONTROLLER STATE DIAGRAM................................................................... 81
Figure 18-1 IBO BASIC CONFIGURATION USING 4 SCTS....................................................... 87
Figure 19-1 RECEIVE SIDE TIMING............................................................................................. 88
Figure 19-2 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled)........................ 89
Figure 19-3 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)...... 90
Figure 19-4 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)..... 91
Figure 19-5 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE......................... 92
Figure 19-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE ..................... 93
Figure 19-7 TRANSMIT SIDE TIMING ......................................................................................... 94
Figure 19-8 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled)..................... 95
Figure 19-9 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) ......... 96
Figure 19-10 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) ......... 97
Figure 19-11 TRANSMIT SIDE INTERLEAVE BUS OPERATIONS, BYTE MODE................... 98
Figure 19-12 TRANSMIT SIDE INTERLEAVE BUS OPERATIONS, FRAME MODE................ 99
Figure 19-13 G.802 TIMING............................................................................................................ 100
Figure 19-14 DS21354/554 FRAMER SYNCHRONIZATION FLOWCHART ............................ 101
Figure 19-15 DS21354/554 TRANSMIT DATA FLOW................................................................. 102
Figure 21-1 INTEL BUS READ AC TIMING (BTS=0 / MUX=1)............................................... 105
Figure 21-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1)................................................... 105
Figure 21-3 MOTOROLA BUS AC TIMING (BTS=1 / MUX=1)................................................ 106
Figure 21-4 INTEL BUS READ AC TIMING (BTS=0 / MUX=0)............................................... 108
Figure 21-5 INTEL BUS WRITE AC TIMING (BTS=0 / MUX=0)............................................. 108
Figure 21-6 MOTOROLA BUS READ AC TIMING (BTS=1 / MUX=0).................................... 109
Figure 21-7 MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0).................................. 109
Figure 21-8 RECEIVE SIDE AC TIMING .................................................................................... 111
Figure 21-9 RECEIVE SYSTEM SIDE AC TIMING.................................................................... 112
Figure 21-10 RECEIVE LINE INTERFACE AC TIMING............................................................. 113
Figure 21-11 TRANSMIT SIDE AC TIMING................................................................................. 115
Figure 21-12 TRANSMIT SYSTEM SIDE AC TIMING................................................................ 116
Figure 21-13 TRANSMIT LINE INTERFACE SIDE AC TIMING................................................ 116

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2 LIST OF TABLES
Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER..................................................... 11
Table 4-2 PIN DESCRIPTION BY SYMBOL ............................................................................. 13
Table 5-1 REGISTER MAP SORTED BY ADDRESS................................................................ 25
Table 6-1 DEVICE ID BIT MAP.................................................................................................. 29
Table 6-2 SYNC/RESYNC CRITERIA........................................................................................ 31
Table 7-1 ALARM CRITERIA..................................................................................................... 42
Table 15-1 HDLC CONTROLLER REGISTER LIST................................................................... 61
Table 16-1 LINE BUILD OUT SELECT IN LICR FOR THE DS21554....................................... 70
Table 16-2 LINE BUILD OUT SELECT IN LICR FOR THE DS21354....................................... 70
Table 16-3 TRANSFORMER SPECIFICATIONS......................................................................... 70
Table 16-4 RECEIVE MONITOR MODE GAIN........................................................................... 76
Table 17-1 INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE ................................ 81
Table 17-2 ID CODE STRUCTURE............................................................................................... 82
Table 17-3 DEVICE ID CODES..................................................................................................... 82
Table 17-4 BOUNDARY SCAN CONTROL BITS....................................................................... 83
Table 18-1 IBO MASTER DEVICE SELECT................................................................................ 86

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3 INTRODUCTION
The DS21354/554 is a superset version of the popular DS2153 and DS2154 SCTs offering the new
features listed below. All of the original features of the DS2153 and DS2154 have been retained and
software created for the original devices is transferable into the DS21354/554.
New Features in the DS21354 and DS21554
FEATURE SECTION
HDLC controller with 64-byte buffers for Sa bits or DS0s or sub DS0s 15
Interleaving PCM bus operation 18
IEEE 1149.1 JTAG-Boundary Scan Architecture 17
3.3V (DS21354 only) supply 2 and 3
Line Interface Support for the G.703 2.048 Synchronization Interface 16
Customer Disconnect Indication (...101010...) Generator 6
Open Drain Line Driver Option 16
New Features in the DS2154 (also in the DS21354 and DS21554)
FEATURE SECTION
Option for non–multiplexed bus operation 1 and 2
Crystal–less jitter attenuation 12
Additional hardware signaling capability including:
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing Interrupt generated on change of signaling data
7
Improved receive sensitivity: 0 dB to –43 dB 12
Per–channel code insertion in both transmit and receive paths 8
Expanded access to Sa and Si bits 11
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state 4
8.192 MHz clock synthesizer 1
Per–channel loopback 8
Addition of hardware pins to indicate carrier loss and signaling freeze 1
Line interface function can be completely decoupled from the framer/formatter to
allow:
Interface to optical, HDSL, and other NRZ interfaces
“tap” the transmit and receive bipolar data streams for monitoring purposes
Be able to corrupt data and insert framing errors, CRC errors, etc.
1
Transmit and receive elastic stores now have independent backplane clocks 1
Ability to monitor one DS0 channel in both the transmit and receive paths 6
Access to the data streams in between the framer/formatter and the elastic stores 1
AIS generation in the line interface that is independent of loopbacks 1 and 3
Transmit current limiter to meet the 50 mA short circuit requirement 12
Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233 3
Automatic RAI generation to ETS 300 011 specifications 3

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3.1 Functional Description
The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP
pins of the DS21354/554. The device recovers clock and data from the analog signal and passes it
through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to
locate the framing/multi-frame pattern. The DS21354/554 contains an active filter that reconstructs the
analog received signal for the nonlinear losses that occur in transmission. The device has a usable receive
sensitivity of 0 dB to –43 dB which allows the device to operate on cables over 2km in length. The
receive side framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects
incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If needed, the
receive side elastic store can be enabled in order to absorb the phase and frequency differences between
the recovered E1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK
input. The clock applied at the RSYSCLK input can be either a 2.048/4.096/8.192 MHz clock or a 1.544
MHz clock.
The transmit side framer is totally independent from the receive side in both the clock requirements and
characteristics. Data off of a backplane can be passed through a transmit side elastic store if necessary.
The transmit formatter will provide the necessary frame/multiframe data overhead for E1 transmission.
Reader’s Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In
each 125 us frame, there are 32 eight–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and
received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32.
Timeslot 0 is identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or
channel) is made up of eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted
first. Bit number 8 is the LSB and is transmitted last. The term “locked” is used to refer to two clock
signals that are phase or frequency locked or derived from a common clock (i.e., a 1.544MHz clock may
be locked to a 2.048MHz clock if they share the same 8KHz component). Throughout this data sheet, the
following abbreviations will be used:
FAS Frame Alignment Signal
CAS Channel Associated Signaling
MF Multiframe
Si International bits
CRC4 Cyclical Redundancy Check
CCS Common Channel Signaling
Sa Additional bits
E-bit CRC4 Error Bits

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3.2 DOCUMENT REVISION HISTORY
Date Notes
1-27-99 Initial release
1-28-99 Corrected TSYSCLK and RSYSCLK timing and added 4.096 MHz and 8.192 MHz
timing
2-3-99 Corrected definition and label of TUDR bit in the THIR register.
2-11-99 Correct address of IBO register in text.
4-1-99 Add Receive Monitor Mode section
4-15-99 Add section on Protected Interfaces
5-7-99 Correct pin # and description of FMS in JTAG section
7-29-99 Add list of tables and figures
9-14-99 Add 10uf cap to interface examples
9-23-99 Correct definition of DS* in pin description.

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DS21354/554 BLOCK DIAGRAM Figure 3-1
Receive Side
Framer
Transmit Side
Formatter
Elastic
Store
TSYNC
TCLK
TCHCLK
TSER
TCHBLK
RCHCLK
RCHBLK
RMSYNC
TSSYNC
TSYSCLK
RSER
RSYSCLK
RSYNC
RFSYNC
TLINK
TLCLK
Timing
Control
Elastic
Store
Sync Control
Timing Control
RLOS/LOTC
Signaling
Buffer
Hardware
Signaling
Insertion TSIG
RSIGF
RCL
Local Loopback
TRING
TTIP
Jitter Attenuator
Either transmit or receive path
Receive
Line I/F
Clock / Data
Recovery
RRING
RTIP
Remote Loopback
VCO / PLL
MCLK
8XCLK
8MCLK
8.192MHz Clock
Synthesizer
32.768MHz
16.384 MHz
XTALD
RCLK
RPOSO
RNEGO
RNEGI
RPOSI
TPOSI TNEGI
TNEGO TPOSO
TESO
TDATA
RCLKO
RCLKI
RDATA
TCLKI
TCLKO
LIUC
LIUC
Parallel & Test Control Port
(routed to all blocks)
D0 to D7 /
AD0 to AD7 BTS
INT* WR*(R/W*)
RD*(DS*)
CS*
TEST
ALE(AS) / A7 A0 to A6
MUX
8
7
Interleave
Bus
CI
RSYSCLK
Interleave
Bus
MUX
MUX
Transmit
LineI/F
DATA
CLOCK
SYNC
Framer Loopback
HDLC/BOC
Controller
Sa / DS0
LOTC
MUX
HDLC/BOC
Controller
Sa / DS0
SYNC
CLOCK
DATA
CO
JTAG PORT
JRST*
JTMS
JTCLK
JTDI
JTDO
RLINK
RLCLK
RSIG
Sa

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4 PIN DESCRIPTION
PIN DESCRIPTION SORTED BY PIN NUMBER Table 4-1
PIN SYMBOL TYPE DESCRIPTION
1 RCHBLK O Receive Channel Block
2 JTMS I IEEE 1149.1 Test Mode Select
3 8MCLK O 8.192 MHz Clock
4 JTCLK I IEEE 1149.1 Test Clock Signal
5 JTRST* I IEEE 1149.1 Test Reset
6 RCL O Receive Carrier Loss
7 JTDI I IEEE 1149.1 Test Data Input
8 NC – No Connect (do not connect any signal to this pin)
9 NC – No Connect (do not connect any signal to this pin)
10 JTDO O IEEE 1149.1 Test Data Output
11 BTS I Bus Type Select
12 LIUC I Line Interface Connect
13 8XCLK O Eight Times Clock
14 TEST I Test
15 NC – No Connect (do not connect any signal to this pin)
16 RTIP I Receive Analog Tip Input
17 RRING I Receive Analog Ring Input
18 RVDD – Receive Analog Positive Supply
19 RVSS – Receive Analog Signal Ground
20 RVSS – Receive Analog Signal Ground
21 MCLK I Master Clock Input
22 XTALD O Quartz Crystal Driver
23 NC – No Connect
24 RVSS – Receive Analog Signal Ground
25 INT* O Interrupt
26 NC – No Connect (do not connect any signal to this pin)
27 NC – No Connect (do not connect any signal to this pin)
28 NC – No Connect (do not connect any signal to this pin)
29 TTIP O Transmit Analog Tip Output
30 TVSS – Transmit Analog Signal Ground
31 TVDD – Transmit Analog Positive Supply
32 TRING O Transmit Analog Ring Output
33 TCHBLK O Transmit Channel Block
34 TLCLK O Transmit Link Clock
35 TLINK I Transmit Link Data
36 CI I Carry In
37 TSYNC I/O Transmit Sync
38 TPOSI I Transmit Positive Data Input
39 TNEGI I Transmit Negative Data Input
40 TCLKI I Transmit Clock Input
41 TCLKO O Transmit Clock Output
42 TNEGO O Transmit Negative Data Output
43 TPOSO O Transmit Positive Data Output

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PIN SYMBOL TYPE DESCRIPTION
44 DVDD – Digital Positive Supply
45 DVSS – Digital Signal Ground
46 TCLK I Transmit Clock
47 TSER I Transmit Serial Data
48 TSIG I Transmit Signaling Input
49 TESO O Transmit Elastic Store Output
50 TDATA I Transmit Data
51 TSYSCLK I Transmit System Clock
52 TSSYNC I Transmit System Sync
53 TCHCLK O Transmit Channel Clock
54 CO O Carry Out
55 MUX I Bus Operation
56 D0/AD0 I/O Data Bus Bit0/ Address/Data Bus Bit 0
57 D1/AD1 I/O Data Bus Bit1/ Address/Data Bus Bit 1
58 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus 2
59 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3
60 DVSS – Digital Signal Ground
61 DVDD – Digital Positive Supply
62 D4/AD4 I/O Data Bus Bit4/Address/Data Bus Bit 4
63 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5
64 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6
65 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7
66 A0 I Address Bus Bit 0
67 A1 I Address Bus Bit 1
68 A2 I Address Bus Bit 2
69 A3 I Address Bus Bit 3
70 A4 I Address Bus Bit 4
71 A5 I Address Bus Bit 5
72 A6 I Address Bus Bit 6
73 ALE(AS)/A7 I Address Latch Enable /Address Bus Bit 7
74 RD*(DS*) I Read Input(Data Strobe)
75 CS* I Chip Select
76 FMS I Framer Mode Select
77 WR*(R/W*) I Write Input(Read/Write)
78 RLINK O Receive Link Data
79 RLCLK O Receive Link Clock
80 DVSS – Digital Signal Ground
81 DVDD – Digital Positive Supply
82 RCLK O Receive Clock
83 DVDD – Digital Positive Supply
84 DVSS – Digital Signal Ground
85 RDATA O Receive Data
86 RPOSI I Receive Positive Data Input
87 RNEGI I Receive Negative Data Input
88 RCLKI I Receive Clock Input
89 RCLKO O Receive Clock Output

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PIN SYMBOL TYPE DESCRIPTION
90 RNEGO O Receive Negative Data Output
91 RPOSO O Receive Positive Data Output
92 RCHCLK O Receive Channel Clock
93 RSIGF O Receive Signaling Freeze Output
94 RSIG O Receive Signaling Output
95 RSER O Receive Serial Data
96 RMSYNC O Receive Multiframe Sync
97 RFSYNC O Receive Frame Sync
98 RSYNC I/O Receive Sync
99 RLOS/LOTC O Receive Loss Of Sync/ Loss Of Transmit Clock
100 RSYSCLK I Receive System Clock
PIN DESCRIPTION BY SYMBOL Table 4-2
PIN SYMBOL TYPE DESCRIPTION
3 8MCLK O 8.192 MHz Clock
13 8XCLK O Eight Times Clock
66 A0 I Address Bus Bit 0
67 A1 I Address Bus Bit 1
68 A2 I Address Bus Bit 2
69 A3 I Address Bus Bit 3
70 A4 I Address Bus Bit 4
71 A5 I Address Bus Bit 5
72 A6 I Address Bus Bit 6
73 ALE(AS)/A7 I Address Latch Enable/ Address Bus Bit 7
11 BTS I Bus Type Select
36 CI I Carry In
54 CO O Carry Out
75 CS* I Chip Select
56 D0/AD0 I/O Data Bus Bit0/ Address/Data Bus Bit 0
57 D1/AD1 I/O Data Bus Bit1/ Address/Data Bus Bit 1
58 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus 2
59 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3
62 D4/AD4 I/O Data Bus Bit4/Address/Data Bus Bit 4
63 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5
64 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6
65 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7
44 DVDD – Digital Positive Supply
81 DVDD – Digital Positive Supply
61 DVDD – Digital Positive Supply
83 DVDD – Digital Positive Supply
45 DVSS – Digital Signal Ground
60 DVSS – Digital Signal Ground
80 DVSS – Digital Signal Ground
84 DVSS – Digital Signal Ground
76 FMS I Framer Mode Select
25 INT* O Interrupt

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PIN SYMBOL TYPE DESCRIPTION
4 JTCLK I IEEE 1149.1 Test Clock Signal
7 JTDI I IEEE 1149.1 Test Data Input
10 JTDO O IEEE 1149.1 Test Data Output
2 JTMS I IEEE 1149.1 Test Mode Select
5 JTRST* I IEEE 1149.1 Test Reset
12 LIUC I Line Interface Connect
21 MCLK I Master Clock Input
55 MUX I Bus Operation
8 NC – No Connect (do not connect any signal to this pin)
9 NC – No Connect (do not connect any signal to this pin)
15 NC – No Connect (do not connect any signal to this pin)
23 NC – No Connect (do not connect any signal to this pin)
26 NC – No Connect (do not connect any signal to this pin)
27 NC – No Connect (do not connect any signal to this pin)
28 NC – No Connect (do not connect any signal to this pin)
1 RCHBLK O Receive Channel Block
92 RCHCLK O Receive Channel Clock
6 RCL O Receive Carrier Loss
82 RCLK O Receive Clock
88 RCLKI I Receive Clock Input
89 RCLKO O Receive Clock Output
74 RD*(DS*) I Read Input(Data Strobe)
85 RDATA O Receive Data
97 RFSYNC O Receive Frame Sync
79 RLCLK O Receive Link Clock
78 RLINK O Receive Link Data
99 RLOS/LOTC O Receive Loss Of Sync/ Loss Of Transmit Clock
96 RMSYNC O Receive Multiframe Sync
87 RNEGI I Receive Negative Data Input
90 RNEGO O Receive Negative Data Output
86 RPOSI I Receive Positive Data Input
91 RPOSO O Receive Positive Data Output
17 RRING I Receive Analog Ring Input
95 RSER O Receive Serial Data
94 RSIG O Receive Signaling Output
93 RSIGF O Receive Signaling Freeze Output
98 RSYNC I/O Receive Sync
100 RSYSCLK I Receive System Clock
16 RTIP I Receive Analog Tip Input
18 RVDD – Receive Analog Positive Supply
19 RVSS – Receive Analog Signal Ground
20 RVSS – Receive Analog Signal Ground
24 RVSS – Receive Analog Signal Ground
33 TCHBLK O Transmit Channel Block
53 TCHCLK O Transmit Channel Clock
46 TCLK I Transmit Clock

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PIN SYMBOL TYPE DESCRIPTION
40 TCLKI I Transmit Clock Input
41 TCLKO O Transmit Clock Output
50 TDATA I Transmit Data
49 TESO O Transmit Elastic Store Output
14 TEST I Test
34 TLCLK O Transmit Link Clock
35 TLINK I Transmit Link Data
39 TNEGI I Transmit Negative Data Input
42 TNEGO O Transmit Negative Data Output
38 TPOSI I Transmit Positive Data Input
43 TPOSO O Transmit Positive Data Output
32 TRING O Transmit Analog Ring Output
47 TSER I Transmit Serial Data
48 TSIG I Transmit Signaling Input
52 TSSYNC I Transmit System Sync
37 TSYNC I/O Transmit Sync
51 TSYSCLK I Transmit System Clock
29 TTIP O Transmit Analog Tip Output
31 TVDD – Transmit Analog Positive Supply
30 TVSS – Transmit Analog Signal Ground
77 WR*(R/W*) I Write Input(Read/Write)
22 XTALD O Quartz Crystal Driver
4.1 PIN FUNCTION DESCRIPTION
4.1.1 Transmit Side Pins
Signal Name: TCLK
Signal Description: Transmit Clock
Signal Type: Input
A 2.048 MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name: TSER
Signal Description: Transmit Serial Data
Signal Type: Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name: TCHCLK
Signal Description: Transmit Channel Clock
Signal Type: Output
A 256 kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is
enabled. Useful for parallel to serial conversion of channel data.

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Signal Name: TCHBLK
Signal Description: Transmit Channel Block
Signal Type: Output
A user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384 kbps (H0), 768
kbps or ISDN–PRI . Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See Section 12 for details.
Signal Name: TSYSCLK
Signal Description: Transmit System Clock
Signal Type: Input
1.544 MHz , 2.048 MHz , 4.096 MHz or 8.192 MHz clock. Only used when the transmit side elastic
store function is enabled. Should be tied low in applications that do not use the transmit side elastic store.
See section 18 on page 86 for details on 4.096 MHz and 8.192 MHz operation using the Interleave Bus
Option.
Signal Name: TLCLK
Signal Description: Transmit Link Clock
Signal Type: Output
4 kHz to 20 kHz demand clock (Sa bits) for the TLINK input. See Section 18 for details.
Signal Name: TLINK
Signal Description: Transmit Link Data
Signal Type: Input
If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination
of the Sa bit positions (Sa4 to Sa8). See Section 14.1 for details.
Signal Name: TSYNC
Signal Description: Transmit Sync
Signal Type: Input / Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR1.1,
the DS21354/554 can be programmed to output either a frame or multiframe pulse at this pin. This pin
can also be configured as an input via TCR1.0. See Section 19 for details.
Signal Name: TSSYNC
Signal Description: Transmit System Sync
Signal Type: Input
Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or
multiframe boundaries for the transmit side. Should be tied low in applications that do not use the
transmit side elastic store.
Signal Name: TSIG
Signal Description: Transmit Signaling Input
Signal Type: Input
When enabled, this input will sample signaling bits for insertion into outgoing PCM E1 data stream.
Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit side elastic store is enabled.

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Signal Name: TESO
Signal Description: Transmit Elastic Store Data Output
Signal Type: Output
Updated on the rising edge of TCLK with data out of the transmit side elastic store whether the elastic
store is enabled or not. This pin is normally tied to TDATA.
Signal Name: TDATA
Signal Description: Transmit Data
Signal Type: Input
Sampled on the falling edge of TCLK with data to be clocked through the transmit side formatter. This
pin is normally tied to TESO.
Signal Name: TPOSO
Signal Description: Transmit Positive Data Output
Signal Type: Output
Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. Can be
programmed to source NRZ data via the Output Data Format (TCR2.2) control bit. This pin is normally
tied to TPOSI.
Signal Name: TNEGO
Signal Description: Transmit Negative Data Output
Signal Type: Output
Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. This pin is
normally tied to TNEGI.
Signal Name: TCLKO
Signal Description: Transmit Clock Output
Signal Type: Output
Buffered output of signal that is clocking data through the transmit side formatter. This pin is normally
tied to TCLKI.
Signal Name: TPOSI
Signal Description: Transmit Positive Data Input
Signal Type: Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally
connected to TPOSO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ
applications.
Signal Name: TNEGI
Signal Description: Transmit Negative Data Input
Signal Type: Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally
connected to TNEGO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ
applications.
Signal Name: TCLKI
Signal Description: Transmit Clock Input
Signal Type: Input
Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high.

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4.1.2 Receive Side Pins
Signal Name: RLINK
Signal Description: Receive Link Data
Signal Type: Output
Updated with the full recovered E1 data stream on the rising edge of RCLK.
Signal Name: RLCLK
Signal Description: Receive Link Clock
Signal Type: Output
4 kHz to 20 kHz clock (Sa bits) for the RLINK output. See Section 15 for details.
Signal Name: RCLK
Signal Description: Receive Clock
Signal Type: Output
2.048 MHz clock that is used to clock data through the receive side framer.
Signal Name: RCHCLK
Signal Description: Receive Channel Clock
Signal Type: Output
A 256 kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data.
Signal Name: RCHBLK
Signal Description: Receive Channel Block
Signal Type: Output
A user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384 kbps service, 768
kbps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See Section 12 for details.
Signal Name: RSER
Signal Description: Receive Serial Data
Signal Type: Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name: RSYNC
Signal Description: Receive Sync
Signal Type: Input/Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC
multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an
input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.

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Signal Name: RFSYNC
Signal Description: Receive Frame Sync
Signal Type: Output
An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries.
Signal Name: RMSYNC
Signal Description: Receive Multiframe Sync
Signal Type: Output
If the receive side elastic store is enabled, an extracted pulse, one RSYSCLK wide, is output at this pin
which identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will
output multiframe boundaries associated with RCLK.
Signal Name: RDATA
Signal Description: Receive Data
Signal Type: Output
Updated on the rising edge of RCLK with the data out of the receive side framer.
Signal Name: RSYSCLK
Signal Description: Receive System Clock
Signal Type: Input
1.544 MHz , 2.048 MHz , 4.096 MHz or 8.192 MHz clock. Only used when the receive side elastic store
function is enabled. Should be tied low in applications that do not use the receive side elastic store. See
section 18 on page 115 for details on 4.096 MHz and 8.192 MHz operation using the Interleave Bus
Option.
Signal Name: RSIG
Signal Description: Receive Signaling Output
Signal Type: Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name: RLOS/LOTC
Signal Description: Receive Loss of Sync / Loss of Transmit Clock
Signal Type: Output
A dual function output that is controlled by the TCR2.0 control bit. This pin can be programmed to either
toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5 µsec.
Signal Name: RCL
Signal Description: Receive Carrier Loss
Signal Type: Output
Set high when the line interface detects a carrier loss.
Signal Name: RSIGF
Signal Description: Receive Signaling Freeze
Signal Type: Output
Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert
downstream equipment of the condition.

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Signal Name: 8MCLK
Signal Description: 8 MHz Clock
Signal Type: Output
An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name: RPOSO
Signal Description: Receive Positive Data Input
Signal Type: Output
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally
tied to RPOSI.
Signal Name: RNEGO
Signal Description: Receive Negative Data Input
Signal Type: Output
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally
tied to RPOSI.
Signal Name: RCLKO
Signal Description: Receive Clock Output
Signal Type: Output
Buffered recovered clock from the T1 line. This pin is normally tied to RCLKI.
Signal Name: RPOSI
Signal Description: Receive Positive Data Input
Signal Type: Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and
RNEGI can be tied together for a NRZ interface. Can be internally connected to RPOSO by tying the
LIUC pin high.
Signal Name: RNEGI
Signal Description: Receive Negative Data Input
Signal Type: Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and
RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the
LIUC pin high.
Signal Name: RCLKI
Signal Description: Receive Clock Input
Signal Type: Input
Clock used to clock data through the receive side framer. This pin is normally tied to RCLKO. Can be
internally connected to RCLKO by tying the LIUC pin high.
4.1.3 Parallel Control Port Pins
Signal Name: INT*
Signal Description: Interrupt
Signal Type: Output
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2
and the HDLC Status Register. Active low, open drain output