Davicom DM9000 User manual

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 1
Version: DM9000-DS-F02
June 26, 2002
1. General Description
The DM9000 is a fully integrated and cost-effective
single chip Fast Ethernet MAC controller with a
general processor interface, a 10/100M PHY and 4K
Dword SRAM. It is designed with low power and high
performance process that support 3.3V with 5V
tolerance.
The DM9000 also provides a MII interface to connect
HPNA device or other transceivers that support MII
interface. The DM9000 supports 8-bit, 16-bit and 32-
bit uP interfaces to internal memory accesses for
different processors. The PHY of the DM9000 can
interface to the UTP3, 4, 5 in 10Base-T and UTP5 in
100Base-TX. It is fully compliant with the IEEE 802.3u Spec.
Its auto-negotiation function will automatically configure the
DM9000 to take the maximum advantage of its abilities. The
DM9000 also supports IEEE 802.3x full- duplex flow control.
This programming of the DM9000 is very simple, so user
can port the software drivers to any system easily.
2. Block Diagram
EEPROM
Interface
External MII
Interface
LED
TX+/-
RX+/-
MII Management
Control
& MII Register
Autonegotiation
Memory
Management
RX Machine
TX Machine
MAC
MII
100 Base-TX
PCS
100 Base-TX
transceiver
10 Base-T
Tx/Rx
PHYceiver
Control &Status
Registers
Internal
SRAM
Processor
Interface

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
2Final
Version: DM9000-DS-F02
June 26, 2002
Table of Contents
1. General Description ..............................................1
2. Block Diagram……………………………………… 1
3. Features ................................................................4
4. Pin Configuration ..................................................5
4.1 Pin Configuration I: with MII Interface.................5
4.2 Pin Configuration II: with 32-Bit Data Bus...........6
5. Pin Description......................................................7
5.1 MII Interface ........................................................7
5.2 Processor Interface.............................................8
5.3 EEPROM Interface. ............................................9
5.4 Clock Interface ....................................................9
5.5 LED Interface ......................................................9
5.6 10/100 PHY/Fiber .............................................10
5.7 Miscellaneous Pins ...........................................10
5.8 Power Pins........................................................10
6. Vendor Control and Status Register Set.............11
6.1 Network Control Register (00H)........................13
6.2 Network Status Register (01H) .........................13
6.3 TX Control Register (02H) ................................13
6.4 TX Status Register I (03H)................................14
6.5 TX Status Register II (04H)...............................14
6.6 RX Control Register (05H)................................14
6.7 RX Status Register (06H) .................................15
6.8 Receive Overflow Counter Register (07H) .......15
6.9 Back Pressure Threshold Register (08H) .........15
6.10 Flow Control Threshold Register (09H) ..........16
6.11 RX/TX Flow Control Register (0AH) ...............16
6.12 EEPROM & PHY Control Register (0BH) .......16
6.13 ROM & PHY Address Register (0CH) ............17
6.14 EEPROM & PHY Data Register (0DH, 0EH)..17
6.15 Wake Up Control Register (0FH)....................17
6.16 Physical Address Register (10H~15H) ...........17
6.17 Multicast Address Register (16H~1DH)..........18
6.18 General Purpose Control Register (1EH)…….18
6.19 General Purpose Register (1FH) ....................18
6.20 TX SRAM Read Pointer Address Register
(22H~23H) ..............................................................18
6.21 RX SRAM Write Pointer Address Register
(24H~25H) .......................................................19
6.22 Vendor ID Register (28H~29H).......................19
6.23 Product ID Register (2AH~2BH) .....................19
6.24 Chip Revision Register (2CH).........................19
6.25 Special Mode Control Register (2FH).............19
6.26 Memory Data Read Command without Address
Increment Register (F0H) ................................19
6.27 Memory Data Read Command with Address
Increment Register (F2H) ................................19
6.28 Memory Data Read_ address Register
(F4H~F5H) ......................................................19
6.29 Memory Data Write Command without Address
Increment Register (F6H) ................................19
6.30 Memory Data Write Command with Address
Increment Register (F8H) ................................19
6.31 Memory Data Write_ address Register
(FAH~FBH) ......................................................20
6.32 TX Packet Length Register (FCH~FDH) ........20
6.33 Interrupt Status Register (FEH) ......................20
6.34 Interrupt Mask Register (FFH) ........................20
7. EEPROM Format ................................................21
8. MII Register Description......................................22
8.1 Basic Mode Control Register (BMCR) – 00 ......23
8.2 Basic Mode Status Register (BMSR) – 01........24
8.3 PHY ID Identifier Register #1 (PHYID1) – 02 ...25
8.4 PHY Identifier Register #2 (PHYID2) – 03........25
8.5 Auto-negotiation Advertisement Register
(ANAR) – 04 ....................................................26
8.6 Auto-negotiation Link Partner Ability Register
(ANLPAR) – 05 ................................................27
8.7 Auto-negotiation Expansion Register (ANER) –
06 .....................................................................27
8.8 DAVICOM Specified Configuration Register
(DSCR) – 16 .....................................................28
8.9 DAVICOM Specified Configuration and Status
Register (DSCSR) – 17 ...................................29
8.10 10BASE-T Configuration/Status (10BTCSR) –
18.....................................................................30

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 3
Version: DM9000-DS-F02
June 26, 2002
9. Functional Description ........................................31
9.1 Host Interface....................................................31
9.2 Direct Memory Access Control .........................31
9.3 Packet Transmission.........................................31
9.4 Packet Reception..............................................31
9.5 100Base-TX Operation .....................................32
9.5.1 4B5B Encoder................................................32
9.5.2 Scrambler.......................................................32
9.5.3 Parallel to Serial Converter............................32
9.5.4 NRZ to NRZI Encoder....................................32
9.5.5 MLT-3 Converter............................................32
9.5.6 MLT-3 Driver ..................................................32
9.5.7 4B5B Code Group..........................................33
9.6 100Base-TX Receiver.......................................34
9.6.1 Signal Detect..................................................34
9.6.2 Adaptive Equalization ....................................34
9.6.3 MLT-3 to NRZI Decoder.................................34
9.6.4 Clock Recovery Module .................................34
9.6.5 NRZI to NRZ ..................................................34
9.6.6 Serial to Parallel.............................................34
9.6.7 Descrambler...................................................34
9.6.8 Code Group Alignment ..................................35
9.6.9 4B5B Decoder................................................35
9.7 10Base-T Operation..........................................35
9.8 Collision Detection ............................................35
9.9 Carrier Sense....................................................35
9.10 Auto-Negotiation .............................................35
9.11 Power Reduced Mode ....................................36
9.11.1 Power Down Mode.......................................36
9.11.2 Reduced Transmit Power Mode ..................36
10. DC and AC Electrical Characteristics ...............37
10.1 Absolute Maximum Rating (25∘C) ................37
10.2 Operating Conditions ......................................37
10.3 DC Electrical Characteristics ..........................38
10.4 AC Electrical Characteristics & Timing
Waveforms.......................................................39
10.4.1 TP Interface .................................................39
10.4.2 Oscillator/ Crystal Timing.............................39
10.4.3 Processor Register Read Timing.................39
10.4.4 Processor Register Write Timing .................40
10.4.5 External MII Interface Transmit Timing........41
10.4.6 External MII Interface Receive Timing.........41
10.4.7 MII Management Interface Timing ...............42
10.4.8 EEPROM Interface Timing ..........................42
11. Application Notes ..............................................43
11.1 Network Interface Signal Routing ...................43
11.2 10Base-T/100Base-TX Application Figure 11-1
.........................................................................43
11.3 10Base-T/100Base-TX (Power Reduction
Application) Figure 11-2................................44
11.4 Power Decoupling Capacitors Figure 11-3 .....45
11.5 Ground Plane Layout Figure 11-4 ..................46
11.6 Power Plane Partitioning Figure 11-5 .............47
11.7 Magnetics Selection Guide .............................48
11.8 Crystal Selection Guide Figure 11-6...............48
11.9 Application of reverse MII Figure 11-7............49
12. Package Information .........................................50
12.1 LQFP 100L Outline Dimensions .....................50
13. Appendix ...........................................................51
14. Order Information..............................................53

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
4Final
Version: DM9000-DS-F02
June 26, 2002
3. Features
■Supports processor interface: byte/word/dword of
I/O command to internal memory data operation
■Integrated 10/100M transceiver
■Supports MII and reverses MII interface
■Supports back pressure mode for half-duplex
mode flow control
■IEEE802.3x flow control for full-duplex mode
■Supports wakeup frame, link status change and
magic packet events for remote wake up
■Integrated 4K dword SRAM
■Supports automatically load vendor ID and
product ID from EEPROM
■Supports 4 GPIO pins
■Optional EEPROM configuration
■Very low power consumption mode:
–Power reduced mode (cable detection)
–Power down mode
–Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
■Compatible with 3.3V and 5.0V tolerant I/O
■100-pin LQFP with CMOS process

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 5
Version: DM9000-DS-F02
June 26, 2002
4. Pin Configuration
4.1 Pin Configuration I: with MII Interface
11
DM9000
75
74
73
72 71
70
69
68
67
66
65
64
63 62 61
60
59 58
57
56 55
54 53 52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
76
TXD1
1 2
3 4
5 6 7 8 9
10 12 13 14 15 16
17 18
19
20
21
22
23
24 25
BGRES
DGND
NC
LINK_O
WAKEUP
PW_RST#
DGND
SD12
IOR#
77
78
79
80
81
82
83
84
85
SD15
SD14
SD13
SD8
SD11
SD10
SD9
SA4
DVDD
IO16
CMD
SA8
SA5
SA6
SA7
SA9
DGND
INT
IOW#
AEN
IOWAIT
DVDD
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
RST
DGND
TEST1 TEST2 TEST3 TEST4
DVDD
X2_25M X1_25M
DGND
SD
AGND
AVDD
AVDD
RXI+
RXI-
AGND
AGND
TXO+
TXO-
AVDD
DVDD
LINK_I
RXD0
RXD1
RXD2
RXD3
DGND
CRS
COL
RX_DV
RX_ER
RX_CLK
TEST5
TX_CLK
TXD0
TXD2 TXD3 TX_EN DVDD MDIO MDC DGND CLK20MO SPEED# DUP# LINKACT# DGND EEDI EEDO EECK EECS GPIO0 GPIO1 GPIO2 GPIO3 DVDD DVDD NC NC

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6Final
Version: DM9000-DS-F02
June 26, 2002
4.2 Pin Configuration II: with 32-Bit Data Bus
11
DM9000
75
74
73
72 71
70
69
68
67
66
65
64
63 62 61
60
59 58
57
56 55
54 53 52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
76
SD19
1 2
3
4
5 6 7 8 9
10 12 13 14 15 16
17 18
19
20
21
22
23
24 25
BGRES
DGND
NC
LINK_O
WAKEUP
PW_RST#
DGND
SD12
IOR#
77
78
79
80
81
82
83
84
85
SD15
SD14
SD13
SD8
SD11
SD10
SD9
SA4
DVDD
IO16
CMD
SA8
SA5
SA6
SA7
SA9
DGND
INT
IOW#
AEN
IOWAIT
DVDD
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
RST
DGND
TEST1 TEST2 TEST3 TEST4
DVDD
X2_25M X1_25M
DGND
SD
AGND
AVDD
AVDD
RXI+
RXI-
AGND
AGND
TXO+
TXO-
AVDD
DVDD
SD31
SD30
SD29
SD28
SD27
DGND
SD26
SD25
SD24
SD23
SD22
TEST5
SD21
SD20
SD18 SD17 NC DVDD SD16 IO32 DGND CLK20MO SPEED# DUP# LINKACT# DGND EEDI EEDO EECK EECS GPIO0 GPIO1 GPIO2 GPIO3 DVDD DVDD NC NC
-

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 7
Version: DM9000-DS-F02
June 26, 2002
5. Pin Description
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,
LI= reset Latch Input, #= asserted low
5.1 MII Interface
Pin No. Pin Name I/O Description
37 LINK_I I External MII device link status
41,40,39,
38
RXD [3:0] I External MII Receive Data
4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode
43 CRS I/O External MII Carrier Sense
Active high to indicate the pressure of carrier, due to receive or transmit activities
in 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface.
44 COL I/O External MII Collision Detect. This pin is output in reverse MII interface.
45 RX_DV I External MII Receive Data Valid
46 RX_ER I External MII Receive Error
47 RX_CLK I External MII Receive Clock
49 TX_CLK I/O External MII Transmit Clock. This pin is output in reverse MII interface.
53,52,51,
50
TXD [3:0] O External MII Transmit Data
4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps
nibble mode
TXD [2:0] is also used as the strap pins of IO base address.
IO base = (strap pin value of TXD [2:0]) * 10H + 300H
54 TX_ EN O External MII Transmit Enable
56 MDIO I/O MII Serial Management Data
57 MDC O MII Serial Management Data Clock
This pin is also used as the strap pin of the polarity of the INT pin
When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin
is high active
Note: The pins of MII interface are all have a pulled down resistor about 60k ohm internally
5.2 Processor Interface
1 IOR# I Processor Read Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
2 IOW# I Processor Write Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
3 AEN I Address Enable
A low active signal used to select the DM9000.
4 IOWAIT O Processor Command Ready
When a command is issued before last command is completed, the IOWAIT will
be pulled low to indicate the current command is waited

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
8Final
Version: DM9000-DS-F02
June 26, 2002
14 RST I Hardware Reset Command, active high to reset the DM9000
6,7,8,9,10,
11,12,13,
89,88,87,
86,85,84,
83,82
SD0~15 I/O Processor Data Bus bit 0~15
93,94,95,
96,97,98
SA4~9 I Address Bus 4~9
These pins are used to select the DM9000.
When SA9 and SA8 are in high states, and SA7 and AEN are in low
states, and SA6~4 are matched with strap pins TXD2~0, the DM9000 is
selected.
92 CMD I Command Type
When high, the access of this command cycle is DATA port
When low, the access of this command cycle is ADDRESS port
91 IO16 O Word Command Indication
When the access of internal memory is word or dword width, this pin will
be asserted
This pin is low active at default
100 INT O Interrupt Request
This pin is high active at default, its polarity can be modified by EEPROM
setting or strap pin MDC. See the EEPROM content description for detail
56,53,52,
51,50,49,
47,46,45,
44,43,41,
40,39,38
37
SD16~31 (in
double word
mode)
I/O Processor Data Bus bit 16~31
These pins are used as data bus bits 16~31 when the DM9000 is set to
double word mode (the straps pin EEDO is pulled high and WAKEUP is
not pull-high)
57 IO32 (in double
word mode)
O Double Word Command Indication
This pins is used as the double word command indication when the
DM9000 is set to double data word mode, and this pin will be asserted
when the access of internal memory is double word width
This pin is low active at default
Note: The pins of processor interface except SD8,SD9 and IO16 are all have a pulled down resistor about 60k ohm
internally
5.3 EEPROM Interface
64 EEDI I Data from EEPROM
65 EEDO I/O Data to EEPROM
This pin is also used as a strap pin. It combines with strap pin WAKEUP,
and it can set the data width of the internal memory access
The decoder table is the following, where the logic 1 means the strap pin
is pulled high
WAKEUP EEDO data width
0 0 16-bit
0 1 32-bit
1 0 8-bit
1 1 reserved

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 9
Version: DM9000-DS-F02
June 26, 2002
66 EECK O Clock to EEPROM
67 EECS I/O Chip Select to EEPROM
This pin is also used as a strap pin to define the LED modes.
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS,EECK and EEDO are all have a pulled down resistor about 60k ohm internally
5.4 Clock Interface
21 X2_25M O Crystal 25MHz Out
22 X1_25M I Crystal 25MHz In
59 CLK20MO O 20Mhz Clock Output
It is used as the clock signal for the external MII device’s clock is 20MHz
This pin has a pulled down resistor about 60k ohm internally.
5.5 LED Interface
60 SPEED100# O Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY
61 DUP# O Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the internal
PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
62 LINK&ACT# O Link LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
5.6 10/100 PHY/Fiber
24 SD I Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
25 BGGND P Bandgap Ground
26 BGRES I/O Bandgap Pin
27 AVDD P Bandgap and Guard Ring Power
28 AVDD P RX Power
29 RXI+ I TP RX Input
30 RXI- I TP RX Input
31 AGND P RX Ground
32 AGND P TX Ground
33 TXO+ O TP TX Output

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
10 Final
Version: DM9000-DS-F02
June 26, 2002
34 TXO- O TP TX Output
35 AVDD P TX Power
5.7 Miscellaneous
16,17,18,
19
TEST1~TEST4 I Operation Mode
Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application
48 TEST5 I It must be ground.
68,69,70,
71
GPIO0~3 I/O General I/O Ports
Registers GPCR and GPR can program these pins
The GPIO0 is an output mode, and output data high at default is to power
down internal PHY and other external MII device
GPIO1~3 defaults are input ports
78 LINK_O O Cable Link Status Output. Active High
This pin is also used as a strap pin to define whether the MII interface is a
reversed MII interface (pulled high) or a normal MII interface (not pulled
high). This pin has a pulled down resistor about 60k ohm internally.
79 WAKEUP O Issue a wake up signal when wake up event happens
This pin has a pulled down resistor about 60k ohm internally.
80 PW_RST# I Power on Reset
Active low signal to initiate the DM9000
The DM9000 is ready after 5us when this pin deasserted
74,75,77 NC Not Connect
5.8 Power Pins
5,20,36,
55,72,90,
73
DVDD P Digital VDD
15,23,42,
58,63,81,
99,76
DGND P Digital GND

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 11
Version: DM9000-DS-F02
June 26, 2002
6. Vendor Control and Status Register Set
The DM9000 implements several control and status
registers, which can be accessed by the host. These CSRs
are byte aligned. All CSRs are set to their default values by
hardware or software reset unless they are specified
Register Description Offset Default value
after reset
NCR Network Control Register 00H 00H
NSR Network Status Register 01H 00H
TCR TX Control Register 02H 00H
TSR I TX Status Register I 03H 00H
TSR II TX Status Register II 04H 00H
RCR RX Control Register 05H 00H
RSR RX Status Register 06H 00H
ROCR Receive Overflow Counter Register 07H 00H
BPTR Back Pressure Threshold Register 08H 37H
FCTR Flow Control Threshold Register 09H 38H
FCR RX Flow Control Register 0AH 00H
EPCR EEPROM & PHY Control Register 0BH 00H
EPAR EEPROM & PHY Address Register 0CH 40H
EPDRL EEPROM & PHY Low Byte Data Register 0DH XXH
EPDRH EEPROM & PHY High Byte Data Register 0EH XXH
WCR Wake Up Control Register 0FH 00H
PAR Physical Address Register 10H-15H Determined by
EEPROM
MAR Multicast Address Register 16H-1DH XXH
GPCR General Purpose Control Register 1EH 01H
GPR General Purpose Register 1FH XXH
TRPAL TX SRAM Read Pointer Address Low Byte 22H 00H
TRPAH TX SRAM Read Pointer Address High Byte 23H 00H
RWPAL RX SRAM Write Pointer Address Low Byte 24H 04H
RWPAH RX SRAM Write Pointer Address High Byte 25H 0CH
VID Vendor ID 28H-29H 0A46H
PID Product ID 2AH-2BH 9000H
CHIPR CHIP Revision 2CH 00H
SMCR Special Mode Control Register 2FH 00H
MRCMDX Memory Data Read Command Without Address Increment
Register
F0H XXH
MRCMD Memory Data Read Command With Address Increment
Register
F2H XXH
MRRL Memory Data Read_ address Register Low Byte F4H 00H
MRRH Memory Data Read_ address Register High Byte F5H 00H
MWCMDX Memory Data Write Command Without Address Increment
Register
F6H XXH
MWCMD Memory Data Write Command With Address Increment
Register
F8H XXH
MWRL Memory Data Write_ address Register Low Byte FAH 00H

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
12 Final
Version: DM9000-DS-F02
June 26, 2002
MWRH Memory Data Write _ address Register High Byte FBH 00H
TXPLL TX Packet Length Low Byte Register FCH XXH
TXPLH TX Packet Length High Byte Register FDH XXH
ISR Interrupt Status Register FEH 00H
IMR Interrupt Mask Register FFH 00H
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where：
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 13
Version: DM9000-DS-F02
June 26, 2002
6.1 Network Control Register (00H)
Bit Name Default Description
7 EXT_PHY 0,RW Selects external PHY when set. Selects Internal PHY when clear. This bit will not
be affected after software reset
6 WAKEEN 0,RW Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
5 RESERVED 0,RO Reserved
4 FCOL 0,RW Force Collision Mode, used for testing
3 FDX 0,RW Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
2:1 LBK 00,RW Loopback Mode
Bit 2 1
0 0 Normal
0 1 MAC Internal loopback
1 0 Internal PHY 100M mode digital loopback
1 1 (Reserved)
0 RST 0,RW Software reset and auto clear after 10us
6.2 Network Status Register (01H)
Bit Name Default Description
7 SPEED 0,RO Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no
meaning when LINKST=0
6 LINKST 0,RO Link Status 0:link failed 1:link OK, when Internal PHY is used
5 WAKEST 0,RW/C1 Wakeup Event Status. Clears by read or write 1
This bit will not be affected after software reset
4 RESERVED 0,RO Reserved
3 TX2END 0,RW/C1 TX Packet 2 Complete Status. Clears by read or write 1
Transmit completion of packet index 2
2 TX1END 0,RW/C1 TX Packet 1 Complete status. Clears by read or write 1
Transmit completion of packet index 1
1 RXOV 0,RO RX FIFO Overflow
0 RESERVED 0,RO Reserved
6.3 TX Control Register (02H)
Bit Name Default Description
7 RESERVED 0,RO Reserved
6TJDIS0,RW
Transmit Jabber Disable
When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is Enable
5EXCECM0,RW
Excessive Collision Mode Control : 0:aborts this packet when excessive collision
counts more than 15, 1: still tries to transmit this packet
4 PAD_DIS2 0,RW PAD Appends Disable for Packet Index 2
3 CRC_DIS2 0,RW CRC Appends Disable for Packet Index 2
2 PAD_DIS1 0,RW PAD Appends Disable for Packet Index 1
1 CRC_DIS1 0,RW CRC Appends Disable for Packet Index 1
0 TXREQ 0,RW TX Request. Auto clears after sending completely

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
14 Final
Version: DM9000-DS-F02
June 26, 2002
6.4 TX Status Register I ( 03H ) for packet index I
Bit Name Default Description
7 TJTO 0,RO Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted
6 LC 0,RO Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal loopback mode
5NC0,RONoCarrier
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal loopback mode
4 LC 0,RO Late Collision
It is set when a collision occurs after the collision window of 64 bytes
3 COL 0,RO Collision Packet
It is set to indicate that the collision occurs during transmission
2 EC 0,RO Excessive Collision
It is set to indicate that the transmission is aborted due to 16 excessive collisions
1:0 RESERVED 0,RO Reserved
6.5 TX Status Register II ( 04H ) for packet index I I
Bit Name Default Description
7 TJTO 0,RO Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted
6 LC 0,RO Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal loopback mode
5NC0,RONoCarrier
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal loopback mode
4 LC 0,RO Late Collision
It is set when a collision occurs after the collision window of 64 bytes
3 COL 0,RO Collision packet, collision occurs during transmission
2 EC 0,RO Excessive Collision
It is set to indicate that the transmission is aborted due to 16 excessive collisions
1:0 RESERVED 0,RO Reserved
6.6 RX Control Register ( 05H )
Bit Name Default Description
7 RESERVED 0,RO Reserved
6WTDIS 0,RW Watchdog Timer Disable
When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabled
5 DIS_LONG 0,RW Discard Long Packet
Packet length is over 1522byte
4 DIS_CRC 0,RW Discard CRC Error Packet
3 ALL 0,RW Pass All Multicast
2 RUNT 0,RW Pass Runt Packet
1 PRMSC 0,RW Promiscuous Mode
0 RXEN 0,RW RX Enable

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 15
Version: DM9000-DS-F02
June 26, 2002
6.7 RX Status Register ( 06H )
Bit Name Default Description
7 RF 0,RO Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes
6 MF 0,RO Multicast Frame
It is set to indicate that the received frame has a multicast address
5 LCS 0,RO Late Collision Seen
It is set to indicate that a late collision is found during the frame reception
4 RWTO 0,RO Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes
3 PLE 0,RO Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception
2 AE 0,RO Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary
1 CE 0,RO CRC Error
It is set to indicate that the received frame ends with a CRC error
0 FOE 0,RO FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
6.8 Receive Overflow Counter Register ( 07H )
Bit Name Default Description
7 RXFU 0,R/C Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
6:0 ROC 0,R/C Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
6.9 Back Pressure Threshold Register (08H)
Bit Name Default Description
7:4 BPHW 3H, RW Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
when RX SRAM free space is lower than this threshold value
Default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
3:0 JPT 7H, RW Jam Pattern Time. Default is 200us
bit3 bit2 bit1 bit0 time
0 0 0 0 5us
0 0 0 1 10us
0 0 1 0 15us
0 0 1 1 25us
0 1 0 0 50us
0 1 0 1 100us
0 1 1 0 150us
0 1 1 1 200us
1 0 0 0 250us
1 0 0 1 300us
1 0 1 0 350us
1 0 1 1 400us
1 1 0 0 450us
1 1 0 1 500us
1 1 1 0 550us
1 1 1 1 600us

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
16 Final
Version: DM9000-DS-F02
June 26, 2002
6.10 Flow Control Threshold Register ( 09H )
Bit Name Default Description
7:4 HWOT 3H, RW RX FIFO High Water Overflow Threshold
Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its means no free RX SRAM space.
Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes)
3:0 LWOT 8H, RW RX FIFO Low Water Overflow Threshold
Send a pause packet with pause_time=0000 when RX SRAM free space is larger
than this value. This pause packet is enabled after the high water pause packet is
transmitted. Default SRAM free space is 8K-byte. Please do not exceed SRAM size
(1 unit=1K bytes)
6.11 RX/TX Flow Control Register ( 0AH )
Bit Name Default Description
7 TXP0 0,RW TX Pause Packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
6 TXPF 0,RW TX Pause packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
5 TXPEN 0,RW Force TX Pause Packet Enable
Enables the pause packet for high/low water threshold control
4 BKPA 0,RW Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when any packet
comes and RX SRAM is over BPHW
3 BKPM 0,RW Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW
2 RXPS 0,R/C RX Pause Packet Status, latch and read clearly
1 RXPCS 0,RO RX Pause Packet Current Status
0FLCE0,RW
Flow Control Enable
Set to enable the flow control mode (i.e. to disable TX function)
6.12 EEPROM & PHY Control Register ( 0BH )
Bit Name Default Description
7:6 RESERVED 0,RO Reserved
5 REEP 0,RW Reload EEPROM. Driver needs to clear it up after the operation completes
4 WEP 0,RW Write EEPROM Enable
3 EPOS 0,RW EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
2 ERPRR 0,RW EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
1 ERPRW 0,RW EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
0 ERRE 0,RO EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 17
Version: DM9000-DS-F02
June 26, 2002
6.13 EEPROM & PHY Address Register ( 0CH )
Bit Name Default Description
7:6 PHY_ADR 01,RW PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
5:0 EROA 0,RW EEPROM Word Address or PHY Register Address
6.14 EEPROM & PHY Data Register (EE_PHY_L：
：：
：0DH EE_PHY_H：
：：
：0EH)
Bit Name Default Description
7:0 EE_PHY_L X,RW EEPROM or PHY Low Byte Data
This data is made to write low byte of word address defined in Reg. CH to
EEPROM or PHY
7:0 EE_PHY_H X,RW EEPROM or PHY High Byte Data
This data is made to write high byte of word address defined in Reg. CH to
EEPROM or PHY
6.15 Wake Up Control Register ( 0FH )
Bit Name Type Description
7:6 RESERVED 0,RO Reserved
5 LINKEN 0,RW When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
4 SAMPLEEN 0,RW When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset
3 MAGICEN 0,RW When set, it enables Magic Packet Wake up Event
This bit will not be affected after software reset
2 LINKST 0,RO When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
1 SAMPLEST 0,RO When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
0 MAGICST 0,RO When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset
6.16 Physical Address Register ( 10H~15H )
Bit Name Default Description
7:0 PAB5 X,RW Physical Address Byte 5 (15H)
7:0 PAB4 X,RW Physical Address Byte 4 (14H)
7:0 PAB3 X,RW Physical Address Byte 3 (13H)
7:0 PAB2 X,RW Physical Address Byte 2 (12H)
7:0 PAB1 X,RW Physical Address Byte 1 (11H)
7:0 PAB0 X,RW Physical Address Byte 0 (10H)

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
18 Final
Version: DM9000-DS-F02
June 26, 2002
6.17 Multicast Address Register ( 16H~1DH )
Bit Name Default Description
7:0 MAB7 X,RW Multicast Address Byte 7 (1DH)
7:0 MAB6 X,RW Multicast Address Byte 6 (1CH)
7:0 MAB5 X,RW Multicast Address Byte 5 (1BH)
7:0 MAB4 X,RW Multicast Address Byte 4 (1AH)
7:0 MAB3 X,RW Multicast Address Byte 3 (19H)
7:0 MAB2 X,RW Multicast Address Byte 2 (18H)
7:0 MAB1 X,RW Multicast Address Byte 1 (17H)
7:0 MAB0 X,RW Multicast Address Byte 0 (16H)
6.18 General purpose control Register ( 1EH )
Bit Name Default Description
7:4 RESERVED 0,RO Reserved
3:0 GEP_CNTL 0001,RW General Purpose Control
Define the input/output direction of General Purpose Register
When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. GPIO0 default is output for POWER_DOWN function. Other defaults are
input
6.19 General purpose Register ( 1FH )
Bit Name Default Description
7:4 RESERVED 0,RO Reserved
3:1 GEPIO3-1 0,RW General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is reflected to pin GEPIO3-1
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from correspondent pins of GEPIO3-1
The GEPIOs are mapped to pins GEPIO3 to GEPIO1 respectively
0 GEPIO0 1,RW General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is the output to pin GEPIO0
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from pin GEPIO0. GEPIO0 default output 1 to
POWER_DOWN Internal PHY. Driver needs to clear this POWER_DOWN signal
by writing “0” when it wants PHY to be active. This default value can be
programmed by EEPROM. Please refer to the EEPROM description
6.20 TX SRAM Read Pointer Address Register (22H~23H)
Bit Name Default Description
7:0 TRPAH 00H,RO TX SRAM Read Pointer Address High Byte (23H)
7:0 TRPAL 00H.RO TX SRAM Read Pointer Address Low Byte (22H)
6.21 RX SRAM Write Pointer Address Register (24H~25H)
Bit Name Default Description
7:0 RWPAH 0CH,RO RX SRAM Write Pointer Address High Byte (25H)
7:0 RWPAL 04H.RO RX SRAM Write Pointer Address Low Byte (24H)

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 19
Version: DM9000-DS-F02
June 26, 2002
6.22 Vendor ID Register (28H~29H)
Bit Name Default Description
7:0 VIDH 0AH,RO Vendor ID High Byte (29H)
7:0 VIDL 46H.RO Vendor ID Low Byte (28H)
6.23 Product ID Register (2AH~2BH)
Bit Name Default Description
7:0 PIDH 90H,RO Product ID High Byte (2BH)
7:0 PIDL 00H.RO Product ID Low Byte (2AH)
6.24 Chip Revision Register (2CH)
Bit Name Default Description
7:0 CHIPR 00H,RO CHIP Revision
6.25 Special Mode Control Register ( 2FH )
Bit Name Default Description
7 SM_EN 0,RW Special Mode Enable
6~3 RESERVED 0,RO Reserved
2 FLC 0,RW Force Late Collision
1 FB1 0,RW Force Longest Back-off time
0 FB0 0,RW Force Shortest Back-off time
6.26 Memory Data Read Command without Address Increment Register (F0H)
Bit Name Default Description
7:0 MRCMDX X,RO Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged
6.27 Memory Data Read Command with Address Increment Register (F2H)
Bit Name Default Description
7:0 MRCMD X,RO Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
6.28 Memory Data Read_address Register (F4H~F5H)
Bit Name Default Description
7:0 MDRAH 00H,R/W Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1
7:0 MDRAL 00H,R/W Memory Data Read_ address Low Byte
6.29 Memory Data Write Command without Address Increment Register (F6H)
Bit Name Default Description
7:0 MWCMDX X,WO Write data to TX SRAM. After the write of this command, the write pointer is
unchanged

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
20 Final
Version: DM9000-DS-F02
June 26, 2002
6.30 Memory data write command with address increment Register (F8H)
Bit Name Default Description
7:0 MWCMD X,WO Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1,2, or 4, depends
on the operator mode. (8-bit, 16-bit,32-bit respectively)
6.31 Memory data write_address Register (FAH~FBH)
Bit Name Default Description
7:0 MDRAH 00H,R/W Memory Data Write_ address High Byte
7:0 MDRAL 00H,R/W Memory Data Write_ address Low Byte
6.32 TX Packet Length Register (FCH~FDH)
Bit Name Default Description
7:0 TXPLH X,R/W TX Packet Length High byte
7:0 TXPLL X,,R/W TX Packet Length Low byte
6.33 Interrupt Status Register (FEH)
Bit Name Default Description
7:6 IOMODE 0, RO Bit 7 Bit 6
0 0 16-bit mode
0 1 32-bit mode
1 0 8-bit mode
1 1 Reserved
5~4 RESERVED 0,RO Reserved
3 ROOS 0,RW/C1 Receive Overflow Counter Overflow Latch
2 ROS 0,RW/C1 Rx Overflow Latch
1 PTS 0,RW/C1 Packet Transmitted Latch
0 PRS 0,RW/C1 Packet Received Latch
6.34 Interrupt Mask Register (FFH)
Bit Name Default Description
7 PAR 0,RW Enable the SRAM read/write pointer to automatically return to the start address
when pointer addresses are over the SRAM size. Driver needs to set. When driver
sets this bit, REG_F5 will set to 0Ch automatically
6~4 RESERVED 0,RO Reserved
3 ROOM 0,RW Enable Receive Overflow Counter Overflow Latch
2 ROM 0,RW Enable RX Overflow Latch
1 PTM 0,RW Enable Packet Transmitted Latch
0 PRM 0,RW Enable Packet Received Latch