Davicom DM9000 User manual

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 1
Version: DM9000-DS-F02
June 26, 2002
1. General Description
The DM9000 is a fully integrated and cost-effective
single chip Fast Ethernet MAC controller with a
general processor interface, a 10/100M PHY and 4K
Dword SRAM. It is designed with low power and high
performance process that support 3.3V with 5V
tolerance.
The DM9000 also provides a MII interface to connect
HPNA device or other transceivers that support MII
interface. The DM9000 supports 8-bit, 16-bit and 32-
bit uP interfaces to internal memory accesses for
different processors. The PHY of the DM9000 can
interface to the UTP3, 4, 5 in 10Base-T and UTP5 in
100Base-TX. It is fully compliant with the IEEE 802.3u Spec.
Its auto-negotiation function will automatically configure the
DM9000 to take the maximum advantage of its abilities. The
DM9000 also supports IEEE 802.3x full- duplex flow control.
This programming of the DM9000 is very simple, so user
can port the software drivers to any system easily.
2. Block Diagram
EEPROM
Interface
External MII
Interface
LED
TX+/-
RX+/-
MII Management
Control
& MII Register
Autonegotiation
Memory
Management
RX Machine
TX Machine
MAC
MII
100 Base-TX
PCS
100 Base-TX
transceiver
10 Base-T
Tx/Rx
PHYceiver
Control &Status
Registers
Internal
SRAM
Processor
Interface

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
2Final
Version: DM9000-DS-F02
June 26, 2002
Table of Contents
1. General Description ..............................................1
2. Block Diagram……………………………………… 1
3. Features ................................................................4
4. Pin Configuration ..................................................5
4.1 Pin Configuration I: with MII Interface.................5
4.2 Pin Configuration II: with 32-Bit Data Bus...........6
5. Pin Description......................................................7
5.1 MII Interface ........................................................7
5.2 Processor Interface.............................................8
5.3 EEPROM Interface. ............................................9
5.4 Clock Interface ....................................................9
5.5 LED Interface ......................................................9
5.6 10/100 PHY/Fiber .............................................10
5.7 Miscellaneous Pins ...........................................10
5.8 Power Pins........................................................10
6. Vendor Control and Status Register Set.............11
6.1 Network Control Register (00H)........................13
6.2 Network Status Register (01H) .........................13
6.3 TX Control Register (02H) ................................13
6.4 TX Status Register I (03H)................................14
6.5 TX Status Register II (04H)...............................14
6.6 RX Control Register (05H)................................14
6.7 RX Status Register (06H) .................................15
6.8 Receive Overflow Counter Register (07H) .......15
6.9 Back Pressure Threshold Register (08H) .........15
6.10 Flow Control Threshold Register (09H) ..........16
6.11 RX/TX Flow Control Register (0AH) ...............16
6.12 EEPROM & PHY Control Register (0BH) .......16
6.13 ROM & PHY Address Register (0CH) ............17
6.14 EEPROM & PHY Data Register (0DH, 0EH)..17
6.15 Wake Up Control Register (0FH)....................17
6.16 Physical Address Register (10H~15H) ...........17
6.17 Multicast Address Register (16H~1DH)..........18
6.18 General Purpose Control Register (1EH)…….18
6.19 General Purpose Register (1FH) ....................18
6.20 TX SRAM Read Pointer Address Register
(22H~23H) ..............................................................18
6.21 RX SRAM Write Pointer Address Register
(24H~25H) .......................................................19
6.22 Vendor ID Register (28H~29H).......................19
6.23 Product ID Register (2AH~2BH) .....................19
6.24 Chip Revision Register (2CH).........................19
6.25 Special Mode Control Register (2FH).............19
6.26 Memory Data Read Command without Address
Increment Register (F0H) ................................19
6.27 Memory Data Read Command with Address
Increment Register (F2H) ................................19
6.28 Memory Data Read_ address Register
(F4H~F5H) ......................................................19
6.29 Memory Data Write Command without Address
Increment Register (F6H) ................................19
6.30 Memory Data Write Command with Address
Increment Register (F8H) ................................19
6.31 Memory Data Write_ address Register
(FAH~FBH) ......................................................20
6.32 TX Packet Length Register (FCH~FDH) ........20
6.33 Interrupt Status Register (FEH) ......................20
6.34 Interrupt Mask Register (FFH) ........................20
7. EEPROM Format ................................................21
8. MII Register Description......................................22
8.1 Basic Mode Control Register (BMCR) – 00 ......23
8.2 Basic Mode Status Register (BMSR) – 01........24
8.3 PHY ID Identifier Register #1 (PHYID1) – 02 ...25
8.4 PHY Identifier Register #2 (PHYID2) – 03........25
8.5 Auto-negotiation Advertisement Register
(ANAR) – 04 ....................................................26
8.6 Auto-negotiation Link Partner Ability Register
(ANLPAR) – 05 ................................................27
8.7 Auto-negotiation Expansion Register (ANER) –
06 .....................................................................27
8.8 DAVICOM Specified Configuration Register
(DSCR) – 16 .....................................................28
8.9 DAVICOM Specified Configuration and Status
Register (DSCSR) – 17 ...................................29
8.10 10BASE-T Configuration/Status (10BTCSR) –
18.....................................................................30

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 3
Version: DM9000-DS-F02
June 26, 2002
9. Functional Description ........................................31
9.1 Host Interface....................................................31
9.2 Direct Memory Access Control .........................31
9.3 Packet Transmission.........................................31
9.4 Packet Reception..............................................31
9.5 100Base-TX Operation .....................................32
9.5.1 4B5B Encoder................................................32
9.5.2 Scrambler.......................................................32
9.5.3 Parallel to Serial Converter............................32
9.5.4 NRZ to NRZI Encoder....................................32
9.5.5 MLT-3 Converter............................................32
9.5.6 MLT-3 Driver ..................................................32
9.5.7 4B5B Code Group..........................................33
9.6 100Base-TX Receiver.......................................34
9.6.1 Signal Detect..................................................34
9.6.2 Adaptive Equalization ....................................34
9.6.3 MLT-3 to NRZI Decoder.................................34
9.6.4 Clock Recovery Module .................................34
9.6.5 NRZI to NRZ ..................................................34
9.6.6 Serial to Parallel.............................................34
9.6.7 Descrambler...................................................34
9.6.8 Code Group Alignment ..................................35
9.6.9 4B5B Decoder................................................35
9.7 10Base-T Operation..........................................35
9.8 Collision Detection ............................................35
9.9 Carrier Sense....................................................35
9.10 Auto-Negotiation .............................................35
9.11 Power Reduced Mode ....................................36
9.11.1 Power Down Mode.......................................36
9.11.2 Reduced Transmit Power Mode ..................36
10. DC and AC Electrical Characteristics ...............37
10.1 Absolute Maximum Rating (25∘C) ................37
10.2 Operating Conditions ......................................37
10.3 DC Electrical Characteristics ..........................38
10.4 AC Electrical Characteristics & Timing
Waveforms.......................................................39
10.4.1 TP Interface .................................................39
10.4.2 Oscillator/ Crystal Timing.............................39
10.4.3 Processor Register Read Timing.................39
10.4.4 Processor Register Write Timing .................40
10.4.5 External MII Interface Transmit Timing........41
10.4.6 External MII Interface Receive Timing.........41
10.4.7 MII Management Interface Timing ...............42
10.4.8 EEPROM Interface Timing ..........................42
11. Application Notes ..............................................43
11.1 Network Interface Signal Routing ...................43
11.2 10Base-T/100Base-TX Application Figure 11-1
.........................................................................43
11.3 10Base-T/100Base-TX (Power Reduction
Application) Figure 11-2................................44
11.4 Power Decoupling Capacitors Figure 11-3 .....45
11.5 Ground Plane Layout Figure 11-4 ..................46
11.6 Power Plane Partitioning Figure 11-5 .............47
11.7 Magnetics Selection Guide .............................48
11.8 Crystal Selection Guide Figure 11-6...............48
11.9 Application of reverse MII Figure 11-7............49
12. Package Information .........................................50
12.1 LQFP 100L Outline Dimensions .....................50
13. Appendix ...........................................................51
14. Order Information..............................................53

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
4Final
Version: DM9000-DS-F02
June 26, 2002
3. Features
■Supports processor interface: byte/word/dword of
I/O command to internal memory data operation
■Integrated 10/100M transceiver
■Supports MII and reverses MII interface
■Supports back pressure mode for half-duplex
mode flow control
■IEEE802.3x flow control for full-duplex mode
■Supports wakeup frame, link status change and
magic packet events for remote wake up
■Integrated 4K dword SRAM
■Supports automatically load vendor ID and
product ID from EEPROM
■Supports 4 GPIO pins
■Optional EEPROM configuration
■Very low power consumption mode:
–Power reduced mode (cable detection)
–Power down mode
–Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
■Compatible with 3.3V and 5.0V tolerant I/O
■100-pin LQFP with CMOS process

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 5
Version: DM9000-DS-F02
June 26, 2002
4. Pin Configuration
4.1 Pin Configuration I: with MII Interface
11
DM9000
75
74
73
72 71
70
69
68
67
66
65
64
63 62 61
60
59 58
57
56 55
54 53 52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
76
TXD1
1 2
3 4
5 6 7 8 9
10 12 13 14 15 16
17 18
19
20
21
22
23
24 25
BGRES
DGND
NC
LINK_O
WAKEUP
PW_RST#
DGND
SD12
IOR#
77
78
79
80
81
82
83
84
85
SD15
SD14
SD13
SD8
SD11
SD10
SD9
SA4
DVDD
IO16
CMD
SA8
SA5
SA6
SA7
SA9
DGND
INT
IOW#
AEN
IOWAIT
DVDD
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
RST
DGND
TEST1 TEST2 TEST3 TEST4
DVDD
X2_25M X1_25M
DGND
SD
AGND
AVDD
AVDD
RXI+
RXI-
AGND
AGND
TXO+
TXO-
AVDD
DVDD
LINK_I
RXD0
RXD1
RXD2
RXD3
DGND
CRS
COL
RX_DV
RX_ER
RX_CLK
TEST5
TX_CLK
TXD0
TXD2 TXD3 TX_EN DVDD MDIO MDC DGND CLK20MO SPEED# DUP# LINKACT# DGND EEDI EEDO EECK EECS GPIO0 GPIO1 GPIO2 GPIO3 DVDD DVDD NC NC

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6Final
Version: DM9000-DS-F02
June 26, 2002
4.2 Pin Configuration II: with 32-Bit Data Bus
11
DM9000
75
74
73
72 71
70
69
68
67
66
65
64
63 62 61
60
59 58
57
56 55
54 53 52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
76
SD19
1 2
3
4
5 6 7 8 9
10 12 13 14 15 16
17 18
19
20
21
22
23
24 25
BGRES
DGND
NC
LINK_O
WAKEUP
PW_RST#
DGND
SD12
IOR#
77
78
79
80
81
82
83
84
85
SD15
SD14
SD13
SD8
SD11
SD10
SD9
SA4
DVDD
IO16
CMD
SA8
SA5
SA6
SA7
SA9
DGND
INT
IOW#
AEN
IOWAIT
DVDD
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
RST
DGND
TEST1 TEST2 TEST3 TEST4
DVDD
X2_25M X1_25M
DGND
SD
AGND
AVDD
AVDD
RXI+
RXI-
AGND
AGND
TXO+
TXO-
AVDD
DVDD
SD31
SD30
SD29
SD28
SD27
DGND
SD26
SD25
SD24
SD23
SD22
TEST5
SD21
SD20
SD18 SD17 NC DVDD SD16 IO32 DGND CLK20MO SPEED# DUP# LINKACT# DGND EEDI EEDO EECK EECS GPIO0 GPIO1 GPIO2 GPIO3 DVDD DVDD NC NC
-

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 7
Version: DM9000-DS-F02
June 26, 2002
5. Pin Description
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,
LI= reset Latch Input, #= asserted low
5.1 MII Interface
Pin No. Pin Name I/O Description
37 LINK_I I External MII device link status
41,40,39,
38
RXD [3:0] I External MII Receive Data
4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode
43 CRS I/O External MII Carrier Sense
Active high to indicate the pressure of carrier, due to receive or transmit activities
in 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface.
44 COL I/O External MII Collision Detect. This pin is output in reverse MII interface.
45 RX_DV I External MII Receive Data Valid
46 RX_ER I External MII Receive Error
47 RX_CLK I External MII Receive Clock
49 TX_CLK I/O External MII Transmit Clock. This pin is output in reverse MII interface.
53,52,51,
50
TXD [3:0] O External MII Transmit Data
4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps
nibble mode
TXD [2:0] is also used as the strap pins of IO base address.
IO base = (strap pin value of TXD [2:0]) * 10H + 300H
54 TX_ EN O External MII Transmit Enable
56 MDIO I/O MII Serial Management Data
57 MDC O MII Serial Management Data Clock
This pin is also used as the strap pin of the polarity of the INT pin
When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin
is high active
Note: The pins of MII interface are all have a pulled down resistor about 60k ohm internally
5.2 Processor Interface
1 IOR# I Processor Read Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
2 IOW# I Processor Write Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
3 AEN I Address Enable
A low active signal used to select the DM9000.
4 IOWAIT O Processor Command Ready
When a command is issued before last command is completed, the IOWAIT will
be pulled low to indicate the current command is waited

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
8Final
Version: DM9000-DS-F02
June 26, 2002
14 RST I Hardware Reset Command, active high to reset the DM9000
6,7,8,9,10,
11,12,13,
89,88,87,
86,85,84,
83,82
SD0~15 I/O Processor Data Bus bit 0~15
93,94,95,
96,97,98
SA4~9 I Address Bus 4~9
These pins are used to select the DM9000.
When SA9 and SA8 are in high states, and SA7 and AEN are in low
states, and SA6~4 are matched with strap pins TXD2~0, the DM9000 is
selected.
92 CMD I Command Type
When high, the access of this command cycle is DATA port
When low, the access of this command cycle is ADDRESS port
91 IO16 O Word Command Indication
When the access of internal memory is word or dword width, this pin will
be asserted
This pin is low active at default
100 INT O Interrupt Request
This pin is high active at default, its polarity can be modified by EEPROM
setting or strap pin MDC. See the EEPROM content description for detail
56,53,52,
51,50,49,
47,46,45,
44,43,41,
40,39,38
37
SD16~31 (in
double word
mode)
I/O Processor Data Bus bit 16~31
These pins are used as data bus bits 16~31 when the DM9000 is set to
double word mode (the straps pin EEDO is pulled high and WAKEUP is
not pull-high)
57 IO32 (in double
word mode)
O Double Word Command Indication
This pins is used as the double word command indication when the
DM9000 is set to double data word mode, and this pin will be asserted
when the access of internal memory is double word width
This pin is low active at default
Note: The pins of processor interface except SD8,SD9 and IO16 are all have a pulled down resistor about 60k ohm
internally
5.3 EEPROM Interface
64 EEDI I Data from EEPROM
65 EEDO I/O Data to EEPROM
This pin is also used as a strap pin. It combines with strap pin WAKEUP,
and it can set the data width of the internal memory access
The decoder table is the following, where the logic 1 means the strap pin
is pulled high
WAKEUP EEDO data width
0 0 16-bit
0 1 32-bit
1 0 8-bit
1 1 reserved

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 9
Version: DM9000-DS-F02
June 26, 2002
66 EECK O Clock to EEPROM
67 EECS I/O Chip Select to EEPROM
This pin is also used as a strap pin to define the LED modes.
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS,EECK and EEDO are all have a pulled down resistor about 60k ohm internally
5.4 Clock Interface
21 X2_25M O Crystal 25MHz Out
22 X1_25M I Crystal 25MHz In
59 CLK20MO O 20Mhz Clock Output
It is used as the clock signal for the external MII device’s clock is 20MHz
This pin has a pulled down resistor about 60k ohm internally.
5.5 LED Interface
60 SPEED100# O Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY
61 DUP# O Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the internal
PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
62 LINK&ACT# O Link LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
5.6 10/100 PHY/Fiber
24 SD I Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
25 BGGND P Bandgap Ground
26 BGRES I/O Bandgap Pin
27 AVDD P Bandgap and Guard Ring Power
28 AVDD P RX Power
29 RXI+ I TP RX Input
30 RXI- I TP RX Input
31 AGND P RX Ground
32 AGND P TX Ground
33 TXO+ O TP TX Output

DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
10 Final
Version: DM9000-DS-F02
June 26, 2002
34 TXO- O TP TX Output
35 AVDD P TX Power
5.7 Miscellaneous
16,17,18,
19
TEST1~TEST4 I Operation Mode
Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application
48 TEST5 I It must be ground.
68,69,70,
71
GPIO0~3 I/O General I/O Ports
Registers GPCR and GPR can program these pins
The GPIO0 is an output mode, and output data high at default is to power
down internal PHY and other external MII device
GPIO1~3 defaults are input ports
78 LINK_O O Cable Link Status Output. Active High
This pin is also used as a strap pin to define whether the MII interface is a
reversed MII interface (pulled high) or a normal MII interface (not pulled
high). This pin has a pulled down resistor about 60k ohm internally.
79 WAKEUP O Issue a wake up signal when wake up event happens
This pin has a pulled down resistor about 60k ohm internally.
80 PW_RST# I Power on Reset
Active low signal to initiate the DM9000
The DM9000 is ready after 5us when this pin deasserted
74,75,77 NC Not Connect
5.8 Power Pins
5,20,36,
55,72,90,
73
DVDD P Digital VDD
15,23,42,
58,63,81,
99,76
DGND P Digital GND