Denon AVR-3801 User manual

Hi-Fi Component
SERVICE MANUAL
MODEL AVR-3801
AV SURROUND RECEIVER


Some illustrations using in this service manual are slightly different from the actual set.

2
AVR-3801
SPECIFICATIONS
!!
!!
!AUDIO SECTION
""
""
"Power Amplifier
Rated output: Front: 105W + 105W (8Ω/ohms, 20Hz ~ 20kHz with 0.05% T.H.D.)
150W + 150W (6Ω/ohms, 1kHz with 0.7% T.H.D.)
180W + 180W (6Ω/ohms, EIAJ)
Center: 105W (8Ω/ohms, 20Hz ~ 20kHz with 0.05% T.H.D.)
150W (6Ω/ohms, 1kHz with 0.7% T.H.D.)
180W + 180W (6Ω/ohms, EIAJ)
Surround: 105W + 105W (8Ω/ohms, 20Hz ~ 20kHz with 0.05% T.H.D.)
150W + 150W (6Ω/ohms, 1kHz with 0.7% T.H.D.)
180W + 180W (6Ω/ohms, EIAJ)
Surround Back: 105W + 105W (8Ω/ohms, 20 Hz ~ 20kHz with 0.05% T.H.D.)
150W + 150W (6Ω/ohms, 1kHz with 0.7% T.H.D.)
180W + 180W (6Ω/ohms, EIAJ)
Dynamic power: 140W ×2ch (8Ω/ohms)
210W ×2ch (4Ω/ohms)
240W ×2ch (2Ω/ohms)
Output terminals: Front, Center, Surr. Back/Multi Zone: 6 ~ 16Ω/ohms
Surround: A or B 6 ~ 16Ω/ohms
A + B 8 ~ 16Ω/ohms
""
""
"Analog
Input sensitivity/input impedance: 200mV/47kΩ/kohms
Frequency response: 10Hz ~ 100kHz: +0, −3dB (DIRECT model)
S/N: 102dB (DIRECT mode)
Distortion: 0.005% (20Hz ~ 20kHz) (DIRECT mode)
Rated output: 1.2V
""
""
"Digital
D/A output: Rated output 2V (at 0dB playback)
Total harmonic distortion 0.008% (1 kHz, at 0 dB)
S/N ratio 102dB
Dynamic range 96dB
Digital input: Format Digital audio interface
""
""
"Phono equalizer (PHONO input 

REC OUT)
Input sensitivity: 2.5mV
RIAA deviation: ±1dB (20Hz to 20kHz)
Signal-to-noise ratio: 74dB (A weighting, with 5mV input)
Rated output/Maximum output: 150mV/8V
Distortion factor: 0.03% (1kHz, 3V)
!!
!!
!VIDEO SECTION
""
""
"Standard video jacks
Input/output level and impedance: 1Vp-p, 75Ω/ohms
Frequency response: 5Hz ~ 10MHz +0, −3dB
""
""
"S-video jacks
Input/output level and impedance: Y (brightness) signal 1Vp-p, 75Ω/ohms
C (color) signal 0.286Vp-p, 75Ω/ohms
Frequency response: 5Hz ~ 10MHz +0, −3dB
""
""
"Color component video jacks
Input/output level and impedance: Y (brightness) signal 1Vp-p, 75Ω/ohms
CB(blue) signal 0.7Vp-p, 75Ω/ohms
CR(red) signal 0.7Vp-p, 75Ω/ohms
Frequency response: 5Hz ~27MHz +0, −3dB
!!
!!
!TUNER SECTION [FM] (note: µV at 75Ω/ohms, 0dBf=1 ×10-15 W) [AM]
Receiving Range: 87.50MHz ~ 107.90MHz 520kHz ~ 1710kHz
(for North America and multiple voltage models) (for North America and Multiple voltage models)
87.50MHz ~ 108.00MHz 522kHz ~ 1611kHz
(for Europe, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models) (for Europe, China, Hong Kong, Taiwan R.O.C. and multiple voltage models)
Usable Sensitivity: 1.0µV (11.2dBf) 18µV
50dB Quieting Sensitivity: MONO: 1.6µV (15.3dBf)
STEREO: 23µV (38.5dBf)
S/N (IHF-A): MONO: 80dB
STEREO: 75dB
Total Harmonic Distortion (at 1kHz): MONO: 0.15%
STEREO: 0.3%
!!
!!
!GENERAL
Power supply: AC120V, 60Hz (for North America and Taiwan R.O.C. models)
AC230V, 50Hz (for Europe model)
AC220V, 50Hz (for China model)
AC115V/230V, 50/60Hz (for Hong Kong and Multiple voltage models)
Power consumption: 7.0A (for North America model)
400W (for Europe, China, Hong Kong and Multiple voltage models)
360W (for Taiwan R.O.C. model)
2.0W Max (Standby)
Maximum external dimensions: 434 (W) ×171 (H) ×416 (D)mm (17-3/32″×6-11/32″×16-3/8″)
Weight: 17.0kg (37 lbs 8 oz)
!!
!!
!REMOTE CONTROL UNIT (RC-883: for North America, China, Hong Kong,Taiwan R.O.C. and Multiple voltage models)
(RC-884: for Europe model)
Batteries: R6P/AA Type (three batteries)
External dimensions: 61 (W) ×230 (H) ×34 (D)mm (2-13/32″×9-1/16″×1-11/32″)
Weight: 200g (Approx. 7 oz) (including batteries)
* For purposes of improvement, specifications and design are subject to change without notice.
SAFETY PRECAUTIONS
The following check should be performed for the continued protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the
power cord is less than 460 kohms, the unit is defective.
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3
AVR-3801
WIRE ARRANGEMENT
If wire bundles are untied or moved to perform adjustment or parts replacement etc.,be sure to rearrange them neatly as they
were originally bundled or placed afterward.
Otherwise, incorrect arrangement can be a cause of noise generation.
Wire arrangement viewed from the top

4
AVR-3801
DISASSEMBLY
(Follow the procedure below in reverse order when reassembling)
1. Top Cover
Remove 3 screws
1
on the rear and 6 screws
2
on both
sides to detach the Top Cover as shown in the arrow
direction.
2. Front Panel
(1) Remove 7 screws 3from the top and bottom edges of
the Front Panel.
(2) Release 4 top and bottom hooks, then detach the Front
Panel as shown in the arrow direction.
Top Cover
3. Inner Panel
Pull out the Inner Panel in the arrow direction after removing
3 screws 4.
Inner Panel
Hook
2
2
1
3
3
3
Hook
Hook
Hook
Front Panel
4
4
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5
AVR-3801
4. Inner Panel Ass'y
(1) Remove 3 round and 1 square knobs, and unscrew 4
nuts.
(2) Remove 15 screws
5
fixing each P.W.B.
Round Knob
5
5
5
Nut
Square Knob
Round Knob Nut
5. Power Transformer
(1) Remove 4 screws fixing the Power Transformer and 4
connectors.
(2) Be careful when removing the Power Transformer as it
is heavy.
Before proceeding to the next stop, take off the Power
Transformer.
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6
AVR-3801
7. Regulator Unit
Take off the Regulator Unit
11
as shown in the arrow
direction after removing 8 screws
12
.
11
12
6. Component Video Unit / PRE-OUT Unit /
AMP Connect Unit
(1) Remove 9 screws
6
to detach Component Video Unit
7and Pre-out Unit 8.
(2) Take off the Amp Connect Unit 9as shown in the
arrow direction after removing 1 screw
10
.
8
6
7
9
10
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7
AVR-3801
8. S-Video / C-video / Audio-in & DSP /
Ext-in & VR / Digital-in / Tuner Unit
(1) Remove 37 screws 13 to detach the Rear Panel.
(2) Take off the objective P.W.B. upward.
9. How to Check Power Amp / µµ
µµ
µ-com Unit
with Power-on
(1) Remove 12 screws
14
, 1 screw
15
, and 4 screws
16
fixing to the Chassis.
(2) Pull up the Unit to separate from the Chassis.
Rear Panel 13
13
13
13
14
15
16
14 14
14
16
14
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12 3 45678
A
B
C
D
E
8
LEVEL DIAGRAMS
AVR-3801

8
76
5
4
3
2
1
A
B
C
D
E
AVR-3801
9

CLOCK FLOW & WAVE FORM IN DIGITAL BLOCK
Wave Form
CH1: D-DATA
(IC510 (5) )
1
CH1: DATA
CH2: fs
CH3: 64fs
CH4: 256fs
3
CH1: DATA
CH2: fs
CH3: 64fs
2
10
AVR-3801

FM/MPX ALIGNMENT
Input Output Adjust
Step
Alignment
Item
Tuning
Frequency
Setting Type
Frequency
Input Level
Modulation
Coupling Type
Connect to
Points Adjust to Remarks
1
Tuning Center
98.1 MHz FM SSG 98.1 MHz 60 dBµNone Antenna
Terminal
Digital
Voltmeter
TP102
(JV36-JV67)
T502 ±50mV
Function : FM
Mode : Auto
2
Separation
98.1 MHz FM SSG 98.1MHz 60 dBµ
Stereo (L)
1KHz 100%
Antenna
Terminal
AC
Voltmeter
AUDIO
OUT
Terminal (R)
VR502 Maximum
Separation

3
Signal Level
98.1MHz FM SSG 98.1MHz 20 dBµOff Antenna
Terminal   VR501
Light
“TUNED”
FLD
Character

AM ALIGNMENT
Output Adjustment
Step
Alignment
Item Frequency Input Type
Connect to
Points Adjust to Remarks
1
IF IF SWEEP
(Input level is not over to work A.G.C.)
Oscilloscope
IC502 12Pin
T503
Maximum height and best
symmetry curve
ADJUSTMENTADJUSTMENT
Tuner SectionTuner Section
CONNECTION DIAGRAM OF MEASURING INSTRUMENTSCONNECTION DIAGRAM OF MEASURING INSTRUMENTS
'' FMFM
'' AMAM
STEREO
MODULATOR
FMSSG
DIGITAL
VOLTMETER
TP102
T502 VR501
VR502
IC502
75Ω
1
1U-3318-5 TUNER UNIT
T503
IC502
1
12 Pin
GND
AM
AM IFOUT
OSCILLOSCOPE
1U-3318-5 TUNER UNIT
1111
AVR-3801AVR-3801

1212
AVR-3801AVR-3801
Audio SectionAudio Section
Idling Current (1U-3315-1)Idling Current (1U-3315-1)
Required measurement equipment : DC VoltmeterRequired measurement equipment : DC Voltmeter
PreparationPreparation
(1)(1) Avoid direct blow from an air conditioner or an electric fan, and adjust the unit at normal room tempereture 15 °C ~ 30 °CAvoid direct blow from an air conditioner or an electric fan, and adjust the unit at normal room tempereture 15 °C ~ 30 °C
(59 °F ~ 86 °F).(59 °F ~ 86 °F).
(2)(2) PresettingPresetting
&& POWER (Power sourse switch)POWER (Power sourse switch) →→ OFFOFF
&& SPEAKER (Speaker terminal)SPEAKER (Speaker terminal) →→ No load (Do not connect speaker, dummy resistor, etc.)No load (Do not connect speaker, dummy resistor, etc.)
AdjustmentAdjustment
(1)(1) Remove top cover and set VR101, VR102, VR201, VR202, VR301, VR302, VR401, on 1U-3315-1 (Power Unit) atRemove top cover and set VR101, VR102, VR201, VR202, VR301, VR302, VR401, on 1U-3315-1 (Power Unit) at fullyfully
counterclockwise (counterclockwise ( ))..
(2)(2) Connect DC Voltmeter to test points (FRONT-Lch: TP101, FRONT-Rch: TP102, CENTER ch: TP401, SURROUND-Lch:Connect DC Voltmeter to test points (FRONT-Lch: TP101, FRONT-Rch: TP102, CENTER ch: TP401, SURROUND-Lch:
TP201, SURROUND-Rch: TP202, SURROUND BACK-Lch: TP301, SURROUND BACK-Rch: TP302).TP201, SURROUND-Rch: TP202, SURROUND BACK-Lch: TP301, SURROUND BACK-Rch: TP302).
(3)(3) Connect power cord to AC Line, and turn power switch "ON".Connect power cord to AC Line, and turn power switch "ON".
(4)(4) Presetting.Presetting. MASTER VOLUMEMASTER VOLUME :: "---" counterclockwise ("---" counterclockwise ( min.)min.)
MODEMODE :: 7CH STEREO7CH STEREO
FUNCTIONFUNCTION :: CDCD
(5)(5) Allow 2 minutes, and turn VR101 clockwise (Allow 2 minutes, and turn VR101 clockwise ( ) to adjust the TEST POINT voltage to 6.5 mV) to adjust the TEST POINT voltage to 6.5 mV ±±0.5 mV DC.0.5 mV DC.
(6)(6) After 10 minutes from preset, turn VR101 to set the voltage to 8 mVAfter 10 minutes from preset, turn VR101 to set the voltage to 8 mV ±±0.5 mV DC.0.5 mV DC.
(7)(7) Adjust the Variable Resistors of other channels in the same way.Adjust the Variable Resistors of other channels in the same way.
(8)(8) After 5 minutes from (6), turn VR101 to set the voltage to 8 mVAfter 5 minutes from (6), turn VR101 to set the voltage to 8 mV ±±0.5 mV DC.0.5 mV DC.
(9)(9) Adjust the Variable Resistors of other channels in the same way.Adjust the Variable Resistors of other channels in the same way.
VR302
DC Voltmeter
TP302
VR401
TP401
VR102
TP102
VR101
TP101
VR202
TP202
VR201
TP201
TP301
VR301
SBR ch
C ch
FR ch
FL ch
SR ch
SL ch
SBL ch

Name Function
TMP88CU74F Terminal Function
Pin
No.
1 P02/S01 RDS RESET O C Z L RDS reset output (LC7074)
2 P03 OSD RST O C Z H OSD control output (M35015)
3 P04 ST/MONO O C Z L STEREO/MONO control signal, L: STEREO
4 P05 PLFL DATA O C  Z L PLL, FL control terminal (LC72131 & LC75721NE)
5 P06 PLL STB O C Z L PLL control terminal (LC72131)
6 P07 PLFL CLK O C Z L PLL, FL control terminal (LC72131 & LC75721NE)
7 Vss Vss I GND  L GND
8 Xout Xout O XTAL
9 Xin Xin I XTAL
10 RESET_ RESET_ I Eu Lv L Reset input
11 P22/XTOUT TUNED_ I Eu Lv Z Tuning detect, L: Tuned
12 P21/XTIN STEREO_ I Eu Lv Z L: At stereo receive
13 TEST TEST I GND S Connect to GND
14 P20/INT5_ B.DOWN_ I Eu Lv Z Power down detect, L: Power down
15 P10/INT0_ PROTECT_ I Ed E&L Z PROTECTION detect input, H: Detect
16 P11/INT1 RDS START I  Z L RDS data input (LC7074)
17 P12 OSD CLK O C  Z H OSD control output (M35015)
18 P13 OSD CS O C Z H OSD control output (M35015)
19 P14 OSD DATA O C  Z L OSD control output (M35015)
20 P15/INT3 REMOCON I Ed E&L Z Remote control signal input
21 P16/INT2 ACK O C  Z L MAIN-SUB CPU comm. control terminal
22 P17/INT4 REQ I Eu Z L MAIN-SUB CPU comm. control terminal
23 P30/SCL SI I MAIN-SUB CPU comm. control terminal
24 P31/SDA SO O C MAIN-SUB CPU comm. control terminal
25 P32/SCK0_ CLK O C MAIN-SUB CPU comm. control terminal
26 P40/AIN0 MODE I Eu Lv Z Destination switching input
27 P41/AIN1 KEY1 I Eu Lv Z Button input 1
28 P42/AIN2 KEY2 I Eu Lv Z Button input 2
29 P43/AIN3 KEY3 I Eu Lv Z Button input 3
30 P44/AIN4 FUNC STB1 O C ZL Function control output, REC OUT (TC9274-011), EXT/SOURCE (TC9274-012)
31 P45/AIN5 FUNC/T. CON CLK O C ZL Function control output (TC9274N, TC9273), TONE control output (TC9184P)
32 P46/AIN6 FUNC/T. CON DATA O C  ZL Function control output (TC9274N, TC9273), TONE control output (TC9184P)
33 P47/AIN7 E.VOL STB2 O C  Z L Multi Elect. volume control output (TC9459)
34 P50/AIN8 E.VOL STB1 O C  L L Elect. volume control output (TC9459)
35 P51/AIN9 TONE STB O C  L L TONE control output (TC9184P)
36 P52/AIN10 E.VOL DATA O C  L H Elect. volume control output (TC9459)
37 P53/AIN11 E.VOL CLK O C  L H Elect. volume control output (TC9459)
Symbol I/O Type Op Det Res Init
SEMICONDUCTORS
!!
!!
!IC’s
Note: Abbreviation ahead of IC No. indicates the name of P.W.B.
PO: Power P.W.B. RE: Regulator P.W.B.
EX: Exit in P.W.B. AU: Audio/DSP P.W.B.
CO: Control P.W.B. AC: Amp Connect P.W.B
TMP88CU74F
(CO: IC303)
Function
38 VASS VASS I Ref. volt (GND)
39 VAREF VAREF I Ref. volt (VDD)
40 VDD VDD I Power supply
41 P60 FL CE O P Ed S L H FL display control output (LC75721NE)
42 P61 FL RES O P Ed S L H FL display control output (LC75721NE)
43 P62 FUNC STB2 O P Ed Z L Function control output (TC9273), INPUT (TC9273)
44 P63 SA-RELAY O P Id L L Surround SP relay A control terminal, L: Mute
45 P64 SB-RELAY O P Id L L Surround SP relay B control terminal, L: Mute
46 P65 C-RELAY O P Id L L Center SP relay control terminal, L: Mute
47 P66 F-RELAY O P Id L H Front SP relay control terminal, L: Mute
48 P67 PRE F MUTE O P Ed L H Front PRE OUT mute control terminal, L: Mute
49 P70 PRE C MUTE O P Ed L L Center PRE OUT mute control terminal, L: Mute
50 P71 PRE S MUTE O P Ed L L Surround PRE OUT mute control terminal, L: Mute
51 P72 SUB WOOFER MUTE OPEdL H Sub-woofer PRE OUT mute control terminal, L: Mute
52 P73 H/P RELAY O P Id L H H/P OUT relay control terminal, L: Mute
53 P74 EXP OE O P Ed L H Port expander control terminal (BU4094)
54 P75 EXP CLK O P Ed L L Port expander control terminal (BU4094)
55 P76 EXP DATA O P Ed L L Port expander control terminal (BU4094)
56 P77 EXP STB O P Ed L L Port expander control terminal (BU4094)
57 P80 POWER O P Id L H Power relay control output, H: ON
58 P81 RESET2 O P Id L L Reset signal output to sub-CPU, H: Reset
59 P82 PRE S.BACK MUTE O P Id L L Surround Back PRE PUT mute control terminal, L: Mute
60 P83 S.BACK VOL MUTE O P Id L L Surround Back volume mute, L: Mute
61 P84 STANDBY O P Id L H Standby LED drive output H: Light
62 P85 S.BACK RELAY O P Id L L Surround Back SP relay control terminal, L: Mute
63 P86 LED CK O P Id L L LED control terminal (BU2090F)
64 P87 LED DATA O P Id L L LED control terminal (BU2090F)
65 P90 TUNER MUTE O P Ed L H TUNER mute control terminal, H: Mute
66 P91 MULTI MUTE O P Id L H MULTI PREOUT mute control terminal, H: Mute
67 P92 S MONI DET I Eu Lv Z S monitor connection detect input, L: Connected
68 P93 S SIG DET I Eu Lv Z S signal detect input, H: Detected
69 P94 SYNC DET. I Eu Lv Z Sync detect input, H: Ext. sync
70 P95 SEL A (M) I Eu Lv Z Master volume rotation detect input (rotary encoder)
71 P96 SEL B (M) I Eu Lv Z Master volume rotation detect input (rotary encoder)
72 P97 CINEMA EQ O P Eu Lv Z L CINEMA EQ control output, H: ON
73 PD0 VOL MUTE O P Ed L L Master volume minimum control, L: Min.
74 PD1 SEL C (S) I Eu Lv Z Surround mode rotation detect input (rotary encoder)
75 PD2 SEL D (S) I Eu Lv Z Surround mode rotation detect input (rotary encoder)
76 PD3 SEL E (F) I Eu Lv Z  Input selector switch rotation detect input (rotary encoder)
77 PD4 SEL F (F) I Eu Lv Z  Input selector switch rotation detect input (rotary encoder)
78 Vkk Vkk GND fixed
79 P00/SCK1_ RDS CLK I SZRDS clock input (LC7074)
80 P01/SI1 RDS DATA I SZRDS data input (LC7074)
I/O Type Op Det Res Init
Name
Pin
No. Symbol
NOTE:
Pin No. : Terminal number of microcomputer.
Port Name : The name entered in the data sheet of microcomputer.
Symbol : Symbolized interface function.
I/O : Input or out of part.
“I” = Input port
“O” = Output port
Type : Composition of port in case of output port.
“C” = CMOS output
“N” = NMOS open drain output
“P” = PMOS open drain output
Op : Pull up/Pull down selection information.
“Iu” = Inner microcomputer pull up
“Id” = Inner microcomputer pull down
“Eu”= External microcomputer pull up
“Ed”= External microcomputer pull down
Det : Indicates judging state of input port. Level detection is “LV”; Edge detection is “Ed”; Detection by both shifting is “E&L”;
Serial data detection is “S” (Serial data output is also “S”).
Res : State at reset.
“H” = Outputs High Level at reset
“L” = Outputs Low Level at reset
“Z” = Becomes High impedance mode at reset
Ini : Initial output state.
Function : Function and logical level explanation of signals to be interface.
124
25
40
41
64
65
80
13
AVR-3801
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TMP93CS41F (AU: IC301)
Name Function
TMP93CS41F Terminal Function
Pin
No.
1 V REFL A/D ref. GND
2 A Vss ← A/D GND
3 A Vcc ← AD +5V
4 _NMI I Not used (fixed to H)
5 P70/TI0 _DEMOD RESET O C Ed L L Demodulator reset output (L: Reset)
6 P71/TO1 DEMOD ON O C Ed L L Demodulator osc. control output (H: Osc.)
7 P72/TO2 FAN1 O C Ed L L FAN control output (H: ON, L: OFF)
8 P73/TO3 FAN2 O C Ed L L FAN control output (H: Hi, L: Low & off)
9 P80/INT4/TI4 B.DOWN_ I Eu E↓&L Z Power down detect (L: Detected)
10 P81/INT5/TI5 DSP ACK I E↑&L Host I/F comm. response input (L: OK)
11 P82/TO4 AC-3 RF DET I E↓&L AC-3 RF signal judge input (L: AC-3 data input)
12 P83/TO5 _REQ O C Eu HL
MAIN-SUB CPU comm. control output (L: Comm. request from
sub)
13 P84/INT6/TI6 _ACK I Eu E↓&L MAIN-SUB CPU comm. control input (L: Ack. return from main)
14 P85/INT7/TI7 ERR I E↑&L DIR control input terminal (LC89055Q)( H: ERR)
15 P86/TO6 _DSP RESET O C Ed L L DSP reset output terminal (L: Reset)
16 P97/INT0 _CS I Ed E↑&L 
DIR control input terminal (LC89055Q), when CH status change
L→H
17 P90/TXD0 SI O C MAIN-SUB CPU comm. control terminal (data output)
18 P91/RXD0 SO I MAIN-SUB CPU comm. control terminal (data input)
19 P92/_CTS0/SCLK0 CLK I/O C MAIN-SUB CPU comm. control terminal (I2C clock in/output)
20 P93/TXD1 O C  ZL
21 P94/RXD1 DIR MISO I Lv DIR control input terminal (LC89055Q) control data input
22 P95/SCLK1 DIR CLK O C  Z L DIR control terminal (LC89055Q) control clock output
23 AM8/_16 ← Fixed to +5V
24 CLK O C Eu 
25 Vcc ← +5V
26 Vss I/O1 GND
27 X1 Xin I X′tal connection
28 X2 Xout O X′tal connection
29 _EA ← Fixed to +5V
30 _RESET RESET2_ I Eu Lv L Reset input (controlled by main CPU)
31 P96/XT1 A/D RESET O N Eu H H A/D control terminal (L: Reset)
32 P97/XT2 ASIC-RESET O N Eu H H ASIC control terminal (L: Reset)
33 TEST1 ←IConnected to TEST2
34 TEST2 ←IConnected to TEST1
35 PA0 DINA O C Ed L L Digital input switching control output
36 PA1 DINB O C Ed L L Digital input switching control output
37 PA2 DINC O C Ed L L Digital input switching control output
38 PA3 DIND O C Ed L L Digital input switching control output
39 PA4 DOUTA O C Ed L L Digital output switching control output
40 PA5 DOUTB O C Ed L L Digital output switching control output
Symbol I/O Type Op Det Res Init
Name Function
Pin
No.
41 PA6 O C Ed LL
42 PA7/SCOUT 96k-DAC O C Ed L L DAC control terminal (H: Sample frequency 96kHz)
43 ALE ←OC L L Address latch enable
44 Vcc +5V
45 P00/AD0 AD0 I/O C  Z L EPROM data in D0 / address out A0
46 P01/AD1 AD1 I/O C  Z L EPROM data in D1 / address out A1
47 P02/AD2 AD2 I/O C  Z L EPROM data in D2 / address out A2
48 P03/AD3 AD3 I/O C  Z L EPROM data in D3 / address out A3
49 P04/AD4 AD4 I/O C  Z L EPROM data in D4 / address out A4
50 P05/AD5 AD5 I/O C  Z L EPROM data in D5 / address out A5
51 P06/AD6 AD6 I/O C  Z L EPROM data in D6 / address out A6
52 P07/AD7 AD7 I/O C  Z L EPROM data in D7 / address out A7
53 P10/AD8/A8 A8 O C  Z L EPROM address out A8
54 P11/AD9/A9 A9 O C  Z L EPROM address out A9
55 P12/AD10/A10 A10 O C  Z L EPROM address out A10
56 P13/AD11/A11 A11 O C  Z L EPROM address out A11
57 P14/AD12/A12 A12 O C  Z L EPROM address out A12
58 P15/AD13/A13 A13 O C  Z L EPROM address out A13
59 P16/AD14/A14 A14 O C  Z L EPROM address out A14
60 P17/AD15/A15 A15 O C  Z L EPROM address out A15
61 _WDTOUT ←OC Z H Watch dog output
62 Vss ← GND
63 Vcc ← +5V
64 P20/A0/A16 A16 O C  Z L EPROM address out A16
65 P21/A1/A17 O C  ZL
66 P22/A2/A18 ADIRCE O C  Z L DIR control terminal (LC89055Q) control chip enable output
67 P23/A3/A19 DIR MOSI O C  Z L DIR control terminal (LC89055Q) control data output
68 P24/A4/A20 O C  ZL
69 P25/A5/A21 FGAIN O C Ed L L FRONT ch GAIN switching control output (H: SW=NO)
70 P26/A6/A22 DAC-RESET O C Ed LL DAC control terminal (L: Power down mode, ↑(rising edge) Reset)
71 P27/A7/A23 SEL CK O C  Z L ADC/DIR data clock switching control terminal (L: ADC)
72 P30/_RD _RD O C  Z L Flash memory control terminal
73 P31/_WR _WR O C  Z L Flash memory control terminal
74 P32/_HWR CSI I Lv DIR control input terminal (L: PCM)
75 P33/_WAIT ERR MUTE_ O C Ed L L Pop noise preventive mute control output (L: Mute)
76 P34/_BUSRQ _DSP REQUEST O C  ZL (ADSP21065L:IRQ1_) host I/F interrupt request output (L: REQ)
77 P35/_BUSRQ DIG.(AC39 MUTE O C Ed Z L Digital mute control output (L: AC-3 or DTS decode enable)
78 P36/_R/W WRITE O C  Z L DSP comm. control terminal (H: Data write)
79 P37/_RAS DIR RESET O C  Z L DIR control output (LC89055Q) (L: Reset)
80 P40/_CS0/_CAS0 OC ZL
81 P41/_CS1/_CAS1 OC ZL
82 P42/_CS2/_CAS2 _CS0 O C  Z L Flash memory control terminal
83 P60/PG00 I/01 I/O C  Z L DSP comm. terminal (ADSP21065L: D16)
84 P61/PG01 I/02 I/O C  Z L DSP comm. terminal (ADSP21065L: D17)
85 P62/PG02 I/03 I/O C  Z L DSP comm. terminal (ADSP21065L: D18)
86 P63/PG03 I/04 I/O C  Z L DSP comm. terminal (ADSP21065L: D19)
87 P64/PG10 I/05 I/O C  Z L DSP comm. terminal (ADSP21065L: D20)
88 P65/PG11 I/06 I/O C  Z L DSP comm. terminal (ADSP21065L: D21)
89 P66/PG12 I/07 I/O C  Z L DSP comm. terminal (ADSP21065L: D22)
90 P67/PG13 I/08 I/O C  Z L DSP comm. terminal (ADSP21065L: D23)
91 Vss ← GND
92 P50/AN0 AUDIO LEVEL I Eu Lv Z Signal level detect, set to A/D input
93 P51/AN1 POSI (FAN) I Eu Lv Z Temperature detect, set to A/D input
94 P52/AN2 EMP I Lv H: EMP on
95 P53/AN3 96K DET I Lv 96k signal detect input, H: 96k
96 P54/AN4 BUSY1 I Lv (ADSP21065L:FLAG2A)
97 P55/AN5 FLAG 3A I Lv (ADSP21065L:FLAG3A)
98 P56/AN6 I Lv 
99 P57/AN7 I Lv 
100 V REFH ← AD ref. +5V
Symbol I/O Type Op Det Res Init
75
76
100
125
26
50
51
14
AVR-3801

15
AVR-3801
ADSP-21065L (AU: IC400)
Pin Name
ADSP-21065L Terminal Function
Pin
No. Pin Name
Pin
No.
Pin Name
Pin
Pin Name
Pin
Pin Name
Pin
Pin Name
Pin
1 VDD
2 RFS0
3 GND
4 RCLK0
5 DR0A
6 DR0B
7 TFS0
8 TCLK0
9 VDD
10 GND
11 DT0A
12 DT0B
13 RFS1
14 GND
15 RCLK1
16 DR1A
17 DR1B
18 TFS1
19 TCLK1
20 VDD
21 VDD
22 DT1A
23 DT1B
24 PWM_EVENT1
25 GND
26 PWM_EVENT0
27 BR1
28 BR2
29 VDD
30 CLKIN
31 XTAL
32 VDD
33 GND
34 SDCLK1
35 GND
36 VDD
37 SDCLK0
38 DMAR1
39 DMAR2
40 HBR
41 GND
42 RAS
43 CAS
44 SDWE
45 VDD
46 DQM
47 SDCKE
48 SDA10
49 GND
50 DMAG1
51 DMAG2
52 HBG
53 BMSTR
54 VDD
55 CS
56 SBTS
57 GND
58 WR
59 RD
60 GND
61 VDD
62 GND
63 REDY
64 SW
65 CPA
66 VDD
67 VDD
68 GND
69 ACK
70 MS0
71 MS1
72 GND
73 GND
74 MS2
75 MS3
76 FLAG11
77 VDD
78 FLAG10
79 FLAG9
80 FLAG8
81 GND
82 DATA0
83 DATA1
84 DATA2
85 VDD
86 DATA3
87 DATA4
88 DATA5
89 GND
90 DATA6
91 DATA7
92 DATA8
93 VDD
94 GND
95 VDD
96 DATA9
97 DATA10
98 DATA11
99 GND
100 DATA12
101 DATA13
102 NC
103 NC
104 DATA14
105 VDD
106 GND
107 DATA15
108 DATA16
109 DATA17
110 VDD
111 DATA18
112 DATA19
113 DATA20
114 GND
115 NC
116 DATA21
117 DATA22
118 DATA23
119 GND
120 VDD
121 DATA24
122 DATA25
123 DATA26
124 VDD
125 GND
126 DATA27
127 DATA28
128 DATA29
129 GND
130 VDD
131 VDD
132 DATA30
133 DATA31
134 FLAG7
135 GND
136 FLAG6
137 FLAG5
138 FLAG4
139 GND
140 VDD
141 VDD
142 NC
143 ID1
144 ID0
145 EMU
146 TDO
147 TRST
148 TDI
149 TMS
150 GND
151 TCK
152 BSEL
153 BMS
154 GND
155 GND
156 VDD
157 RESET
158 VDD
159 GND
160 ADDR23
161 ADDR22
162 ADDR21
163 VDD
164 ADDR20
165 ADDR19
166 ADDR18
167 GND
168 GND
169 ADDR17
170 ADDR16
171 ADDR15
172 VDD
173 ADDR14
174 ADDR13
175 ADDR12
176 VDD
177 GND
178 ADDR11
179 ADDR10
180 ADDR9
181 GND
182 VDD
183 ADDR8
184 ADDR7
185 ADDR6
186 GND
187 GND
188 ADDR5
189 ADDR4
190 ADDR3
191 VDD
192 VDD
193 ADDR2
194 ADDR1
195 ADDR0
196 GND
197 FLAG0
198 FLAG1
199 FLAG2
200 VDD
201 FLAG3
202 NC
203 NC
204 GND
205 IRQ0
206 IRQ1
207 IRQ2
208 NC
1
53
52 104
105
156
157208
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16
AVR-3801
LC89055W (AU: IC531)
Pin Name Function
LC89055W Terminal Function
Pin
No.
1 DISEL I Data input terminal (select input pin of DIN0, DIN1)
2 DOUT O Input bi-phase data through output terminal
3 DIN0 I Amp built-in coaxial/optical input correspond data input terminal
4 DIN1 I Amp built-in coaxial/optical input correspond data input terminal
5 DIN2 I Optical input correspond data input terminal
6 DGND Digital GND
7 DVDD Digital power supply
8 R I VCO gain control input terminal
9 VIN I VCO free-run frequency setting input terminal
10 LPF O PLL loop filter setting terminal
11 AVDD Analog power supply
12 AGND Analog GND
13 CKOUT O Clock output terminal (256fs, 384fs, 512fs, X′tal osc., VCO free-run osc.)
14 BCK O 64fs clock output terminal
15 LRCK O fs clock output terminal (L: Rch, H: Lch, I2S: Reverse)
16 DATAO O Data output terminal
17 XSTATE O Input data detecting result output terminal
18 DGND Digital GND
19 DVDD Digital power supply
20 XMCK O X′tal osc. clock output terminal (24.576MHz or 12.288MHz)
21 XOUT O X′tal osc. connection output terminal
22 XIN I X′tal osc. connection input terminal, external signal input possible (24.576MHz or 12.288MHz)
23 EMPHA O Emphasis information output terminal of channel status
24 AUDIO O Bit1 output terminal of channel status
25 CSFLAG O Top 40bit revise flag output terminal of channel status
26 F0/P0/C0 O Input fs cal. sig. out / data type out / input word inf. output terminal
27 F1/P1/C1 O Input fs cal. sig. out / data type out / input word inf. output terminal
28 F2/P2/C2 O Input fs cal. sig. out / data type out / input word inf. output terminal
29 VF/P3/C3 O Validity flag out / data type out / input word inf. output terminal
30 DVDD Digital power supply
31 DGND Digital GND
32 AUTO O Non PCM burst data transfer detect sig. output terminal
33 BPSYNC O Non PCM burst data preamble Pa, Pb, Pc, Pd sync sig. output terminal
34 ERROR O PLL lock error, data error flag output terminal
35 DO O CPU I/F read data output terminal
36 DI I CPU I/F write data input terminal
37 CE I CPU I/F chip enable input terminal
38 CL I CPU I/F clock input terminal
39 XSEL I Frequency select input pin of XIN X′tal osc. (24.576MHz or 12.288MHz)
40 MODE0 I Mode setting input terminal
41 MODE1 I Mode setting input terminal
42 DGND Digital GND
43 DVDD Digital power supply
44 DOSEL0 I Data output format select input terminal
45 DOSEL1 I Data output format select input terminal
46 CKSEL0 I Output clock select input terminal
47 CKSEL1 I Output clock select input terminal
48 XMODE I Reset input terminal
I/O
* For latch-up countermeasure, set digital (DVDD) and analog (AVDD) power on/off in the same timing.
DISEL
DOUT
DIN0 DIN1 DIN2
DGND
DVDD
R
VIN
LPF
AVDD
AGND
AUDIO
EM PHA
XIN
XOUT
XM CK
DVDD
DGND
XSTATE
DATA0
LR C K
BCK
CKOUT
CE
CL
XSEL
MODE0
MODE1
DGND
DVDD
DO SEL0
DO SEL1
CKSEL0
CKSEL1
XM O DE
DI DO ERROR BPSYNC AUTO DGND DVDD VF/P3/C3 F2/P2/C2 F1/P1/C1 F0/P0/C0 CSFLAG
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17
AVR-3801
M35015-210SP Terminal Function
Pin No. Symbol Name I/O Function
1 OSC1 Osc. circuit ext. I External terminal for indication oscillator circuit. Standard OSC. freq. is approx. 7MHz.
2 OSC2 terminal. O With this OSC. freq., decides horizontal indicatin and character width.
3 CS Chip select input I Chip select terminal and turns to “L” when transfer serial data.
Hysteresis input. Pull up resistor is built-in.
4 SCK Serial clock input I Takes in serial data of SIN at SCK rise when CS terminal is in “L”.
Hysteresis input. Pull up rersist is built-in.
5 SIN Serial data input I Serial input of register for indication control and data, and address for indication data
memory. Hysteresis input. Pull up rersistor is built-in.
6 AC Auto-clear input I Resets internal circuit of IC at “L” mode.
Hysteresi input. Pull up resistor is built-in.
7V
DD2 Power supply Power supply terminal of analog system. Connect to +5V.
8CVIDEO
Combined
video output OOutput terminal of combined video signal. Outputs 2Vp-p combined signal. Character
output, etc. Overlap CVIN signal and outputs at superimpose.
9 LECHA Character level
input IInput terminal deciding character output level in combined video signal. color of character
is white.
10 CVIN Combined video
input IInput terminal of external combined video signal.
Character output etc. overlap this external combined video signal.
11 Vss Ground Ground terminal. Connect to GND.
12 P0 Output port p0 O General output or character background signal BL NK1* output is switchable.
Polarity can be selected at ROM mask.
13 P1 Output port P1 O General output or character background signal CO1* output is switchable.
Polarity can be selected at ROM mask.
14 P2 Output port P2 O General output or character background signal BLNK2* output is switchable.
Polarity can be selected at ROM mask.
15 P3 Output port P3 O General output or character background signal CO2* output is switchable.
Polarity can be selected at ROM mask.
16 OSCOUT O Terminal for external use of sync signal OSC. circuit. Use the freq.: 14.32MHz at NTSC
17 OSCIN I system, 17.73MHz at PAL. system, 14.30MHz at MPAL system.
18 HOR* Horizontal sync
signal IInputs horizontal sync signal.
Hysteresis input.
19 VERT* Vertical sync
signal Input vertical sync signal. Hysteresis input. Polarity can be selected at ROM mask.
20 VDD1 Power supply I Power supply terminal of digital system. Connect to +5V.
Ext. terminal
for sync sig.
OSC. Circuit
M35015-210SP (AC: IC308)
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OSC1
OSC2
CS
SCK
SIN
AC
V
DD2
CVIDEO
LECHA
CVIN
V
DD1
VERT*
HOR*
OSCIN
OSCOUT
P3
P2
P1
P0
Vss
CS
SCK
SIN
V
DD1
20
AC
Vss
V
DD2
P1
P0
CVIN
LECHA
CVIDEO
OSCOUT
OSCIN
HOR*VERT*OSC2OSC1
IN P U T
CONTROL
CIRCUIT
INDICATION
O SC ILLA TO R
DATA
CONTROL
CIRCUIT
ADDRESS
CONTROL
CIRCUIT TIM ING
GENERATOR
INDICATION
CONTROL
REGISTER
INDICATION RAM
INDICATION CHARACTER ROM
LINKING CIRCUIT
SHIFT REGISTER
INDICATION
CONTROL CIRCUIT
READ OUT ADDRESS
CONTROL CIRCUIT
IINDICATION LOCATION
DETECTION CIRCUIT
H COUNTER
SYNC SIG NAL
SW ITCHING CIRCUIT
S Y N C S IG N A L D IS -
CRIMINATING CIRCUIT
OSC CIRCUIT
FO R SYNC SIGNAL
GENERATION
TIM ING
GENERATOR
NTSC
VIDEO OUTPUT
CIRCUIT
6
11
5
4
3
7
1 2 19 18
17
16
8
9
10
12
13
P2
14
P3
15
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18
AVR-3801
Symbol Function
CO: IC304
Q1 A Video input switching
Q2 B Video input switching
Q3 C Video input switching
Q4 D Video output switching
Q5 E Video output switching
Q6 F Video output switching
Q7 H Video output switching
Q8 G Video output switching
Port
Symbol Function
CO: IC305
Port
Q1 DIRECT DIRECT relay control (H: DIRECT)
Q2 S1 Video signal switching control output
Q3 S2 Video signal switching control output
Q4 SB/MULTI S.BACK/MULTI switching control (H: MULTI (Power AMP Assignment))
Q5 NC
Q6 NC
Q7 NC
Q8 NC
BU4094BCF (CO: IC304, 305)
AK5353 (AU: IC604)
STROBE 1
2
3
4
5
6
7
89
10
11
16
15
14
13
12
DATA
CLOCK
Q1
Q2
Q3
Q4
VSS
VDD
OE
Q5
Q6
Q7
Q8
Q'
S
QS
AINR
AINL
VREF
VCOM
AGND
VA
VD
DGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TST
TTL
DIF
PDN
SCLK
MCLK
LRCK
SDTO
Name Function
Terminal Function
No.
1 AINR I Rch analog input pin
2 AINL I Lch analog input pin
3 VREF O Ref.V out pin
4 VCOM O Common V out pin
5 AGND Analog GND pin
6VA Analog power pin, +2.7~+5.5V
7VD Digital power pin, +2.7~+5.5V
8 DGND Digital GND pin
9 SDTO O Serial data out pin, 2's complement, MSB first out, at power down: L
10 LRCK I L/R clock pin
11 MCLK I Master clock input pin
12 SCLK I Serial data clock input pin, A/D data out at SCLK falling edge
13 PDN I Power down pin, L: Power down mode
14 DIF I Serial interface format pin (L: Firward, H: I2S)
15 TTL I Digital input level select pin, L: CMOS level, H: TTL level
16 TST I Test pin (internal pull-down)
I/O
TC9274N-011 (AU: IC107)
1
23456789
10 11 12 13 14 15 16 17 18 19
20
21
22
23
24
25
26
2728
29
3031
32
33
3435
36
37
38
3940
41
42
V
DD
V SS
S1 S2 S3 S4 S5 S6 S7 S8 S9
S10 S11 S12 S13 S14 S15 S16 S17 S18
GND
CK
DATA
STB
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18
18 bit Latch Circuit (Rch)
(Lch) Same as Rch
L e v e l S h ft + S h ft R e g s te r C rc u t
1
23456789
10 11 12 13 14 15 16 17 18 19
20
21
22
23
24
25
26
2728
29
3031
32
33
3435
36
37
38
3940
41
42
V
DD
V SS
S1 S2 S3 S4 S5 S6 S7 S8 S9
S10 S11 S12 S13 S14 S15 S16 S17 S18
GND
CK
DATA
STB
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18
18 bit Latch Circuit (Rch)
(Lch) Same as Rch
L e v e l S h ft + S h ft R e g s te r C rc u t
TC9274N-012 (IC312)

19
AVR-3801
LC72131M (AC: IC507)
LA1265 (S)
(AC: IC502)
1
VOL
REG OSC
SYM M ETRICAL
REOCTANCE
CIRCUIT
PHASE
COMPARATOR
VCO STOP
PILO T DET
FF FF FF
38kH z
FF
38kH z 90°
FF
19kH z 90°
MUTING
FM AM CH AN G E
Ro
Rc
Rc Rb
DECODER M UTING CO N TRO L
F M A M C H A N G E O V E R
Vcc ON
MUTING
MUTING
OUTPUT
STEREO
SW ITCH
TRIGGER
LAM P
DRIVER
Rb
2345678910 11
22 21 20 19 18 17 16 15 14 13 12
LA3401 (AC: 503)
120
219 318
417 516 615
714 813 912
10 11
XIN
CE
DI
CL
DO
BO1 BO2 BO3 BO4
IO 1
AOUT AIN PD V
DD
FM IN AM IN IO 2 IF IN Vss XOUT
123
4
567
8
9
10
11
12
13 14
15
16
17
18
19
20
21 22
22
1
11
FM IF
Level
Det.
Level
Det.
RF Amp Mix. AM IF Det. LED
Driver
Osc. Buffer Reg. AGC S meter SD Adj
GND
Q Det
S Curve
Vcc
Post
Amp
BU2090F (EX: IC103)
1Vss
2DATA
3CLOCK
4LCK
5Q0
6Q1
7Q2
8Q3
9Q4
18
17
16
15
14
13
12
11
10
V
DD
OE
Q11
Q10
Q9
Q8
Q7
Q6
Q5
CONTROL CIRCUIT
12-bit SHIFT RESISTER
12-bit STRAGE RESISTER
OUTPUT BUFFER (OPEN DRAIN)

20
AVR-3801
BA7625 (AC: IC302, 377) (RE: 402, 450, 451)
BA7626 (AC: IC301, 376) (RE: 452, 453)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Monitor OUT
GND
IN5
GND
IN4
CTL E
IN3
CTL D
IN1
CTL A
V OUT1
Vcc
IN2
CTL B
V OUT2
CTL C
6dB
6dB
LOGIC
LOGIC
AB E
MONITOR OUT
LL * IN1
HL * IN2
LH * IN3
HH L IN4
HHH IN5
CD E V OUT1
LL * ¾
HL * IN2
LH * IN3
HH L IN4
HHH IN5
CD E
MONITOR OUT
LL * IN1
HL * ¾
LH * IN3
HH L IN4
HHH IN5
Note 1: * mark means that feasible for either H or L.
Note 2: Each input terminal is provided with sink chip clamp (BA7625).
Each input terminal takes 20kohm at the end (BA7626).
LC75721E (EX: IC101)
64
49
48 33
32
17
161
AM 1 AM 2 AM 3 AM 4 AM 5 AM 6 AM 7 AM 8 AM 9 AM 10 AM 11 AM 12 AM 13 AM 14 AM 15 AM 16
AM 17
AM 18
AM 19
AM 20
AM 21
AM 22
AM 23
AM 24
AM 25
AM 26
AM 27
AM 28
AM 29
AM 30
AM 31
AM 32
G7 G8 G9 G10 G11 AA8/G12 AA7/G13 AA6/G14 AA5/G15 AA4/G16 AA3 AA2 AA1 AM35 AM34 AM33
DI
CL
CE
RES
V
DD
OSCI
OSCO
Vss
TEST
V
FL
G1
G2
G3
G4
G5
G6
Symbol
V
DD
Vss
Power terminal +5V
Power terminal GND
V
FL
Power terminal FL drive
DI
CL
CE
Serial data transfer terminal
DI: Data
CL: Clock
CE: Chip enable
OSCI
OSCO External CR connecting terminal
RES System reset terminal
AM1~AM35
AA1~AA3 Anode output terminal
AA4/G16
AA5/G15
AA6/G14
AA7/G13
AA8/G12
Anode/Grid output terminal
G1~G11 Grid output terminal
TEST LSI test terminal
Function
LC75721E Terminal Function
74VHC541MTC (AU: IC413)
SN74AHCT541PW (AU: IC414)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
G1
A1
A2
A3
A4
A5
A6
A7
A8
GND
Vcc
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
TC9273N-004 (AU: IC108)
S2
S3
S4
S5
S6
S7
S8
S9
S10
S1
V
DD
STB
DATA
S2
S3
S4
S5
S6
S7
S8
S9
S10
GND
CK
Vss
S1
13
14
1
3
4
5
6
7
8
9
10
11
12
2
15
16
28
27
26
25
24
23
22
21
20
19
18
17
1
13
28
2~12
12~27
14
15
16
Vss
GND
V
DD
S1~S10
CK
DATA
STB
GND=0V
Vss=-8.0~-17V
GND=0V
Border Input
Pin No Symbol Name Function
Dual Power Use:VDD = 8.0~17 V Single Power Use:VDD = 8.0~18V
+Power Terminal
Digital Ground
+Power Terminal
I/O Terminal
Clock Input Low level
Terminal
Clock input for data transfer.
Serial input for switch setting.
Strobe InputStrobe input for data writing.Strobe Input
Data Input
Input terminal of analog switch.
TC9273N Terminal Function