Digital Equipment DA10 User manual

~D~DDmD
DA10 PDP-BIB INTERFACE

DEC-1O-IACA-D
DA1D
PDP-B/8 INTERFACE
INSTRUCTION
MANUAL
June 1968
DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS

Copyright © 1968 by Digital Equipment Corporation

1.1
1.2
1.3
2. 1
2.2
2.2. 1
2.3
2.3. 1
2.3.2
2.3.3
2.4
2.4. 1
2.4.2
2.4.3
3. 1
3.2
3.3
3.4
3.4. 1
3.5
3.6
3.7
3.8
3.8. 1
3.8.2
3.8.3
CONTENTS
CHAPTER 1
INTRODUCTION
Referenced Publications
General Description
Equipment Specifications
CHAPTER 2
OPERATION AND PROGRAMMING
Indi cator Panel
Power Control Panel
Power Application
Device Selection
PDP-lO Device Selection
PDP-9 Devi ce Selection
PDP-8 Devi ce Selection
Programming Notes
PDP-l0 Instructions
PDP-9 Programming
PDP-8 Programming
Power Requirements
Environmental Conditions
Space Requ irements
Device Selection Wiring
CHAPTER 3
INSTALLATION
PDP-8
Devi ce Selection Cards
Data Transfer Pulse
Mi xers
FM 10 Buffer Output Mixer
TOlO Buffer Input Mixer
I/O Bus Connections
PDP-l0 I/O Bus Cables
PDP -9 I/O Bus Cables
PDP-8
I/O Bus Cables
iii
1-1
1-2
1-2
2-1
2-2
2-3
2-4
2-4
2-4
2-4
2-5
2-5
2-6
2-7
3-1
3-1
3-1
3-1
3-1
3-2
3-5
3-8
3-10
3-10
3-11
3-12

CONTENTS (Cont)
Page
3.9
One-Shot Adjustment 3-12
CHAPTER 4
THEORY OF OPERATION
4. 1 Functional Description
4-1
4.2
Detai led Description
4-3
4.2.1
Data Transfer to a PDP-8
4-4
4.2.2
Data Transfer to a PDP-9
4-7
4.2.3
Data Transfer From a PDP-8 to a PDP-10
4-12
4.2.4
Data Transfer From a PDP-9 to a PDP-10
4-16
4.3
Self-Check Operation
4-19
4.4 Power Turn-On and Initialization
4-26
4.5 Logic Block Diagrams
4-26
4.5, 1 Signals Mnemonics
4-29
4.5.2 Logi c Functions
4-29
CHAPTER 5
MAINTENANCE
5. 1
Preventive Maintenance
5-1
5. 1. 1 Mechanical Checks 5-1
5. 1.2 DEC Type 728 Power Supply 5-2
5. 1 .3
Margi n Checks 5-2
5.2 Corrective Maintenance 5-2
5.2. 1 Prel iminary Investigation 5-3
5.2.2
System Troubleshooting 5-3
5.2.3
Module Troubleshooting
5-5
5.3
Repair
5-5
5.3. 1 Type
R302 Module Replacement 5-6
5.4
Validation Test
5-6
5.5
Log Entry
5-6
5.6
Spare Parts Li st
5-6
iv

CONTENTS (Cont)
Page
CHAPTER 6
ENGINEERING DRAWINGS
6. 1 Drawing Terminology
6-1
6.2
Logi c Symbols
6-2
6.3
Logi c Levels
6-2
6.4
Flip Chip Pulses
6-4
6.5
Engineering Drawing List
6-5
TABLES
1-1 Available Publications
1-1
1-2 DA 10 General Specifi cations
1-4
2-1 DA 10 Indicator Panel
2-1
2-2 Power Control Panel,
Switches and Indi cators
2-3
3-1
PDP-l0 I/O Bus Cables
3-11
3-2
PDP-9 I/O Bus Cables
3-11
3-3
PDP-8 I/O Bus Cables
3-12
5-1 Recommended Spare Parts for DA 10
5-7
6-1
DA 10 Engineering Drawings
6-5
ILLUSTRATIONS
1-1 DA 10 Interface, Typi cal System Diagram
1-3
1-2 DA 10 Interface, Assembly Locations
1-3
2-1
DA10 Interface, Indicator Panel
2-1
2-2
Type 844 Power Control Panel
2-3
2-3
CONO Data Word
2-5
2-4
CONI Data Word
2-6
3-1 DA 10 Area Requirements 3-2
3-2
PDP-8/DA10 Device Selection Cards
3-3
3-3
FM 10 Buffer Output Mixer -PDP-8 Strapping 3-6
3-4
FM 10 Buffer Output Mixer - PDP-9 Strapping
3-7
3-5
TOlO Buffer Input Mixer - PDP-8 Strapping
3-8
3-6
TOlO Buffer Input Mixer - PDP-9 Strapping
3-9
4-1
DA 10 Interface - Simplified Block Diagram
4-2
v

ILLUSTRATIONS (Cont)
Page
4-2
Data Transfer from PDP-IO to PDP-8, Simplified Block Diagram
4-5
4-3 Data Transfer from PDP-lO to PDP-9, Simplified Block Diagram
4-9
4-4
PDP-9 lOT Instruction Format 4-11
4-5 Data Transfer from PDP-8 to PDP-10, Simplified Block Diagram 4-13
4-6 Data Transfer from PDP-9 to PDP-lO, Simplified Block Diagram 4-17
4-7 DA 10 Self-Check Block Diagram (Part 1) 4-21
4-7
DA 10 Self-Check Block Diagram (Part 2)
4-23
4-8 Power Up and CO NO Instruction, Simplified Block Diagram 4-27
6-1
DEC Standard Logi c Symbols 6-3
6-2
R-Series and S-Series Pulses
6-4
6-3 B-Series Pulse
6-4
vi

DA10
PDP-8/9 INTERFACE

----~-----
-------:...~----
;::~=-:.--
DA 10 PDP-8/ 9 Interface

CHAPTER 1
INTRODUCTION
The DA 10 Interface is an optional unit available with the PDP-10 System, manufactured by
Digital Equipment Corporation (DEC) Maynard, Massachusetts. The interface allows data and control
information to be transferred in both directions between the PDP-10 processor and either a PDP-8
processor or a PDP-9 processor.
This manual and the documents referenced herein provide the necessary information for the
installation, operation and mainteance of the DA10 Interface Unit. The level of discussion in this
manual assumes the reader is fami liar with the logic symbology used by DEC, and the general operations
of the PDP -8, PDP -9, and PDP - 10 processors.
1. 1 REFERENCED PUBLICATIONS
Table 1-1 lists the publications which are available to supplement the information in this
manual. These documents can be obtained from the nearest DEC regional office or by writing to:
Title
Digital Logic Handbook
PDP-10 Maintenance
Manuals
Volume 1
Volume 2
Volume 3
Digital Equipment Corporation
146 Main Street
Maynard, Massachusetts 01754
Table 1-1
Avai
lable Publications
Document No. Descripti on
C-105 Description and specifications of the
standard FLIP CHIP modules. Simplified
explaination of the selection and use
of the modules.
DEC-1O-HMAA-D Complete information on the internal
operation of the KA 10 Processor mem-
ory, basic I/O, and opti ons.
DEC-1O-HMBA-D The engi
neeri ng drawings associ ated
with the KA 10 Processor.
DEC-10-HMCA-D Description, schematics and specifi-
cations of the special modules used in
the PDP-10 System.
1-1

Title
PDP-10 Peripheral
Device
Engineering Drawing Set
(Volume 4)
PDP-S Maintenance
Manual
PDP-9
Maintenance
Manuals
Volume 1
Volume 2
DA 10 Interface Test
PDP-10 System
Reference Manual
Table 1-1 (Cont)
Avai
lable Publications
Document No.
DEC-1O-I6DA-D
F-S7
F-97
F-97
MAINDEC-l0-DSAO-D
DEC-lO-HGAA-D
1.2 GENERAL DESCRIPTION
Description
Logic
block diagrams and other pertin-
ent engineering drawings for BA 10 and
DA 10 options.
Complete information on the PDP-S
processor operation and avai lable
options.
Complete information on the PDP-9
Processor
and avai lable options.
Logic block diagrams and other pertin-
ent engineering drawings for the PDP -9 •
A description and listing of the program
used
to detect and diagnose malfunc-
tions in the DA 10.
Programming and operating information
on
the PDP-lO Processor and options.
The DAlO Unit allows the interconnecting of the Input/Output (I/O) Bus from the KA10
Processor to the I/O bus of either a PDP-S or PDP-9 Processor. Because of the differences in word
length and I/O signals of the three devices, the DA 10 interface assembles 12-bit words from the
PDP-S or lS-bit words from the PDP-9 into a 36-bit word for transfer to the PDP-l0 Processor, or
divides a 36-bit word from the PDP-l0 into the required length for transfer to the associated processor.
Figure 1-1 is a
typical system diagram using the DA10 Interface. During input and output operations
the DA 10 receiyes both data and control informati on.
1.3 EQUIPMENT SPECIFICATIONS
Figure 1-2 shows the assemblies mounted in the front and rear of the DA10 Unit which con-
sists of a standard 19 in. cabinet, Type CAB-9B, which is contructed with welded steel frames and
sheet a lumi num coveri ng. Access doors are mounted on the front and rear of the cabi net and are
held closed by magnetic latches. The power control and dc power supply are mounted inside the rear
1-2

access door on a plenum door that is latched by a spring-loaded pin at the top. Module mounting
panels are mounted behind the front door with the wiring side facing outward. Access to the modules
for removal, replacement and/or adjustment is gained through the rear of the cabinet. A fan at the
bottom of the cabinet draws cooling air into the cabinet through a dust filter, and a fan assembly
mounted in the logic rack passes the cooling air over the modules. The air is exhausted through an
opening
at the top of the cabinet. Table 1-2 contains the general specifications of the DA lOA and
DA lOB units.
DATA 8 CONTROL
KAII2I A
DATA 8 CONTROL
PROCESSOR
I/O BUS
UNIT V DAIO
INTERFACE
I/O BUS
PCI"-B OR PDP-9
~
UNIT
PROCESSOR UNIT
'-'
TO OTHER DEVICES
Figure 1-1 DA 10 Interface, Typical System Diagram
[ INDICATOR I PANEL
BLANK
BLANK
BLANK BLANK
BLANK BLANK
BLANK
BLANK BLANK
BLANK BLANK
BLANK
A MODULE
MOUNTING
728A OR 728B
B PANEL
POWER SUPPLY
C MODULE MOUNTING
D PANEL
844
POWER
E MODULE MOUNTING CONTROL
F PANEL BLANK
FAN ASSEMBLY
FRONT VIEW REAR VIEW
Figure 1-2 DA 10 Interface, Assemb Iy Locat ions
1-3

Table 1-2
DA 10 Genera I Speci fi cat ions
Current Power Heat Service Maximum
Voltage
(A)
Dissipation Dissipation Dimensions
Clearance
Weight Cable
ac
Nominal
(W)
(Btu;hr) (in .)
(i n.)
(lb) Lengths
115V (ft)
See Height:
69
PDP-8: 20
Notes Front 36 PDP-9: 100
1 and
2.0 230 800
Wi dth: 21-1/4
Rear 36
300 PDP-10: 150
2 Depth: 27
(I/O Bus)
Note 1: PDP-10 Systems normally operate from 3-phase (WYE connected), 115V ± 10%, 60 Hz ±
2 Hz, or 230V ± 10%,50 Hz ± 2 Hz phase to neutral. Individual devices have separate power cords
using
3-wire 30A (single phase) Hubbel Twistlock connectors. An earth/ground connection must be
supplied through the power cord in addition to the ground bus requirements.
Note 2: Equipment for use within North America will have the 3-wire Hubbel #3331 (mates with
Hubbel #3330) power cord cap (male plug) supplied on the end of a 25 ft line cord.
Equipment for use outside of North America will have a pressure-type terminal strip suitable for 8 to
18 gage wire enclosed within the equipment's power control.
Two configurations of the DA10 are available. The Type DA10A is a 60 Hz configuration
and the Type DA lOB is a 50 Hz configuration. With the exception of the power supply and power
wiring, both configurations are similar. A 728 power supply is used with the DA10A and a 728A power
supply is used with the DA10B. The differences in the power wiring of the two configurations are shown
on drawing
D-IC-DA 10-0-3.
1-4

CHAPTER 2
OPERATION AND PROGRAMMING
The following paragraphs provide the information and programming notes needed to operate
the DA10 Interface with either a PDP-8 or PDP-9 Processor. For the detailed programming information
refer to the PDP-10 System Reference Manual, DEC-10-HGAA-D.
2.1 INDICATOR PANEL
The indi cat or panel (Fi gure 2-1) is mounted on the top front of the DA 10 cabi net. It con-
tains the indicators listed in Table 2-1 and displays the contents and status of the registers and flip-flops
in this interface unit.
Figure 2-1 DA10 Interface, Indicator Panel
Table 2-1
DA10 Indi cator Panel
Indi cator
Function
FROM 10 BUFFER
Indi cates the contents of the FM 10 Buffer,
bits 0 through 35.
(0 through 35)
TO 10 BUFFER
Indi cates the contents of the TO 10 Buffer, bits 0 through 35.
(0 through 35)
2-1

Indi cator
PWR
DEV SEL
8
9
10
EMPTY
TOW
(STAT BUFD)
FMW
(STAT BUFB)
FULL
TOlO
(STAT BUFC)
FMlO
PI CHANNEL
(33 through 35)
Table 2-1 (Cont)
DA10 Indicator Panel
Function
Lights to indicate that dc power is applied to the logic rack.
Lights to indicate that DAlO is selected by the PDP-8 Processor.
Lights to indicate that DA10 is selected by the PDP-9 Processor.
Lights to indi cate that DA 10 is selected by the PDP-l0 Processor.
Lights to indicate that the 36-bits in the TO 10 Buffer have been
transferred to the PDP-W or that bit IOB32 is set to a 1 during a
CONO instruction.
Li ghts to indi cate that the last byte of the FM 10 Buffer has been
transferred to the PDP-8 or PDP-9 or that IOB28 is set to a 1
during a CONO instruction.
Lights to indicate that the last byte from a PDP-8 or PDP-9 which
loads
the TOlO Buffer has been received or that bit IOB30 is set
to a 1 during a CONO instruction.
Lights to indicate that 36-bits from the PDP-l0 have been loaded
into the FM 10 Buffer or that bit IOB26 is set to a 1 during a
CONO instruction.
Indicates the binary configuration of the PI Channel selected.
2.2 POWER CONTROL PANEL
The Type
844 Power Control Panel (Figure 2-2) is mounted on the plenum door at the rear
of the cabinet. This panel contains the switches and indicators (listed in Table 2-2) that are used to
control the main ac power and select the local and remote modes of operation.
2-2

Figure 2-2 Type 844 Power Control Panel
Table 2-2
Power Control Panel, Switches and Indi cators
Swi tch/Indi cator
White indicator
Red indi cator
30 AMP
(Circuit Breaker)
REMOTE/LOCAL
(Switch)
POWER
(Switch)
2.2. 1 Power Application
Function
Lights to indicate that 115 Vac or 230 Vac line power is applied.
Lights to indicate wrong polarization of the ac line or when
230 Vac is applied.
Controls the line power to the convenience outlets and protects
the input line.
Selects either LOCAL or REMOTE mode of operation. (Refer to
Paragraph 2.2. 1.)
Controls line power to the dc power suppliers and DA10 system.
The DA 10 has two power appli cation modes selectable by the REMOTE/LOCAL switch on
the power control panel. In the remote mode, power to the DA 10 is controlled by the POWER switch
on the control panel of the KA 10 Processor when the following conditions are met.
2-3

a. The PDP-10 remote turn-on bus is connected to the DA10 power control.
b. The REMOTE/LOCAL switch on the power control panel of the DA 10 is in the REMOTE
position.
c. The circuit breaker and POWER switch on the DA 10 power control panel are in the
up position.
The local mode is in effect when the REMOTE/LOCAL switch is in the LOCAL position.
This allows the 30A circuit breaker and POWER switch to control power to the unit.
2.3 DEVICE SELECTION
The DA 10 is selected via the I/O busses of the PDP-8 or PDP-9 or the PDP-lO central
processors. Each central processor selects the DAlO in an independent manner, therefore, each
method is explained separately in this section. For additional information on device selection, refer
to Chapter 3, Installation.
2.3. 1 PDP-lO Device Selection
The DA 10 is selected by bits 3 through 9 of the I/O instructions from the PDP-l0 central
processor. Seven complementary pairs of signals representing IOS3 through IOS9 are sent to the DA lO
via the I/O bus. The lOS lines necessary to select code 0148 (000001 12) are. connected to an AND
gate shown on drawing D-BS-DAlO-O-CS. When this code appears on the I/O bus, the AND gate is
enabled and its output conditions the DATAO enable, DATAl enable, CONO enable, and CONI
enable gates.
2.3.2 PDP-9 Device Selection
The PDP-9 central processor uses bits 6 through 13 of lOT instructions for device selection.
These eight levels form a 6-bit device selection code, DSO through DS5, and two subdevice selection
codes, SDO and SD1. The PDP-9 device code 228 (OlO OlO2) has been assigned to the DA 10. When
this code
is present on the device selection lines of the I/O bus, it is decoded by the decoder shown
on drawing D-BS-DA1O-0-SI. The subdevi
ce codes SDO and SDl are ANDed with the appropriate
lOP signals to generate buffer clear and data transfer signals as shown on drawing D-BS-DA1O-0-DTL.
2.3.3
PDP-8 Device Selection
The PDP-8 central processor uses bits 3 through 8 of the lOT instructions for device selection.
These lines are connected to a pair of W990 modules located in card slots D04 and D05, as shown on
drawing D-BS-DA
10-0-SI. Jumpers are inserted on the W990 modules to obtain the outputs that are
2-4

used for decoding, and the decoders are shown in the upper left-hand corner of the drawing. The
PDP-S codes assigned to the DA 10 are as follows; 70
8 (111
000
2
), 718 (111 001 2 ), and 72 (111 0102 ).
In the event that these codes conflict with another peripheral device in a particular system, they can
be changed by modifying the jumpers on the W990 modules. It must be noted that the codes cannot
overlap octal triads (i .e., the most significant octal bit must be the same for all selected codes).
Refer to Paragraph 3.4.1 for additional information on jumper placement.
2.4
PROGRAMMING NOTES
2.4. 1
PDP-lO Instructions
The
DA 10 responds to the standard PDP -10 I/O instructions. It requires one I/O devi ce
number (standard: 014) and provides program interrupt requests on one PI channel. Data, status, and
control are transferred via the assigned I/O instructions. Various aspects of the I/O instructions are
described below.
2.4.1.1 CONO (Conditions Out) -Control information is transferred to the DA 10 via the right
lS-bits of a CONO instruction. Figure 2-3 shows specifically which bits are used and the respective
functions that are performed if the specific bit is a 1 during the performance of the CONO instruction.
The CONO instruction is completed in two parts. First, the CONO clear pulse is sent to the DA 10,
and 1 fJs later, the CONO SET pulse is sent. Since the PI channel (bits 33 through 35) is cleared by
the CONO clear pulse, the PI channel assignment must be placed on bits 33 through 35 whenever a
CONO instruction is performed to set the PI channel.
Clear
Set
Clear Set
Clear Set Clear
Set
Clear
Set
1Set I
Self Self FM10 FM10 FM10 FM10 TOlO TOlO TOlO TOlO
Check Check
Full Full Empty Empty Full Full Empty Empty
PI Channel
Enable Enable Flag Flag Flag Flag Flag Flag Flag Flag I
34 I
23 24 25 26 27 28
29
30
31
32
33 35
Figure
2-3 CONO Data Word
2.4. 1.2 CONI (Conditions In) -The status of the DA 10 is transferred to the central processor by a
CONI instruction. Figure 2-4 shows specifically which bits are transferred and their respective func-
tion. A 1 in any bit except bits 33 through 35 indicates that the associated flag is set. References to
the CONI instruction include the CaNSO and CONSZ instructions.
2-5

Self FM10 FM10
TOIO TOIO
I Check Full Empty Full Empty
Enable Flag Flag Flag Flag
PI Channel
23
24
25 26 27 28 29
30 31 32
33 I 34 I35
Figure
2-4 CONI Data Word
2.4.1.3 DATAO (Data Out) -The DATAO instruction is performed in two parts. First the DATAO
clear pulse is sent to the DA10, and 11-'s later, the DATAO SET pulse is sent. In the case of the DA10,
the DATAO clear pulse performs the following functions: clears the FM 10 buffer conditioning it for a
data transfer; and clears the FMIO EMPTY flag removing the PI request to the PDP-l0. The DATAO
set pulse performs the following functions: strobes the data on the PDP-1O I/O bus into the FM 10
buffer; and sets the FM 10 FULL flag enabling the PI gate in the DA 10 which sends a PI request to the
PDP-8 or PDP-9. References to the DATAO instruction in this manual include the appropriate func-
tions of the BLKO instruction.
2.4. 1.4 DATAl (Data In) -When the DATAl instruction is performed, commands to the DA 10 will
transfer the contents of the TOIO buffer to the central processor via the 36 data lines of the I/O bus,
c lear the TO 10 FULL flag, and set the TO 10 EMPTY flag. The clearing of the TO 10 FULL flag removes
the PI request from the PDP-IO, and the setting of the TO 10 EMPTY flag sends a PI request to the PDP-8
or
PDP-9. The references to DATAl instructions in this manual include the appropriate functions of the
B LK I instructi on.
2.4.2
PDP-9 Programming
The DA10 is
assigned device code 228 for the PDP-9. Both data and control to the DA10
pass via the assigned device codes. The PDP-9 receives a PI request when either the FM10 FULL flag
or the TO 10 EMPTY flag is set.
The DA 10 status can be tested with the following instructions.
Instruction
702221
702241
Test
Skip
one if the TOIO EMPTY flag is set.
Ski pone if the TO10 FULL flag is set.
A 702201 instruction will clear the TOIO buffer and the TOlO EMPTY flag.
2-6