Dragonchip DCT-EDP User manual

DCT-EDP Rev3.x User Manual
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DCT-EDP Rev3.x User Manual
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Document Revision 1.3 June, 2019
Dragonchip

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Table of Content
1INTRODUCTION .............................................................................................................. 3
1.1 BOX CONTENTS................................................................................................................. 3
1.2 USEFUL LINKS.................................................................................................................... 3
2HARDWARE..................................................................................................................... 5
2.1 CONTROL INTERFACE......................................................................................................... 5
3DEBUG............................................................................................................................. 6
3.1 HARDWARE SETUP............................................................................................................. 6
3.2 DEBUG PORT PIN ASSIGNMENT ........................................................................................... 7
3.3 PIN ASSIGNMENT ON POD BOARD....................................................................................... 8
3.3.1 DC6688EMT-1TS-POD Rev2.0 board................................................................. 8
3.3.2 DC6288EMT-FT-POD Rev2.0 board................................................................... 8
3.4 SOFTWARE INSTALLATION .................................................................................................. 9
3.4.1 Source Code Template...................................................................................... 10
3.4.2 Keil Project Settings........................................................................................... 10
3.5 VIEW MEMORY CONTENT................................................................................................. 13
3.5.1 DC6688F2SER/F2STR...................................................................................... 13
3.5.2 DC6688FLB ....................................................................................................... 13
3.5.3 DC6688FLX/FLE/FLT/FL96TE .......................................................................... 13
3.5.4 DC6688FSB/FSX/FSE/FST............................................................................... 14
3.5.5 DC6688BT ......................................................................................................... 14
3.5.6 DC6288FT ......................................................................................................... 14
3.6 SUPPLEMENTARY INFORMATION ....................................................................................... 14
3.6.1 Limitation............................................................................................................ 14
3.6.2 Troubeshooting.................................................................................................. 15
4PROGRAMMING............................................................................................................ 16
4.1 SOFTWARE INSTALLATION ................................................................................................ 16
4.2 HARDWARE SETUP........................................................................................................... 16
4.3 DC6688FSX .................................................................................................................. 17
4.4 DC6688FST/FLT/BT ..................................................................................................... 18
4.5 DC6288FT..................................................................................................................... 23
REVISION HISTORY .............................................................................................................. 26

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1 Introduction
This document aims at describing the operation of the tool ‘DCT-EDP Rev3.x’.
DCT-EDP is primarily used for flash programming and debugging software
running on 8051-based System-on-Chip (SoC) devices from Dragonchip.
1.1 Box Contents
1. 1 x DCT-EDP Rev3.x
2. 1 x USB cable
3. 1 x 20-pin flat cable with 2x10 2.54mm connector
4. 1 x 6-pin flat cable with 1x6 2.54 connector
1.2 Useful links
Generally, all the products information is available in our website. Below are
some examples.
1. DC6688
1. Emulator –download latest software installer(Software SLP,
Emulator driver, and Source Code Template in one package) and
user manual
2. Technical website

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2. DC6288
1. Emulator –download latest software installer(Software SLP,
Emulator driver, and Source Code Template in one package) and
user manual
2. Technical website

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2 Hardware
2.1 Control Interface
Front panel have two ports:
1. Debug port
甲、Keil use this port for debug and programming
2. Programming port
甲、Software SLP use this port for programming
Status LED:
Power ON
Debug / Programming
ON/OFF Button:
Power ON/OFF
device
USB Port:
- Connect to PC
Rear panel
Programming Port:
- Connect to IC
Debug Port:
- Connect to IC / POD
Front panel
Debug
Programming
VDD
SL VSS CLK1 PROG CLK2

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3 Debug
3.1 Hardware setup
Debug port provides JTAG and SL interface to IC package with JTAG and SL
pins. Prior to entering debug mode in Keil IDE, the firmware will be
downloaded automatically through this SL interface. JTAG interface is used for
debug communication.
There are two cases of connection depending on whether the package
provided with JTAG pins or not.
1. IC package with JTAG pins
An example is DC6288FT32N3E. In this case, the debug port can connect
directly to the IC.
2. IC package without JTAG pins
Debug
P/N: DCT-EDP Rev3.0
USB
Target system
IC with JTAG
JTAG
+
SL
Keil

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An example is DC6688FL96TT, TSSOP28 without JTAG pin. The DCT-EDP
has to connect to target system through a POD board.
3.2 Debug port pin assignment
Reserved pins must be no connection.
VDD pin, with maximum output current 500mA, should be handled with care to
avoid conflict with the power from self-powered target system. They should not
be connected together unless target system power supplied by VDD pin of
Debug port. If the power of Dragonchip IC is supplied by self-powered target
system, VDD pin of Debug port should be left disconnected.
The following series are compulsory to connect VDD pin of Debug port,
instead of target system.
1. DC6688
2. DC6388
Ribbon cable is strongly recommended for better noise immunity.
Debug
P/N: DCT-EDP Rev3.0
USB
Target system
Keil
POD
Emulator IC
Pin header
JTAG
+
SL
VSS
VSS VSS VSS VSS VSS VSS VSS Reserved
Reserved
PROG
TMS
SL
TDI
TDO
CLK2
TCK
CLK1
Reserved
VDD

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3.3 Pin assignment on POD board
3.3.1 DC6688EMT-1TS-POD Rev2.0 board
This board can support both DC6688FST and DC6688FLT for those packages
without JTAG pins.
3.3.2 DC6288EMT-FT-POD Rev2.0 board
Pin
Description
Pin
Description
1
PD3
2
PD2
3
PC3
4
IRI
5
VDD(3.3V)
6
VSS
7
PC2
8
PD1
9
PC1
10
PD0
11
PC0
12
NC
13
PB7
14
PA0
15
PB6
16
PA1
17
PB5
18
PA2
19
PB4
20
PA3
21
PB3
22
PA4
23
PB2
24
PA5
25
PB1
26
PA6
27
PB0
28
PA7
29
PC5
30
PC4
31
PD6
32
PD5
33
NC
34
PD4
35
NC
36
NC
37
NC
38
NC
39
NC
40
NC

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This board can support both DC6288FT for those packages without JTAG
pins.
3.4 Software Installation
Install the following components in order:
1) Keil PK51 Prof. Developers Kit (recommend v9.55)
It must be installed prior to the following components.
2) Dragonchip ‘DC_TOOL_Rev3.2.1.exe’ or higher which includes the
following items:
a. Source Code Template
b. Emulator Driver
c. Software SLP
Pin
Description
Pin
Description
1
VDD(3.3V)
2
VDD(3.3V)
3
VSS
4
VSS
5
PD3
6
PD2
7
PD1
8
PD0
9
PB7
10
PB6
11
PB5
12
PB4
13
PB3
14
PB2
15
PB1
16
PB0
17
PA7
18
PA6
19
PA5
20
PA4
21
PA3
22
PA2
23
PA1
24
PA0
25
PC3
26
PC4
27
PC1
28
PC2
29
NC
30
PC0

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3.4.1 Source Code Template
This useful tool can help to generate Keil Project Templates for various
Dragonchip 8051-based MCU products with all necessary project settings for
using emulators. User can either start the development with the generated
source code template or compare the project settings with their existing Keil
project.
3.4.2 Keil Project Settings
All necessary Keil Project Settings are listed in this section. The settings might
vary from one part no. to another.
For illustration, DC6688FL96E is taken as an example.
1) Enter ‘Options for Target’
2) ‘Device’Tab - Select DC6688 part from the list.

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3) ‘Target’Tab
Note: The Clock frequency in this page is invalid setting. The setting should be
selected in ‘Programming Setting’instead.
4) ‘Debug’Tab - Follow the settings shown below:

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5) ‘Utilities’ Tab - Follow the settings shown below:
6) Click ‘Settings’ in ‘Utilities’ tab to enter Programming Setting. Input relevant
settings for programming the emulator chip.
Note: Program File does not need to select path.
Select Device
and Clock
Frequency
Select paths of
Firmware files
(All these files
should be put
in the Keil
project folder)
Model (2 bytes) –configure by Custom Info file
Version (2 bytes) –configure by Custom Info file
Checksum (2 bytes) –generate automatically from Program file

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3.5 View Memory Content
3.5.1 DC6688F2SER/F2STR
Memory
Size
Memory
Type
Start
Address
End
Address
Example
Program Flash
Up to 2000B
code
0x0000
0x07CF
C:0x00000
EEPROM
16 bytes
xdata
0x100
0x10F
X:0x0100
Internal SRAM
64 bytes
idata
0x00
0x3F
I:0x00
SFR
128 bytes
data
0x80
0xFF
D:0x80
XFR
256 bytes
xdata
0x00
0xFF
X:0x0000
3.5.2 DC6688FLB
Memory
Size
Memory
Type
Start
Address
End
Address
Example
Program Flash
FL16B
FL32B
Up to 12KB
Up to 24KB
code
code
0x0000
0x0000
0x2FFF
0x5FFF
C:0x0000
C:0x0000
Data Flash
FL16B
FL32B
4KB
8KB
code
code
0x6000
0x6000
0x6FFF
0x7FFF
C:0x6FFF
C:0x6000
Internal SRAM
256 bytes
idata
0x00
0xFF
I:0x00
Expanded SRAM
2KB
xdata
0x0200
0x09FF
X:0x0200
SFR
128 bytes
data
0x80
0xFF
D:0x80
XFR
256 bytes
xdata
0x00
0xFF
X:0x0000
3.5.3 DC6688FLX/FLE/FLT/FL96TE
Memory
Size
Memory
Type
Start
Address
End
Address
Example
Program/Data Flash
FL32T
FLX/FL64T
FLE/FL96T
FL96TE
Up to 31KB
Up to 64KB
Up to 95KB
Up to 95KB
code
0x0000
0x7BFF
0xFFFF
0x17BFF
0x17BFF
C:0x0000
Internal SRAM
256 bytes
idata
0x00
0xFF
I:0x00
Expanded SRAM
FLX/FLE
FL32T
FL64T/FL96T
FL96TE
2KB
1.5KB
3KB
3KB
xdata
0x0200
0x0200
0x8200
0x8200
0x09FF
0x07FF
0x8DFF
0x8DFF
X:0x0200
X:0x0200
X:0x8200
X:0x8200
SFR
128 bytes
data
0x80
0xFF
D:0x80
XFR
256 bytes
xdata
0x00
0xFF
X:0x0000

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3.5.4 DC6688FSB/FSX/FSE/FST
Memory
Size
Memory
Type
Start
Address
End
Address
Example
Program Flash
FSB
FST
FSX/FSE
Up to 30KB
Up to 29.5KB
Up to 62KB
code
0x0000
0x77FF
0x75FF
0xF7FF
C:0x0000
EEPROM
64 bytes
xdata
0x100
0x13F
X:0x0100
Internal SRAM
256 bytes
idata
0x00
0xFF
I:0x00
SFR
128 bytes
data
0x80
0xFF
D:0x80
XFR
256 bytes
xdata
0x00
0xFF
X:0x0000
3.5.5 DC6688BT
Memory
Size
Memory
Type
Start
Address
End
Address
Example
Program/Data Flash
BT32
BT96
Up to 31KB
Up to 95KB
code
0x0000
0x7BFF
0x17BFF
C:0x0000
Internal SRAM
256 bytes
idata
0x00
0xFF
I:0x00
Expanded SRAM
BT32
BT96
1.5KB
3KB
xdata
0x0200
0x8200
0x07FF
0x8DFF
X:0x0200
X:0x8200
SFR
128 bytes
data
0x80
0xFF
D:0x80
XFR
256 bytes
xdata
0x00
0xFF
X:0x0000
3.5.6 DC6288FT
Memory
Size
Memory
Type
Start
Address
End
Address
Example
Program/ Data Flash
Up to 31KB
code
0x00000
0x7BFF
C:0x00000
Internal SRAM
256 bytes
idata
0x00
0xFF
I:0x00
Expanded SRAM
1KB
xdata
0x0200
0x05FF
X:0x0200
1.5KB
xdata
0x0200
0x07FF
X:0x0200
2KB
xdata
0x0200
0x09FF
X:0x0200
SFR
128 bytes
data
0x80
0xFF
D:0x80
XFR
256 bytes
xdata
0x00
0xFF
X:0x0000
3.6 Supplementary Information
3.6.1 Limitation
A) Keil IDE

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DragonICE does not support the following features.
B) Hardware
1) Voltage Supply
甲、The VDD of Debug port is fixed at specified voltage listed below. User
should only do emulation at this voltage level.
Items
VDD/V
DC6288
3.3
DC6388
3.3
DC6688
3.3
DC6688FL32TC
1.8
2) Peripherals
甲、When the emulator is stopped in debugging platform, all the running
peripherals (e.g. timer 2) will still keep running. Hence, the
peripherals will be out of synchronization with the code instruction.
3) Counter A in one shot mode
甲、In one shot mode (CAM = 0), this bit have to reset to 0 every time
before setting CAS = 1.
3.6.2 Troubeshooting
1) Driver Installation
After installing the DragonICE driver, plug the emulator to PC, the driver will
be installed automatically for port connected. In case the PC fails to locate
the driver, select the driver path “C:\WINDOWS\system32” manually.
2) Upgrade Keil Project
When uv2/ uv3 projects are closed, user can choose to upgrade the project
to an uv4 project (*.uvproj).
3) Complie Keil Project
Always compile the code before entering the Keil debugging environment.
Otherwise the emulated flash content may not be updated and the debug
action may not match with the displayed code.
For example,
a) Cursor jumped to a wrong code location in debugger.
b) ‘Step’instruction wrong executed as ‘Free Run’instruction.

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4 Programming
4.1 Software Installation
Software SLP is required on PC to control the hardware. Detail refers to
section 3.4.
4.2 Hardware setup
Programming port provides SL interface to IC. Software SLP will automatically
select this programming port to download firmware to IC.
During debug, this port is disabled automatically.
Warning: Keil IDE must exit debugger mode before using this port via Software
SLP.

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Detail of Software SLP operation can refer to SLP user manual.
4.3 DC6688FSX
The 4-pin connection to the DCT-EDP’s programming port from chip is shown
below. 3-pin connection is not supported.
Programming
P/N: DCT-EDP Rev3.0
USB
IC
SL
VDD
ISPSEL
VSS
XIN
DC6688FSX
PCB
VDD
SL
VSS
CLK1
DCT-EDP

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4MHz of clock frequency on Software SLP below must be selected if the board
resonator is 12MHz.
4.4 DC6688FST/FLT/BT
To do trimming during programming stage, 6 pads are required on PCB to
complete this process.
PD2 1
VSS 2
XOUT 3
XIN 4
ISPSEL 5
PA0 6
MISO/PA1 7
PA2 8
PA3 9
PA4 10
PA5 11
PA6 12
PA7 13
PC4 14
28 PC3
27 VDD
26 PC2/T2
25 PC1/REM/T1
24 PC0/T0/ISPSS
23 PB7
22 PB6/T2EX
21 PB5
20 PB4
19 PB3/TXD1
18 PB2/RXD1
17 PB1/TXD0/MOSI
16 PB0/RXD0/ISPSCK
15 PC5

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DC6688FL32TH6 only requires 4 pads.
DC6688FL32TH6 (QFN16)
VDD
SL/PD0
VSS
PROG
ECLK/PD1
PB6
DC6688FL32TC /
FL32T / FL64T /
FL96T / FST / BT
PCB
VDD
SL
VSS
PROG
CLK1
CLK2
DCT-EDP
VDD
SL
VSS
ECLK
DC6688FL32TH6
PCB
VDD
SL
VSS
CLK1
DCT-EDP
Rev3.1 or

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DC6688FL32TC
12 PB1/INTB/SDA0
11 PB0/INTB/SCL0
10 PA5/INTA/TXD0/SDO/PWM0
9 PA4/INTA/RXD0/SDI
VSS 1
PB3/INTB/SL 2
PB4/INTB/ECLK 3
RSTN 4
16 IRI/IRTX/PC1
15 VDD_IR 14 VDD 13 PB2/INTB/REM
PA0/INTA/T2EX/T24EX
PA1/INTA/SCK/T2
PA2/INTA/SCL1/T1
PA3/INTA/SDA1/T0/PWM1
5 6 7 8
PB0
PB4
PB5
RST
N
IRI
PB1
PC2
VDD
PC1
VSS
PB6
PRO
G
PC0
PA1
PD0
PD1
A
B
C
D
1 2 3 4
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