DAQ system PCI-FRM11 User manual

PCI-FRM11
User Manual
Version 1.2
ⓒ2005 DAQ SYSTEM Co., Ltd. All rights reserved.
Microsoft®is a registered trademark; Windows®, Windows NT®, Windows XP®, Windows 7®, Windows 8®, Windows 10®
All other trademarks or intellectual property mentioned herein belongs to their respective owners.
Information furnished by DAQ SYSTEM is believed to be accurate and reliable, However, no responsibility is assumed by DAQ SYSTEM for its use, nor
for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under
any patent or copyrights of DAQ SYSTEM.
The information in this document is subject to change without notice and no part of this document may be copied or reproduced without the prior
written consent.

PCI-FRM11 User‟s Manual
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Contents
1. Introduction -------------------------------------------------------------------------- 3
1-1 Product Features ------------------------------------------------------------------------- 4
1-2 Product Application ------------------------------------------------------------------------- 5
2. PCI-FRM11 Board Function
2-1 Board Block Diagram ------------------------------------------------------------------------ 6
2-2 Camera Link ------------------------------------------------------------------------ 7
2-3 Camera Link Cable & Connector ----------------------------------------------------------- 9
2-4 Camera Link & PCI-FRM11 ---------------------------------------------------------- 10
3. PCI-FRM11 Board Description
3-1 PCI-FRM11 Board Layout ------------------------------------------------------------------ 12
3-2 Device Features ------------------------------------------------------------------ 13
3-3 Connector Pin out ---------------------------------------------------------- 14
3-3-1 J1(MDR) Connector ----------------------------------------------------------------- 15
3-3-2 J2 Connector ------------------------------------------------------------------ 17
3-3-3 SW1 Switch --------------------------------------------------------------------- 19
3-3-4 J4 Connector ---------------------------------------------------------------------- 19
3-3-5 JP3 Connector ---------------------------------------------------------------------- 19
3-4 Digital Input/Output
3-4-1 Photo Coupler Input -------------------------------------------------------------- 20
3-4-2 Photo Coupler Output ------------------------------------------------------------- 21
4. Installation
4-1 Product Contents ----------------------------------------------------------------------- 22
4-2 Installation Process ------------------------------------------------------------------------ 22

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5. Sample Program
5-1 FrmTest Program ---------------------------------------------------------------- 26
5-1-1 Image Frame Function ------------------------------------------------------ 27
5-1-2 UART Function ------------------------------------------------------------------- 27
5-1-3 DIO Function ---------------------------------------------------------------- 28
5-2 FrameView Program ----------------------------------------------------------------- 29
6. Test
6-1 Image Frame Input Test ------------------------------------------------------------------ 31
6-2 UART Tx/Rx Test -------------------------------------------------------------------- 32
6-3 DIO Test ------------------------------------------------------------------- 32
Appendix
A-1 Board Size --------------------------------------------------------------------- 33
A-2 Repair Regulations --------------------------------------------------------------------- 34
References ------------------------------------------------------------------------ 35

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1. Introduction
PCI-FRM11 is a board that transmits the captured image frame to the PC through the PCI interface
method in conjunction with the Camera-link standard camera.
The operation of the board is controlled by the program API, and the figure below shows the
interlocking operation of the board.
[Figure 1-1. PCI-FRM11 Board Usage]
As shown in [Figure 1-1], PCI-FRM11 is installed in the PCI slot in the PC and receives from the
camera through the image frame through the Camera-Link standard interface. It is responsible for
transmitting the received data to the application program through the PCI interface.

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1-1 Product Features
Items
Description
Remark
Hardware
PC Interface
PCI Express 1x
Operation Power
PC Power
+3.3V (Max 1.1A)
+12V (Max 1A).
Video Interface
Base Camera Link
Feature
Area Scan Camera
Pixel Clock : 20 ~ 85MHz
External I/O
4-Ch. Digital In
8-Ch Digital Out
Digital Input :
Voltage Range : 9 ~ 24V
Current Range : 3.75mA (For 9V)
~ 10mA (For 24V)
Digital Output :
Voltage Range : ~ 7V
Current Range : Within 10mA
On-board Memory
Communication
UART(Data bit 8, 1 start, 1 stop, No
parity, 9600/19200/38400/57600
/115200bps)
Simultaneous use of
boards
Max. 4
Software
OS
Windows 2000/XP/7/8/10 (32/64bit)
API
Windows Client DLL API
Development
Support
Sample Program
VC++
Environmental conditions
Operating temperature
range
0 ~ 60℃
Storage temperature
range
-20 ~ 80℃
Humidity range
5 ~ 95%
Non-condensing
Board size
120.8mm X 68mm
PCB Board Size

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1-2 Product Applications
Image recognition (Pattern, particle, etc.)
Inspection equipment (Sensor, Semiconductor, Device etc.)
Black and White, Color Image Display
Medical Image Capture (X-ray, Supersonic etc.)

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2. PCI-FRM11 Board Function
2-1 Board Block Diagram
As shown in the figure below, in the case of PCI-FRM11, FPGA Core Logic is in charge of
overall control. Main functions include Frame Data reception, UART data transmission/reception
for this, Camera Control signal and external trigger.
These functions are performed using API in PC through PCI interface.
PCI Target
/ Master
PCI BUS
Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00 –0x5F)
Reserved
(0x70 –0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCI-FRM11 INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0 –0xFF)
[Figure 2-1. PCI-FRM11 FPGA Block Diagram]
The FPGA core logic is programmed using JTAG, and the logic program is saved in FPGA
Program Logic and loaded when power is applied.

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2-2 Camera Link
Camera Link is a communication interface developed for use in vision applications. In the past,
we used proprietary connectors and cables between camera makers and frame grabber makers.
This caused a lot of confusion and cost increase for users. In order to resolve this confusion,
increasing data rate, and confusion in data transmission, the specifications of the Camera Link
interface are the specifications of cable or connector assembly, transmission speed and It was
made with regulations such as transmission method.
Many digital video solutions today use Low Voltage Differential Signal (LVDS) communication
defined by RS-644. RS-644 LVDS has become the Camera Link standard by improving the existing
RS-422 method, which had inconvenient cables and limited transmission speed. LVDS can transmit
data at high speed by using a differential signal with a low voltage swing. Compared to the
existing single-ended signal using one line, the differential signal transmits the signal using two
complementary lines. This transmission structure has the characteristics of large-scale common-
phase voltage rejection, low power consumption, and excellent noise immunity, which is
impossible with single-ended systems that only reference ground for data transmission.
An advanced LVDS technology for the transmission of digital data is a Channel Link. The channel
link can transmit parallel-to-serial and serial-to-parallel at 2.38 Gbps. Referring to [Figure 2-3], the
transmitter converts 28-bit CMOS/TTL data into 4 LVDS data streams. The converted signal is
transmitted to the MDR cable according to the Transmit Clock, and the opposite receiver converts
these four LVDS data into a 28-bit CMOS/TTL parallel signal according to the Receive Clock. This
channel link technology is being used as a low-cost chipset that is easy to learn and portable, so
that it can be used immediately.
Camera Link interface includes Base Configuration, Medium Configuration, and Full
Configuration. Base Configuration uses four RS-644 LVDS pairs for transmitter/receiver and camera
control as shown in [Figure 2-3], and uses two RS-644 LVDS pairs for communication between
camera and frame grabber. The data transmitted serially through the 26-Pin MDR Cable is
changed to 28-bit parallel image data at the Receive end of the frame grabber and used.

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[Figure 2-2. Base Camera Link Block Diagram]

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2-3 Camera Link Cable & Connector
Camera Link The connection between the camera and the PCI-FRM11 board uses a 26 Pin MDR
(Mini D Ribbon) cable. The camera link cable consists of a twin-axial shielded cable and two MDR
26-male plugs. [Figure 2-3] below is a commonly used camera link cable.
[Figure 2-4] is a 26-Pin Male MDR Connecter located at both ends of the cable, and [Figure
2-5] is a 26-Pin Female MDR Connector, located at the camera or frame grabber. As shown in the
figure, the pin numbers are cross-connected, so that the transmitter and receiver terminals of the
camera and frame grabber signal lines are cross-connected.
[Figure 2-3. MDR-26 Camera Link Straight Cable]
[Figure 2-4. MDR-26 Cable Pin Map]
[Figure 2-5. MDR-26 Connector Pin Map(Opposite Connector)]

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2-4 Camera Link & PCI-FRM11
PCI-FRM11 supports Camera Link Base Configuration. Base Configuration consists of 4 LVDS
signal lines serializing 28-bit parallel signals including 24 data bits and 4 enable signals Frame
Valid, Line Valid, Data Valid, and a spare, and 1 LVDS signal line to synchronize with the camera. ,
Asynchronous serial communication including 4 CC (Camera Control) signals and 2 LVDS lines for
asynchronous serial communication to communicate with the camera are transmitted through
MDR cables.
The transmitted signal deserilizes 4 video LVDS serial signals into 28-bit parallel video signals and
control signals (Frame Valid, Line Valid, Data Valid, and a spare) through the Channel Link chip in
PCI-FRM11. In addition, a clock signal is made with one LVDS to synchronize the signal between
the camera and PCIe-FRM11, and the remaining cameras control signals and communication
signals are converted into general TTL signal levels and used.
CCx+
CCx-
Camera Control
The figure shows the Camera Control output circuit that can send the control signal from the
PCI-FRM11 board to the Camera through the Camera-link cable. A total of 4 digital outputs are
output through the differential method. Each output is mapped to a digital output and becomes
an output. Each bit position is shown in [Figure 2-6] below.
CC1+
CC1-
CC_D0
CC2+
CC2-
CC_D1
CC3+
CC3-
CC_D2
CC4+
CC4-
CC_D3
[Figure 2-6. Camera Control LVDS Digital Output Circuit]

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The figure below shows the circuit that uses the serial input signal input through the Camera-
link cable as a general input on the PCI-FRM11 board.
[Figure 2-7. Serial Communication LVDS Digital Output Circuit]
PCI-FRM11 supports Base Configuration including the following bit allocation.
1, 2 ,or 3 Pixels (or Taps) at 8 Bits
1 or 2 Pixels (or Taps) at 10 Bits
1 or 2 Pixels (or Taps) at 12 Bits
1 Pixel (or Tap) at 14 Bits
1 Pixel (or Tap) at 16 Bits
24 Bits RGB

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3. PCI-FRM11 Board Description
Each important board function is briefly described. For detailed function information, please refer to
the parts specification.
3-1 PCI-FRM11 Board Layout
[Figure 3-1. PCI-FRM11 Layout]
The board has 3 LEDs with indication functions, and the description of each is as follows.
LED2 : Lights up when an image frame is received.
LED3 : Lights up when frame data is being transmitted.
LED1 : Lights up when the board finishes configuration and ready for operation.

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3-2 Device Features
(1) FPGA : U5
All of the board functions are controlled by the Logic program of the FPGA.
(2) LVDS : U1
Receive an image frame.
Transmits/receives UART signals.
Outputs Camera Control Digital Output.
(3) Regulator : U7
It supplies the power used by the board.
(4) Level Shifter : U3, U6
It protects the circuit by converting the interface of higher voltage than 3.3V CMOS Logic to
3.3V logic level.
(5) SW1
Set the board number.

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3-3 Connector Pin-out
This section describes connectors and jumpers used in PCI-FRM11. There is an MDR 26pin
connector for the Camera Link connection.
[Figure 3-2] shows the bracket that interfaces with the board and the outside, and the
connection connector.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
26
25
[Figure 3-2. PCI-FRM11 Front View]

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3-3-1 J1 (MDR26) Connector
The figure below shows the pin map of the J1 connector of the board used when using
the Base Configuration Camera Link. All pin specifications are input/output based on the
Camera Link standard, so please refer to the Camera Link standard document for details.
3
10
9
8
7
6
1
2
5
4
19
18
17
16
15
14
13
12
1124
23
22
21
20
Inner shield Inner shield
26
25
SerTFG-
SerTC+
Xclk-
X3-
X2-
X1-
X0-
Inner shield
Frame Grabber
SerTFG+
SerTC-
Xclk+
X3+
X2+
X1+
X0+
Inner shield
CC4-
CC3+
CC2-
CC1+
CC4+
CC3-
CC2+
CC1-
[Figure 3-3. J1 Connector Pin-out]

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[Table 1. J1 Connector]
Pin No
Name
Description
Remark
1
Inner Shield
Cable shield
2
CC4-
Camera Control output 4-
3
CC3+
Camera Control output 3+
4
CC2--
Camera Control output 2-
5
CC1+
Camera Control output 1+
6
SerTFG+
Serial to Frame grabber +
7
SerTC-
Serial to Camera-
8
X3+
Camera link LVDS receive data3 +
9
Xclk+
Camera link LVDS receive clock +
10
X2+
Camera link LVDS receive data2 +
11
X1+
Camera link LVDS receive data1 +
12
X0+
Camera link LVDS receive data0 +
13
Inner Shield
14
Inner Shield
15
CC4+
Camera Control output 4+
16
CC3-
Camera Control output 3-
17
CC2+
Camera Control output 2+
18
CC1-
Camera Control output 1-
19
SerTFG-
Serial to Frame grabber-
20
SerTC+
Serial to Camera+
21
X3-
Camera link LVDS receive data3-
22
Xclk-
Camera link LVDS receive clock-
23
X2-
Camera link LVDS receive data2-
24
X1-
Camera link LVDS receive data1-
25
X0-
Camera link LVDS receive data0-
26
Inner Shield
(Note) For more information, refer to Camera Link Standard Specification.

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3-3-2 J2 Connector
The PCI-FRM11 board is an external digital input/output device, and 8 digital inputs and 8
digital outputs isolated by a photo-coupler can be used through the J5 connector. The
photo-coupler circuit is shown below.
INx
IN_COM
DINx
2.4K
3.3V
< Photo coupler Input>
OUTx
OUT_COM DOUTx
22
3.3V
<Photo coupler Output>
[Figure 3-4. Photo-coupler Input/Output Circuit]
The pin map of the connector is shown in the figure below.
1
2
3
4
95
6 8
7
10
11
12
13
14 20
19
18
17
16
15 21
22
23
24
25
26
[Figure 3-5. J2 2x13, 2.53 pitch pin-out]
[Table 2. J2 Connector]
Pin No
Name
Description
Remark
1
DIN0
Input 0
2
DIN4
Input 4
3
DIN1
Input 1
4
DIN5
Input 5
5
DIN2
Input 2

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6
DIN6
Input 6
7
DIN3
Input 3
8
DIN7
Input 7
9
DIN_COM
Input Common
10
DIN_COM
Input Common
11
DOUT0
Output 0
12
DOUT4
Output 4
13
DOUT1
Output 1
14
DOUT5
Output 5
15
DOUT2
Output 2
16
DOUT6
Output 6
17
DOUT3
Output 3
18
DOUT7
Output 7
19
DOUT_COM
Output Common
20
DOUT_COM
Output Common
21
N.C
Not Connect
22
N.C
Not Connect
23
GND
Ground
24
GND
Ground
25
+3.3V
3.3V Power
26
+3.3V
3.3V Power

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3-3-3 SW1 Switch
PCI-FRM11 board is designed to use up to 4 PCIe-FRM11 boards simultaneously in one
system (PC). Each board classification can be set through the 4-pin DIP switch in the board.
1
ON
OFF
2
[Figure 3-6. SW1 Switch (Top View)]
[Table 3. SW1 PIN-OUT]
1
2
Description
OFF
OFF
Board No. 0
ON
OFF
Board No. 1
OFF
ON
Board No. 2
ON
ON
Board No. 3
3-3-4 J4 Connector
It is a 3.3V external DC power connector. This is the power used when installing the FPGA
and is not normally used.
3-3-5 JP3 Connector
JP3 is a JTAG (Joint Test Action Group) connector and is used to update the FPGA program
on the board. Do not use when operating the board normally.