Dynamic Engineering IP-429-II User manual

DYNAMIC ENGINEERING
150 DuBois St Suite C, Santa Cruz, CA 95060
831-457-8891 Fax [phone]
Web Page http://www.dyneng.com
E-Mail [email protected]
Est. 1988
User Manual
IP-429-II
ARINC 429 Interface
IP Module
Revision A1
Corresponding Hardware: 10-2007-0501/2

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IP429-II
ARINC 429 Interface
IP Module
Dynamic Engineering
150 DuBois St Suite C
Santa Cruz, CA 95060
831- 457-8891
831-457-4793 FAX
This document contains information of proprietary interest
to Dynamic Engineering. It has been supplied in
confidence and the recipient, by accepting this material,
agrees that the subject matter will not be copied or
reproduced, in whole or in part, nor its contents revealed in
any manner or to any person except to meet the purpose
for which it was delivered.
Dynamic Engineering has made every effort to ensure that
this manual is accurate and complete. Still, the company
reserves the right to make improvements or changes in the
product described in this document at any time and without
notice. Furthermore, Dynamic Engineering assumes no
liability arising out of the application or use of the device
described herein.
The electronic equipment described herein generates,
uses, and can radiate radio frequency energy. Operation of
this equipment in a residential area is likely to cause radio
interference, in which case the user, at his own expense,
will be required to take whatever measures may be
required to correct the interference.
Dynamic Engineering’s products are not authorized for use
as critical components in life support devices or systems
without the express written approval of the president of
Dynamic Engineering.
This product has been designed to operate with IP Module
carriers and compatible user-provided equipment.
Connection of incompatible hardware is likely to cause
serious damage.
©1998-2015 by Dynamic Engineering.
IndustryPack is a registered trademark of GreenSpring Computers Inc..
Other trademarks and registered trademarks are owned by their
respective manufactures.
Manual Revision A2. Revised November 3rd, 2015

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Table of Contents
PRODUCT DESCRIPTION 6
THEORY OF OPERATION 8
ADDRESS MAP 10
PROGRAMMING 12
Register Definitions 13
IP429II_BASE_REG0 13
IP429II_BASE_REG1 14
IP429II_BASE_REG2 15
IP429II_BASE_REG3 15
IP429II_VECTOR 16
IP429II_STATUS0 17
IP429II_STATUS1 18
IP429II_Parallel 19
IP429_Encoder/Decoder 20
IP429_CHx_CNTL21
IP429_CHXX_TS 23
Interrupts 24
ID PROM 25
LOOP-BACK 26
IP MODULE LOGIC INTERFACE PIN ASSIGNMENT 27
IP MODULE IO INTERFACE PIN ASSIGNMENT 28
APPLICATIONS GUIDE 29
Interfacing 29
Construction and Reliability 30

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Thermal Considerations 31
WARRANTY AND REPAIR 31
Service Policy 31
Out of Warranty Repairs 31
For Service Contact: 32
SPECIFICATIONS 33
ORDER INFORMATION 34

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List of Figures
FIGURE 1 IP-429 INTERNAL ADDRESS MAP 11
FIGURE 2 IP-429 CONTROL REGISTER 0 BIT MAP 13
FIGURE 3 IP-429 CONTROL REGISTER 1 BIT MAP 14
FIGURE 4 IP-429 CONTROL REGISTER 2 BIT MAP 15
FIGURE 5 IP-429 CONTROL REGISTER 3 BIT MAP 15
FIGURE 6 IP-429 STATUS REGISTER 0 BIT MAP 17
FIGURE 7 IP-429 STATUS REGISTER 1 BIT MAP 18
FIGURE 8 IP-429 CONTROL REGISTER 0 BIT MAP 19
FIGURE 9 IP-429 3282 CONTROL REGISTER BIT MAP 21
FIGURE 10 IP-429 ID PROM STANDARD 25
FIGURE 11 IP-429 LOGIC INTERFACE 27
FIGURE 12 IP-429 IO INTERFACE 28

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Product Description
ARINC 429 is a versatile standardized bus interface. ARINC 429 is robust featuring
Manchester encoding and enough voltage swing to provide excellent noise immunity
and reasonable throughput rates. ARINC 429 is the interface of choice for critical
applications; for example aircraft instrumentation and control. There are many devices
supporting the 429 bus - printers, instrumentation, sensors and more.
IP-429-II makes it easy to gain access to the ARINC 429 bus. Just connect; program a
few registers and use like an IO device. Reference software, schematics and
debugging aides are available in the Engineering Kit.
IP-429-II is an upgrade to the original IP-429 design. Dynamic Engineering designed
the original IP-429 in 1998 and both manufactured and licensed the design.
GreenSpring Computers, and later SBS manufactured the board under their licensing
agreements.
The base version of the upgraded design uses the same address and bit maps. The
design is enhanced with the Time Trigger / Time Stamp capability now being included
on all versions and moved into the IO space. The IO connector has the same signal
definitions. The revision 2 and later boards have FLASH memory instead of the PROM
and the JTAG signals available on the IO connector.
Please refer to the web page for updated versions with enhanced features. The new
versions will have different IDPROM definitions to allow differentiation in your system.
Previously purchased IP-429-II rev B and later boards can be updated to make use of
the new features.
IP-429-II is capable of providing up to 8 Receive and 4 Transmit channels of ARINC 429
compatible IO in one IP position. Each of the eight (8) receive channels has a 32 bit
Time Tag register associated with it. The Time Tag generator operates with a 1 uS
resolution. When each new message is received the Data Ready signal from the 429
decoder device is used to trigger the time stamp for that channel.
In addition to the ARINC 429 capability, a parallel IO port is provided to allow custom
formats and specialized status to be implemented. The hardware is capable of other
formats including 571, 575, and 706 with software set-up changes.
IP-429 supports both the High and Low speed standards for data transmission. A
programmable register allows each TX channel to operate at either rate. Each
transmitter is supported by an 8 deep 32 bit wide FIFO.

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Transmission and Reception can be done on an interrupt or polled basis. The interrupts
are individually maskable. The vector is user programmable by a read/write register.
The interrupt occurs on IntReq0.
The IP interface is 8 and 32 MHz. capable for efficient programming and data transfer.
All configuration registers support read and write operations for maximum software
convenience. Word and byte operations are supported (please refer to the memory
map).
IP-429-II conforms to the VITA standard. This guarantees compatibility with multiple IP
Carrier boards. Because the IP may be mounted on different form factors, while
maintaining plug and software compatibility, system prototyping may be done on one IP
Carrier board, with final system implementation on a different one. Dynamic
Engineering carrier boards have Drivers available for Windows® and Linux. IP-429-II is
supported with a Windows driver included with the purchase of the card. This manual
contains enough data to write your own driver should you prefer to take that approach.
Using IP-429 and a PCI3IP or PCI5IP creates a PCI-429 capability. For example using
an IP-429-4 and a PCI3IP makes a PCI slot compatible ARINC 429 solution with 8
receivers and 4 transmitters. Adding more IP’s can add more channels up to 40
receivers and 20 transmitters in the PCI slot [on a PCI5IP]. Other options are available
for PCIe, cPCI [3U and 6U] and PC104p. Coming soon VPX, cPCIe, and PCIe104
carriers.

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Theory of Operation
IP-429-II is designed for the purpose of transferring data from one point to another with
the ARINC-429 protocol.
IP-429-II features a Xilinx FPGA and industry standard 3282 compatible ARINC 429
receiver / transmitter devices. The FPGA contains the IP interface and control required
for the 429 devices. Each 3282 provides two Receiver channels and one partial
Transmit channel. A separate device provides the “drive” circuitry for the transmit
channel. The ‘3282 data sheet is available on-line from the IP-429 webpage.
IP-429-II is a part of the IP Module family of I/O products. It meets the IP Module VITA
Standard. Contact VITA for a copy of this specification. It is assumed that the reader is
at least casually familiar with this document and logic design. In standard configuration
it is a Type II mechanical with passive low profile components on the back of the board
and one slot wide.
The bus interface to the host CPU is controlled by a logic block within the Xilinx device
that contains the decoding and timing elements required to interface to the IP bus
interface. The timing is referenced to the 8 or 32 MHz IP logic clock. The IP responds to
the ID, INT, MEM and IO selects. The FPGA design requires wait states for read or
write cycles to any address. Hold cycles are supported as required by the host
processor. Data remains enabled during a read until the host removes the SEL line.
Local timing terminates a write cycle prior to SEL being de-asserted.
The interface to the 429 encoder/decoder modules is operated at 100 MHz. to allow for
precise timing with as little wasted time as possible. The IO space decodes for the write
and read functions are set based on the IP clock rate. The state-machine detects the
request and handles the data transfer to/from the encoder/decoder. The number of
wait-states will depend on the IP clock rate in use. At 8 Mhz the timing of the
encoder/decoder is similar which will lead to fewer wait states. At 32 Mhz the IP clock is
faster than the read or write timing to the encoder/decoder leading to more wait-states.
The overall time will be shorter with the 32 MHz clock. If available it [32 MHz] is
recommended for use.
Before transmitting or receiving data IP-429-II requires register programming to select
data rates and formats as well as system clock speed, interrupt masking etc.. Each of
the programmable registers is described in the programming section. Once IP-429-II
has been set-up for operation in your environment, data can be transferred.
To transmit, data is loaded into the transmitter FIFO within the channel of interest and
the transmission enabled. If programmed, an interrupt will alert the host that the data

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has been transferred. If preferred, the TX status can be polled and the transmitter
status determined. Each transmitter channel is independent of the other transmitter
channels.
To receive data another transmitter in the system sends data on the bus, which is
connected, to the IP-429. There are up to eight receive channels per IP-429-II and
each channel can be connected to a different ARINC 429 bus. The Receiver channels
are controlled in pairs for the clock speed. When data is received, an interrupt can be
generated to the host. The interrupt to the host is the ‘OR’ of the interrupt requests from
all of the channels. Each channel has an interrupt mask. There is a status register to
allow the host to determine the cause of the interrupt and to set priorities for responding
to the interrupt(s). The interface can be operated in a polled mode by reading the status
register.
If the system needs to know when data was received, Time Tagging can be useful. IP-
429-II supports Time Tagging by providing a 32 bit counter, which operates at 1 MHz to
provide a 1 uS Time Tag count. When the interrupt from any of the receive channels is
asserted the current “time” is registered into one of eight Time Tag registers. The
software can access the registers to read the count. The time should be read before
another interrupt is generated on that channel or the time will be updated for the new
interrupt. The counter is resettable to allow synchronization with a system timer. With
32 bits, the counter will roll over after ~71.58 minutes.
The Time Tag registers are internal to the Xilinx and are loaded automatically. The
registers are aligned to allow reading as longwords – using the automatic double reads
built into Dynamic Engineering carriers.

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Address Map
IO Space
Function Offset Width Type
// IP 429 relative addresses //
#define IP429II_BASE_REG0 0x00 // byte on word boundary
#define IP429II_BASE_REG1 0x02 // byte on word boundary
#define IP429II_BASE_REG2 0x04 // byte on word boundary
#define IP429II_BASE_REG3 0x06 // byte on word boundary
#define IP428II_VECTOR 0x08 // byte on word boundary
#define IP429II_STATUS0 0x0a // byte on word boundary
#define IP429II_STATUS1 0x0c // byte on word boundary
#define IP429II_PARALLEL 0x0e // byte on word boundary
#define IP429II_INFO 0x10 // Driver info register word
#define IP429II_TS_DEV1_CH1_LWR 0x14 Time Tag Device 1 receiver 1 D15..D0 read only
#define IP429II_TS_DEV1_CH1_UPR 0x16 Time Tag Device 1 receiver 1 D31..D16 read only
#define IP429II_TS_DEV1_CH2_LWR 0x18 Time Tag Device 1 receiver 2 D15..D0 read only
#define IP429II_TS_DEV1_CH2_UPR 0x1A Time Tag Device 1 receiver 2 D31..D16 read only
#define IP429II_TS_DEV2_CH1_LWR 0x1C Time Tag Device 2 receiver 1 D15..D0 read only
#define IP429II_TS_DEV2_CH1_UPR 0x1E Time Tag Device 2 receiver 1 D31..D16 read only
#define IP429II_TS_DEV2_CH2_LWR 0x20 Time Tag Device 2 receiver 2 D15..D0 read only
#define IP429II_TS_DEV2_CH2_UPR 0x22 Time Tag Device 2 receiver 2 D31..D16 read only
#define IP429II_TS_DEV3_CH1_LWR 0x24 Time Tag Device 3 receiver 1 D15..D0 read only
#define IP429II_TS_DEV3_CH1_UPR 0x26 Time Tag Device 3 receiver 1 D31..D16 read only
#define IP429II_TS_DEV3_CH2_LWR 0x28 Time Tag Device 3 receiver 2 D15..D0 read only
#define IP429II_TS_DEV3_CH2_UPR 0x2A Time Tag Device 3 receiver 2 D31..D16 read only
#define IP429II_TS_DEV4_CH1_LWR 0x2C Time Tag Device 4 receiver 1 D15..D0 read only
#define IP429II_TS_DEV4_CH1_UPR 0x2E Time Tag Device 4 receiver 1 D31..D16 read only
#define IP429II_TS_DEV4_CH2_LWR 0x30 Time Tag Device 4 receiver 2 D15..D0 read only
#define IP429II_TS_DEV4_CH2_UPR 0x32 Time Tag Device 4 receiver 2 D31..D16 read only
#define IP429II_OE0_DEV1_L 0x40 // read from Device 1 port 1 lower half
#define IP429II_OE0_DEV1_U 0x42 // read from Device 1 port 1 upper half
#define IP429II_OE1_DEV1_L 0x44 // read from Device 1 port 2 lower half
#define IP429II_OE1_DEV1_U 0x46 // read from Device 1 port 2 upper half
#define IP429II_LD1_DEV1 0x48 // write to Device 1 TX port lower half
#define IP429II_LD2_DEV1 0x4a // write to Device 1 TX port upper half
#define IP429II_CNTL_DEV1 0x4c // write to Device 1 control word
#define IP429II_OE0_DEV2_L 0x50 // read from Device 2 port 1 lower half
#define IP429II_OE0_DEV2_U 0x52 // read from Device 2 port 1 upper half
#define IP429II_OE1_DEV2_L 0x54 // read from Device 2 port 2 lower half

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#define IP429II_OE1_DEV2_U 0x56 // read from Device 2 port 2 upper half
#define IP429II_LD1_DEV2 0x58 // write to Device 2 TX port lower half
#define IP429II_LD2_DEV2 0x5a // write to Device 2 TX port upper half
#define IP429II_CNTL_DEV2 0x5c // write to Device 2 control word
#define IP429II_OE0_DEV3_L 0x60 // read from Device 3 port 1 lower half
#define IP429II_OE0_DEV3_U 0x62 // read from Device 3 port 1 upper half
#define IP429II_OE1_DEV3_L 0x64 // read from Device 3 port 2 lower half
#define IP429II_OE1_DEV3_U 0x66 // read from Device 3 port 2 upper half
#define IP429II_LD1_DEV3 0x68 // write to Device 3 TX port lower half
#define IP429II_LD2_DEV3 0x6a // write to Device 3 TX port upper half
#define IP429II_CNTL_DEV3 0x6c // write to Device 3 control word
#define IP429II_OE0_DEV4_L 0x70 // read from Device 4 port 1 lower half
#define IP429II_OE0_DEV4_U 0x72 // read from Device 4 port 1 upper half
#define IP429II_OE1_DEV4_L 0x74 // read from Device 4 port 2 lower half
#define IP429II_OE1_DEV4_U 0x76 // read from Device 4 port 2 upper half
#define IP429II_LD1_DEV4 0x78 // write to Device 4 TX port lower half
#define IP429II_LD2_DEV4 0x7a // write to Device 4 TX port upper half
#define IP429II_CNTL_DEV4 0x7c // write to Device 4 control word
FIGURE 1 IP-429 INTERNAL ADDRESS MAP
The address map provided is for the local decoding performed within the IP-429. The
addresses are all offsets from a base address. The carrier board where the IP is
installed provides the base address and controls the “naming of the bytes”. We refer to
the bytes following Motorola conventions i.e. upper is D15-D8 and lower is D7-D0.
When byte wide data is located on the lower byte then an odd address results or the
use of a word access using only the lower byte of data. We prefer the word oriented
approach because it is more consistent across platforms.
Please note the double wide registers for TX and RX data functions are located on LW
boundaries allowing for 32 bit read or write actions with carriers that support automatic
32 ó 16 conversion. All Dynamic Engineering carriers have this feature.
IP-429-II can have up to 4 of the encoder/decoder “chips” installed. The –1 version has
device 1 installed , -2 has both device 0 and device 1 and so forth. The names for the
decodes above have the chip number followed by the port within the chip and the
function. For example IP429II_OE1_DEV3_U is the upper half data read from chip 3
port 1. The OE, LD, CNTL etc. can be used as a guide to the IC function name when
comparing with the schematic or datasheet.

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Programming
Programming the IP-429 requires only the ability to read and write data in the host's I/O
and Memory spaces. The base address is determined by the IP Carrier board. This
documentation refers to the address where the IO space for the slot that the IP is
installed in as the base address.
A typical sequence would be to first write to the vector register with the desired interrupt
vector. For example $40 is a valid user vector for the Motorola 680x0 family. Please
note that most carrier boards do not use the interrupt vector. VME is about the only
system still using vectored interrupts. The interrupt service routine should be loaded
and the mask should be set. For auto-vectored systems – PCI etc. this step can be
skipped.
Refer to the Theory of Operation section above and the Interrupts section below for
more information regarding the exact sequencing and interrupt definitions.
A local oscillator provides a 50 MHz reference. The reference is used to generate a 1
MHz. clock used for the time-stamp and encoder/decoder functions. The clock is
doubled [100 MHz.] to use as a reference for the IO state-machine. No programming
required for this functionality.
Dynamic Engineering carriers come with Windows and other drivers. The drivers are
structured to detect the carrier and the installed IP modules. The carrier driver will
automatically load the appropriate IP module driver if available and the generic driver for
that IP position if the installed IP is not in the list of supported devices. The carrier has
a DIP switch which can be used to differentiate between carrier boards when more than
one are in the same system. The IP’s are also named to allow for complete control over
the addressing path in systems where the address is not known until run-time [PCI,
PCIe etc].
Dynamic Engineering drivers take care of the system level interaction and provide an
easy to use platform to write your user level software. The driver comes with “Userap”
which is an open source collection of tests using the driver to test the card in question.
Userap is a great reference for loop-back testing and other quick start code writing.
The use of Dynamic Engineering drivers is highly recommended. The details that
follow are for those who just need to know or need to implement a driver for another
carrier or unsupported OS.
http://www.dyneng.com/drivers.html has a more complete summary of driver operation.

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Register Definitions
IP429II_BASE_REG0
[$00 429 Control Register Port read/write
CONTROL REGISTER 0
DATA BIT DESCRIPTION
7 Send4 0 = tx disabled, 1 = enabled ch3
6 Send3 0 = tx disabled, 1 = enabled ch2
5 Send2 0 = tx disabled, 1 = enabled ch1
4 Send1 0 = tx disabled, 1 = enabled ch0
3 spare
2 CLR_CNT 0 = run, 1 = clear
1 INT_SET 0 = no interrupt, 1 = force interrupt
0 Clock Speed 0 = 8Mhz, 1 = 32 MHz.
FIGURE 2 IP-429 CONTROL REGISTER 0 BIT MAP
The Clock Speed bit is used to select either the 8 MHz or 32 MHz. IP Clock rate. The
Clock Speed selection defaults to 8 MHz. = 0. The selection should match the IP
reference clock rate to insure proper operation. This is a legacy bit retained for software
commonality but has no effect on operation.
INT_SET is used to force an interrupt condition to occur. This control bit is useful for
SW development and HW testing. Default to no interrupt = 0, force interrupt with 1.
CLR_CNT is used to reset the 32 bit Time Stamp counter. The clear bit is written with a
1 and then released with a 0 to set the counter to a 0 value and restore operation.
Please refer to the Time Stamp registers for more information.
The Send bits are used to enable the transmitter sections to send when ready. The
transmitters are ready to send when there is data in the output FIFO. The Sendx bit
should be held in the disabled state if more than one word is to be placed into the output
FIFO. If only one word is to be sent each time the Sendx bit can be left enabled and the
data will automatically be transferred when LD2 is accessed with the second write.

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IP429II_BASE_REG1
$02 429 Control Register Port read/write
CONTROL REGISTER 1
DATA BIT DESCRIPTION
7 /RESET4 reset, 1 = enabled
6 /RESET3
5 /RESET2
4 /RESET1
3 /DBCEN4 1 = force parity, 0 = normal
2 /DBCEN3
1 /DBCEN2
0 /DBCEN1
FIGURE 3 IP-429 CONTROL REGISTER 1 BIT MAP
/DBCENx is used to force Parity to be inserted into the data stream. This bit is normally
left programmed to 0. There is another control bit within the -3282 that also controls
Parity along with even or odd sense. It is recommended to use the 3282 control bit.
Default is 0.
/RESETx is used to reset the 3282 associated with each channel. The channel should
be reset when the 3282 control register is written to. [write only port]. Default is reset
[0]. 1 = normal operation. Reset should be asserted for 200 nS minimum.
The TX FIFO, bit counters, word counter, gap timers, /DRx, and TXR are affected by
reset assertion. The Control register is not.

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IP429II_BASE_REG2
$04 429 Control Register Port read/write
CONTROL REGISTER 2
DATA BIT DESCRIPTION
7 spare
6 spare
5 spare
4 spare
3 Hi/_LO_4 1 = 100Khz, 0 = 12.5 KHz.
2 Hi/_LO_3
1 Hi/_LO_2
0 Hi/_LO_1
FIGURE 4 IP-429 CONTROL REGISTER 2 BIT MAP
The transmit speed port is used to select the transmit speed for each of the ports
installed. 1 = 100 KHz. and 0 = 12-14.5Khz. operation. The spare bits are read-write.
Please note that the 3282 programming needs to match the CNTL2 selections for
speed. This is a legacy register retained for software commonality but has no effect on
operation. The new transmitter does not require this input.
IP429II_BASE_REG3
$06 429 Control Register Port read/write
CONTROL REGISTER 3
DATA BIT DESCRIPTION
7 Tx Int En 4 0 =disabled 1 = enabled
6 Tx Int En 3 0 =disabled 1 = enabled
5 Tx Int En 2 0 =disabled 1 = enabled
4 Tx Int En 1 0 =disabled 1 = enabled
3 Rx Int En 4 0 = disabled 1 = enabled
2 Rx Int En 3 0 = disabled 1 = enabled
1 Rx Int En 2 0 = disabled 1 = enabled
0 Rx Int En 1 0 = disabled 1 = enabled
FIGURE 5 IP-429 CONTROL REGISTER 3 BIT MAP
Configuration Devices
-1 1
-2 1,2
-3 1,2,3
-4 1,2,3,4

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Tx Int En X is used to enable or disable the interrupt associated with the transmit
device installed.
Devices not populated on the board should be masked off. 1 = enabled and 0 =
disabled for the interrupt. Default = 0. The leading edge of the TXRx status line from
the “3282” is used to generate the interrupt. After a transmission the TX FIFO is empty
causing the TXRx line to transition high. The line will remain high until data is written
into the FIFO for that channel. The interrupt is edge triggered so no further interrupts
will occur until another transition occurs. Clear the interrupt request by disabling the
interrupt enable for that channel and then [if desired] re-enable. The TXRx bits are
available in STATUS1.
Rx Int En X is used to enable or disable the interrupt associated with the receive
device. Each device has two receivers. The interrupts for the two receivers are
masked together by the chip interrupt mask. The individual receiver within each device
is identifiable with STATUS0.
Devices not populated on the board should be masked off. 1 = enabled and 0 =
disabled for the interrupt. Default = 0. The level from the DRx status lines from the
“3282” are used to generate the interrupt. After a reception the receive register has
data available is causing the DRx line to transition low. The line will remain low until
data is read for that channel.
The DRx lines transition off once the data is read so no further interrupts will occur until
another reception occurs. Clear the interrupt request by reading the data or setting the
mask to 0.
IP429II_VECTOR
$08 429 Interrupt Vector Port
The Interrupt vector for the 429 is stored in this byte wide register. This read/write
register is initialized to 'xxFF' upon power-on reset or software reset. The vector is
stored in the odd byte location [D7..0]. The vector should be initialized before the
interrupt is enabled or the mask is lowered. The interrupt is not cleared when the CPU
reads the vector. Please refer to the REG3 register description. For auto-vectored
systems this register can be ignored.

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IP429II_STATUS0
[$0A 429 Control Register Port read only
CONTROL REGISTER 1
DATA BIT DESCRIPTION
7 DR2 device 4 1 = data ready, 0 = no data
6 DR1 device 4
5 DR2 device 3
4 DR1 device 3
3 DR2 device 2
2 DR1 device 2
1 DR2 device 1
0 DR1 device 1
FIGURE 6 IP-429 STATUS REGISTER 0 BIT MAP
The DRx bits are the Data Ready status outputs from the encoder/decoder devices.
The signals are buffered and inverted to create active high data ready signals. DR1 is
receiver 1 of device N. DR2 is receiver 2 of device N. Each of the 4 channels has 2
receivers. There are four devices and your hardware may not have all four installed.
Uninstalled devices should be masked off when reading this status register. These bits
can be used for polled operation of the receivers. The signals return to zero when the
data is read. The _oe1 addresses should be accessed for the receiver 1 data and the
_oe2 addresses for the receiver 2 data within each channel.

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IP429II_STATUS1
[$0C 429 Control Register Port read only
CONTROL REGISTER 1
DATA BIT DESCRIPTION
7 undefined
6 undefined
5 undefined
4 undefined
3 TXR4
2 TXR3
1 TXR2
0 TXR1
FIGURE 7 IP-429 STATUS REGISTER 1 BIT MAP
The TXRx bits are the Transmitter Ready bits driven from the “3282”. When high the
bits indicate that the transmitter is ready to receive data. The rising edge of the signal is
used to create the TX completed interrupt as that edge indicates that the transmitter is
ready to receive more data. When the signal is low it indicates that the transmitter is
ready to send. If the SENDx bit is enabled then the transmission will begin. This bit can
be used for polled operation of the transmitter.

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IP429II_Parallel
$0E 429 Control Register Port read/write
CONTROL REGISTER Parallel Port
DATA BIT DESCRIPTION
15-8 read-back of lower 7 bits
7 PI_7 – read-back “cable side”
6 PI_6
5 PI_5
4 PI_4
3 PIO_3
2 PIO_2
1 PIO_1
0 PIO_0
FIGURE 8 IP-429 CONTROL REGISTER 0 BIT MAP
The PIO port consists of read only and read-writeable bits. The lower 4 bits [0-3] are
read-writeable. The bits are used to control open drain high sink drivers. The read-
back comes from the bus side of the drivers. If high then a low on the driver indicates
another device is driving the line low. The lines are pulled up with 1K pull-up resistors
and are terminated with 33Ωseries resistors. The upper 4 bits are read only and are
terminated with 33Ωseries terminators.
The port is configured with an 8 bit register. The lower 4 bits are used to control the
open drain drivers as described above. The lower 8 bits of the port are the read-back
from the cable side of the interface. The upper 8 bits are the registered bits read-back –
not affected by the cable.

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IP429_Encoder/Decoder
#define IP429II_OE0_DEV1_L 0x40 // read from Device 1 port 1 lower half
#define IP429II_OE0_DEV1_U 0x42 // read from Device 1 port 1 upper half
#define IP429II_OE1_DEV1_L 0x44 // read from Device 1 port 2 lower half
#define IP429II_OE1_DEV1_U 0x46 // read from Device 1 port 2 upper half
#define IP429II_LD1_DEV1 0x48 // write to Device 1 TX port lower half
#define IP429II_LD2_DEV1 0x4a // write to Device 1 TX port upper half
#define IP429II_CNTL_DEV1 0x4c // write to Device 1 control word
There are up to 4 “3282” devices installed per board. Each “3282” has two receivers
and 1 transmitter port. To support the control of the part several addresses are defined
per channel and replicated for each channel. Each channel is independent of the other
channels. Some settings within each “channel” [device installed] are binding on the
assets of the channel. For example the receive rate can be programmed high or low
per channel and affects both receivers within the channel.
IP429II_OE0_DEV1_L
IP429II_OE0_DEV1_U
IP429II_OE1_DEV1_L
IP429II_OE1_DEV1_U
These four addresses are for the reading of data from receiver 1 or 2 of channel 0. One
should access Lower then Upper. Both addresses actually activate the same control
signal to the 3282, but provide a different sense to the SEL line to tell the 3282 which 16
bit word to enable onto the bus at that time. When “U” is accessed the DRx flag is
reset.
“L” corresponds to the lower [D15..0] 16 bits of the 32 bit ARINC 429 data word.
“U” corresponds to the upper [D31..16] 16 bits of the 32 bit ARINC 429 data word.
IP429II_LD1_DEV1
IP429II_LD2_DEV1
The load addresses are for loading the upper and lower words for transmission. Word 1
should be loaded before word 2. Word 1 corresponds to the lower word of data
[D15..0], and word 2 corresponds to the upper word [D31..16]