Dynamic Engineering PCIeBiSerialDb37-BA22 User manual

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DYNAMIC ENGINEERING
150 DuBois St. Suite C, Santa Cruz, CA 95060
831-457-8891 Fax [phone]
http://www.dyneng.com
[email protected]
Est. 1988
User Manual
PCIeBiSerialDb37-BA22
Image Data Transmit & Receive Port
2 bit serial with clock and sync
PCIe 4 lane Module
LVDS
Revision C
Corresponding Hardware: Revision 1
10-2009-0402
FLASH 0303

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PCIeBiSerialDb37BA22
Image Data Interface
PCIe Module
Dynamic Engineering
150 DuBois St. Suite C, Santa Cruz CA 95060
831-457-8891 831-457-4793 FAX
This document contains information of proprietary interest to Dynamic
Engineering. It has been supplied in confidence and the recipient, by accepting
this material, agrees that the subject matter will not be copied or reproduced, in
whole or in part, nor its contents revealed in any manner or to any person except
to meet the purpose for which it was delivered.
Dynamic Engineering has made every effort to ensure that this manual is
accurate and complete. Still, the company reserves the right to make
improvements or changes in the product described in this document at any time
and without notice. Furthermore, Dynamic Engineering assumes no liability
arising out of the application or use of the device described herein.
The electronic equipment described herein generates, uses, and can radiate
radio frequency energy. Operation of this equipment in a residential area is likely
to cause radio interference, in which case the user, at his own expense, will be
required to take whatever measures may be required to correct the interference.
Dynamic Engineering’s products are not authorized for use as critical
components in life support devices or systems without the express written
approval of the president of Dynamic Engineering.
This product has been designed to operate with PCIe motherboards and
compatible user-provided equipment. Connection of incompatible hardware is
likely to cause serious damage.
©2009-2014 by Dynamic Engineering.
Other trademarks and registered trademarks are owned by their respective
manufacturers.
Manual Revision C. Revised 11/14/14

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PRODUCT DESCRIPTION 6!
ADDRESS MAP 14!
Base Address Map 14!
Channel Address Map 15!
Programming 16!
Base Register Definitions 18!
BA22_BASE_BASE 18!
BA22_BASE_ID 19!
BA22_BASE_STATUS 20!
BA22_BASE_PLL_WRITE BA22_BASE_PLL_READ 21!
Channel Bit Maps 22!
BA22_CHAN_CNTRL 22!
BA22_CHAN_STATUS 25!
BA22_CHAN_WR_DMA_PNTR 29!
BA22_CHAN_TX_FIFO_COUNT 30!
BA22_CHAN_RD_DMA_PNTR 30!
BA22_CHAN_RX_FIFO_COUNT 31!
BA22_CHAN_FIFO 31!
BA22_CHAN_TX_AMT_LVL 32!
BA22_CHAN_RX_AFL_LVL 32!
BA22_CHAN_READY_CNT 33!
BA22_CHAN_FRAME_REF 33!
BA22_CHAN_LINE_LENGTH 34!
BA22_CHAN_IDLE_LENGTH 34!
BA22_CHAN_FRAME_LENGTH 35!
CHAN_TX_PreAmblePat 35!
CHAN_TX_PreAmbleLen 35!
CHAN_TX_SyncPat 36!
CHAN_TX_SyncLen 36!
CHAN_TX_IdlePat 36!
CHAN_TX_DataPat 37!
LOOP-BACK 38!
PCIE MODULE FRONT PANEL IO INTERFACE PIN ASSIGNMENT 39!
Table of Contents

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APPLICATIONS GUIDE 40!
Interfacing 40!
Construction and Reliability 41!
Thermal Considerations 41!
Warranty and Repair 42!
Service Policy 42!
Out of Warranty Repairs 42!
SPECIFICATIONS 43!
ORDER INFORMATION 44!

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FIGURE 1 PCIEBISERIALDB37BA22 BLOCK DIAGRAM 8!
FIGURE 2 PCIEBISERIALDB37BA22 TIMING DIAGRAM 11!
FIGURE 3 PCIEBISERIALDB37BA22 IMAGE DIAGRAM 12!
FIGURE 4 PCIEBISERIALDB37BA22 INTERNAL ADDRESS MAP BASE FUNCTIONS 14!
FIGURE 5 PCIEBISERIALDB37BA22 CHANNEL ADDRESS MAP 15!
FIGURE 6 PCIEBISERIALDB37BA22 CONTROL BASE REGISTER BIT MAP 18!
FIGURE 7 PCIEBISERIALDB37BA22 ID AND SWITCH BIT MAP 19!
FIGURE 8 PCIEBISERIALDB37BA22 STATUS PORT BIT MAP 20!
FIGURE 9 PCIEBISERIALDB37BA22 PLL FIFO PORT BIT MAP 21!
FIGURE 10 PCIEBISERIALDB37BA22 CHANNEL CONTROL REGISTER 22!
FIGURE 11 PCIEBISERIALDB37BA22 CHANNEL STATUS PORT 25!
FIGURE 12 PCIEBISERIALDB37BA22 WRITE DMA POINTER REGISTER 29!
FIGURE 13 PCIEBISERIALDB37BA22 TX FIFO DATA COUNT PORT 30!
FIGURE 14 PCIEBISERIALDB37BA22 READ DMA POINTER REGISTER 30!
FIGURE 15 PCIEBISERIALDB37BA22 RX FIFO DATA COUNT PORT 31!
FIGURE 16 PCIEBISERIALDB37BA22 RX/TX FIFO PORT 31!
FIGURE 17 PCIEBISERIALDB37BA22 TX ALMOST EMPTY LEVEL REGISTER 32!
FIGURE 18 PCIEBISERIALDB37BA22 RX ALMOST FULL LEVEL REGISTER32!
FIGURE 19 PCIEBISERIALDB37BA22 TX READY COUNT REGISTER 33!
FIGURE 20 PCIEBISERIALDB37BA22 TX FRAME REFERENCE REGISTER 33!
FIGURE 21 PCIEBISERIALDB37BA22 TX LINE LENGTH REGISTER 34!
FIGURE 22 PCIEBISERIALDB37BA22 TX IDLE LENGTH REGISTER 34!
FIGURE 23 PCIEBISERIALDB37BA22 TX FRAME LENGTH REGISTER 35!
FIGURE 24 PCIEBISERIALDB37BA22 TX PREAMBLE PATTERN REGISTER 35!
FIGURE 25 PCIEBISERIALDB37BA22 TX PREAMBLE LENGTH REGISTER 35!
FIGURE 26 PCIEBISERIALDB37BA22 TX SYNC PATTERN REGISTER 36!
FIGURE 27 PCIEBISERIALDB37BA22 TX SYNC LENGTH REGISTER 36!
FIGURE 28 PCIEBISERIALDB37BA22 TX IDLE PATTERN REGISTER 36!
FIGURE 29 PCIEBISERIALDB37BA22 TX DATA PATTERN REGISTER 37!
FIGURE 24 PCIEBISERIALDB37BA22 LOOP-BACK WIRING DIAGRAM 38!
FIGURE 25 PCIEBISERIALDB37BA22 FRONT PANEL INTERFACE 39!
List of Figures

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Product Description
In embedded systems many of the interconnections are made with differential [RS-
422/485 or LVDS] signals. Depending on the system architecture an IP, PMC or native
bus card will be the right choice to make the connection. You have choices with carriers
for cPCI, PCI, PCIe, VME, PC/104p and other buses for both PMC and IP mezzanine
modules.
The BiSerial family includes IP, PMC, PCI-104 and PCIe versions, each with multiple
“clientized” design implementations.
Usually the choice of format is based on other system constraints. Dynamic
Engineering is happy to assist in your decision regarding architecture and other trade-
offs with the form factor decision. Dynamic Engineering has carriers for IP and PMC
modules for most systems, and is adding more as new solutions are requested by our
clients.
The PCIe compatible PCIeBiSerialDb37 has 18 independent differential IO available. A
DB-37 connector is mounted through the bezel to carry the signals. Each of the IO has
independent direction and termination controls. Each of the IO is matched length and
routed with 100 Ωdifferential impedance.
The IO’s are buffered from the FPGA with differential transceivers. The transceivers
can be populated with LVDS or RS-485 compatible devices. The power plane for the
transceivers is isolated to allow selectable 3.3 or 5V references for the IO. The LVDS
IO requires 3.3, and 40 MHz capable RS-485 requires 5V. When mixed LVDS and
RS485 are used the reference is set to 3.3 and lower speed [20 MHz] RS-485 parts are
used that are compatible with the 3.3V.
Each IO has pull-up and pull-down options to allow half duplex lines to be set to a
“marking” state when no device is on the line. The P is is ganged and the M side is too.
Each side can be set to GND or VCC to allow a ‘1’ or a ‘0’ to be set on the lines. The
resistors are in resistor packs and can be implemented with many values.
The terminations utilize analog switches to selectively parallel terminate the differential
pair with approximately 100 ohms. It is recommended that the receiver side provide the
termination.
The analog switches are protected with a diode on the input side of the power supply.
The switches can back-feed voltage into the rest of the circuit when powered down and
the system connected to it is not. The diodes allow for more flexible operation and
power sequencing.
PcieBiSerialDb37BA22 is a “clientized” version of the standard PCIeBiSerialDb37

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board. “BA22” is set to use the LVDS standard, and supports one Transmit and one
Receive channel. The transmitter and receiver are designed to interface with a 2 bit
serial data stream with reference sync and clk. The base frequency is 73.636 MHz.
The transmit frequency is programmable using the A output from the PLL.
The receive side auto-bauds to the incoming rate. The data is deserialized and when
the synchronization pattern indicates, captured into a FIFO. The captured data is
available for DMA transfer to the host memory.
The Transmitter is supported with a combination of discrete 128Kx32 and BRAM based
FIFO’s for a total of 268,285 x 32 FIFO. Using DMA transfers the transmit side can
provide a continuous flow of data at the output. The transmitter has a programmable
frame start reference as well as programmable Line, Idle, Frame, Sync and PreAmble
lengths. In addition the control pattern for IDLEs, DATA, SYNC, and PreAmble are
programmable. The rate of transmission, and the dimensions of the transmission are
programmable.
Since the data is serialized as 2 -7 bit streams from 1 -14 bit word data is packed 2
pixels per LW. With the standard transmission rate of 73.636 MHz the effective unload
rate is (73.636/7)*2 or 5.259 MLW/S. The input side capability with DMA is 33 MLW/S
before overhead and perhaps 20 MLW/S with overhead.
The transmitter has an additional programmable feature of a minimum FIFO count
before starting transmission. By setting the count to be fairly large, the FIFO can be
effectively used as a timing buffer to insure a constant flow of data . With the large
multiplier (DMA vs Transmission) the “fill side” will always be able to keep up with the
transmitter on an overall basis. The FIFO will insure short term delays in processing do
not cause under-run issues. 268,285 x 2 * 3/4 * 7 * 13.58 => 38 mS of storage. [total
TX FIFO (LW) * 2 Pixels/LW * fraction filled when OS system delay happens* effective
bits per pixel [14 but 2 streams] * period of transmission clock]
The Receiver and Transmitter are separately supported with scatter gather capable
DMA engines.

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Figure 1 PcieBiSerialDb37BA22 Block Diagram
BA22 supports transmission and reception of serialized 2 bit wide data. The Data
transfer is controlled with a continuous clock plus sync pattern. The transmitter uses
the rising edge of the clock. The receiver uses the falling edge of the clock. The
serialized data is deserialized and stored as pixels, two per LW. The upper two bits per
stored pixel are used to mark frames and lines to allow for SW synchronization.
The PLL can be used to create a Tx clock reference. The control is via SW. The PLL is
referenced to 25 MHz. and can be programmed with new .JED files using the driver.
The hardware supports programming the PLL with an I2C bus , 2-256x32 FIFO’s and a
state-machine. The UserAp and driver provide a reference for programming the PLL.
The .JED file is the output from the Cypress 22393 programming tool. The Dynamic
Engineering SW “cracks” the .JED and loads the appropriate portions into the storage
elements for the state-machine to transfer to the PLL.
The transmitter hardware waits until the SW enable is set, the programmed minimum
data in the TX FIFO has been met, and the sync pulse is received [from the local timer].
Once in transmission the sync pulse and a non empty FIFO are the requirements to
(2 x 4 x LVDS)
termination
PCI IF
Data Flow
Control
PLL
TX FIFO
~262K x 32
TX State
Machine
RX FIFO
5K x 32
RX State
Machine
BA22
PCIe x4
PCI Bridge

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start sending the second, third…. frames. Once started if the data FIFO is empty when
the transmitter is ready to read the next data set, an error for underflow is flagged. The
error can cause an interrupt if desired.
An additional feature is programmable IDLE pattern output. When IDLEs are enabled in
the control register the transmitter will begin transmitting IDLEs whenever the state-
machine is enabled. When IDLEs are not enabled, IDLEs are still transmitted between
lines and frames, but not when the transmitter is not active.
The receiver uses the received clock to capture data with a small state-machine that
loads the data into 2 parallel shift registers. Data from the shift registers is combined to
form pixels. In addition the upper bit [D15] is set when a frame boundary is
encountered. D14 is set for each line received. Frame detection is based on either the
Sync or PreAmble patterns being detected – next data pixel is then marked. Lines are
marked when Idles are detected, again on the next data pixel. If the IDLE pattern is the
same as the SYNC pattern all lines will be marked as having both Frame and Line.
Two pixels are stored to make a 32 bit quantity before moving to the first storage FIFO.
The reference rate of the input to the FIFO is the receive clock.
The read side of the first receive FIFO is tied to the input side of a 1Kx32 FIFO. The
second FIFO is used to support the receive DMA action.
The second FIFO has two sources. The transmit data chain can be looped back from a
point between the second discrete FIFO and the final transmission FIFO to the DMA
FIFO. With the Bypass bit set data loaded into the TX side can be read from the RX
side for an internal BIT. The first receive and last transmit stages are the only missing
pieces.
Both the transmitter and receiver allow for pixel reversal. The data is stored as 32 bit
words into the transmit FIFO from the system or the receive FIFO from the interface.
The pixel stored into the D15-0 or D31-16 can be transmitted first depending on the
selection of the transmit data order. Similarly the receive side data order can be
reversed if needed.
Custom cables can be manufactured to your requirements. The loop-back IO
definitions are toward the end of this manual. Please contact Dynamic Engineering with
your specifications.
In the “BA22” design the Termination and Direction controls are set in the VHDL for the
IO. The received signals are terminated and the transmitted signals are not.
All of the IO is routed through the FPGA to allow for custom applications. Larger
external and internal FIFO’s and Dual Ported memories are implemented for this

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version by FPGA selection, and adding the 128K x 32 FIFO’s to the board.
The registers are mapped as 32 bit words and support 32 bit access. Most registers are
read-writeable. Windows® , Linux and other OS can be used to interface with this
design. For Dynamic Engineering drivers please check the DDS [Dynamic Data Sheet
on-line] . Custom drivers can be written for your situation. Existing drivers are “free” to
BA22 clients. Support programs are available based on the client’s level of expertise
and need. Use standard C/C++ to control your hardware or use the Hardware manual
to make your own software interface. The software manuals are also available on-line.
PcieBiserialDb37 can be used for multiple purposes with applications in
telecommunications, control, sensors, IO, test; anywhere multiple independent or
coordinated IO are useful.
PcieBiserialDb37 features a Xilinx FPGA, and high-speed differential devices. The
FPGA contains the PCI interface and control required for the IO interface.
The Xilinx design incorporates the “PCI Core” and additional modules for DMA in
parallel with a direct register decoded programming model. The design model has a
“base” level with the basic board level functions and “channels” which contain IO
oriented functions. In the BA22 design the IO functions are designed into the channel
and the PLL programming, switch, and other common or basic functions are in the base
design.
From a software perspective the design can be treated as “Flat” or as a hierarchy. The
Dynamic Engineering Windows® driver uses the hierarchical approach to allow for more
consistent software with common bit maps and offsets. This implementation has only
one channel. The channel function was kept to allow for future expansion with more
than 1 IO interface or a secondary function in added channels. The user software can
control the Channels with the same calls and use the channel number to distinguish.
This makes for consistent and easier to implement user level software.
The hardware is designed with each of the channels on a common address map – each
channel has the same memory allocated to it and as much as possible the offsets within
each space are defined in the same way or similar way. Again this make understanding
each port easier to accomplish and less likely to have errors.
The transceivers are initialized to the receive state. Once a channel is defined via
software to be a transmitter the IO are enabled and driven to the appropriate levels.
Terminations are activated for ports defined to be receivers.
PcieBiserialDb37 is part of the PCIe Module family of modular I/O components. The
PcieBiserialDb37 conforms to the PCIe standard. This guarantees compatibility with
your PCIe system. The base is 4 lane operation. The design can handle 1-4 lanes

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being available. LED’s are provided to show the active PCIe lanes.
Designs implemented on PC104p, PMC, IP and PCIe versions of the BiSerial family can
in large part be ported between platforms. If you see what you need in one version and
prefer it on another please contact Dynamic Engineering about porting the design. In
most cases it will require a recompile of the VHDL and not much more. We do a lot of
“just like but different “ adaptations for our clients. Please contact us to help you with a
successful special adaptation of off- the-shelf hardware.
The DMA programmable length is 32 bits => longer than most computer OS will allow in
one segment of memory. The DMA is scatter gather capable for longer lengths than the
OS max and for OS situations where the memory is not contiguous. With Windows®
lengths of 4K are common while Linux can provide much larger spaces. Larger spaces
are more efficient as there are fewer initialization reads and reduced overhead on the
bus. A single interrupt can control the entire transfer. Head to tail operation can also be
programmed with two memory spaces with two interrupts per loop.
The hardware is organized with the IO function in channel 0 and the card level functions
in the “base”. The driver provides the ability to find the hardware and to allocate
resources to use the base and channel functions.
The basic use of the interface is to facilitate data transfer between the host and the
remote target.
Figure 2 PCIEBISERIALDB37BA22 Timing Diagram
The clock is free running. The transmitter provides data with close to 50% duty cycle –
CLK
DATAL 654 3210
DATAU 13 12 11 10 9 8 7
SYNC F
6
13

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changing on the rising edge, and stable on the falling edge.
The transmit rate is programmable for the BA22. PLL channel A is programmed to
73.636 MHz for a 73.636 MHz. output rate.
Sync programmable both for pattern and number of pixels. In addition a PreAmble is
provided again with programmable pattern and number of pixels. Master Frame Sync
=> PreAmble => Sync => Data/IDLE…complete Frame. If the number of PreAmble
Pixels is zero the HW will automatically skip to the Sync unless that is also zero pixels in
which case it starts with the Data Control pattern.
Some camera interfaces use a 1 pixel sync followed by some number of IDLE
characters to form a sync pattern. In this case the PreAmble is programmed as the
SYNC, the SYNC as the IDLE pattern and then DATA and IDLE as normal. The
PreAmble length would be 1 and the Sync length 3 or whatever the camera interface
requires.
Figure 3 PCIEBISERIALDB37BA22 Image Diagram
The Image Transfer Area is controlled by programming the number of pixels per line
[Line Length], the number of pixel times at the end of a line [Idle Length], the number of
IDLE
IMAGE AREA
BLANKING
LINE LENGTH
LINE COUNT

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lines per frame [Frame Length], and the repetition rate. The Blanking time is the
difference in the frame repetition rate and the size of the image and idle time. It is
programmed in terms of the reference rate clock. The time does not have to be an
integer number of pixels. Please see the register definitions for more detail.

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Address Map
Base Address Map
Function Offset
// PCIeBiSerialDb37BA22 BASE definitions
#define BA22_BASE_BASE 0x0000 // 0 BA22Base Base control register
#define BA22_BASE_USER_SWITCH 0x0004 // 1 BA22Base User DIP switch read
#define BA22_BASE_XILINX_REV 0x0004 // 1 BA22Base Xilinx revision read port
#define BA22_BASE_XILINX_DES 0x0004 // 1 BA22Base Xilinx design read port
#define BA22_BASE_STATUS 0x0008 // 2 BA22Base status Register offset
#define BA22_BASE_PLL_WRITE 0x0000 // 4 BA22Base PLL FIFO write port
#define BA22_BASE_PLL_READ 0x0000 // 4 BA22Base PLL FIFO read port
Figure 4 PCIeBiSerialDb37BA22 Internal Address Map Base Functions
The address map provided is for the local decoding performed within
PcieBiserialDb37BA22. The addresses are all offsets from a base address. Dynamic
Engineering prefers a long-word oriented approach because it is more consistent across
platforms.
The map is presented with the #define style to allow cutting and pasting into many
compilers “include” files.
The host system will search the PCI bus to find the assets installed during power-on
initialization. The VendorId = 0xDCBA and the CardId = 0x0052 for the
PcieBiSerialDb37BA22.
The BA22 design has 1 channel implemented at this time. The BASE contains the
common elements of the design, while the Channels have the IO specific interfaces.
The BASE starts at the card offset. Channel 0 starts at register 20
Section Register Address Range COM name
(starting Hex address)
Base 0-19 (0x0000) PLL, Switch, Status
Channel 0 20-39 (0x0050) BA22 Transmitter & Receiver

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Channel Address Map
Function Offset from Channel Base Address
#define CHAN_CNTRL 0x00000000 // 0 General control register
#define CHAN_STATUS 0x00000004 // 1 Interrupt status port
#define CHAN_INT_CLEAR 0x00000004 // 1 Interrupt clear port
#define CHAN_WR_DMA_PNTR 0x00000008 // 2 Write DMA dpr physical PCI address register
#define CHAN_TX_FIFO_COUNT 0x00000008 // 2 Tx FIFO count read port
#define CHAN_RD_DMA_PNTR 0x0000000C // 3 Read DMA dpr physical PCI address register
#define CHAN_RX_FIFO_COUNT 0x0000000C // 3 Rx FIFO count read port
#define CHAN_FIFO 0x00000010 // 4 FIFO offset for single word access R/W
#define CHAN_TX_AMT 0x00000014 // 5 Tx almost empty count register - used for Urgent
and pulsed interrupt
#define CHAN_RX_AFL 0x00000018 // 6 Rx almost full count register
#define CHAN_READY_CNT 0x00000024 // 9 Amount of data in pipeline before Tx can start
#define CHAN_FRAME_REF 0x00000028 // 10 Count representing time between frame start
triggers
#define CHAN_LINE_LENGTH 0x0000002C // 11 Number of pixels in a line
#define CHAN_IDLE_LENGTH 0x00000030 // 12 Number of idles at end of line
#define CHAN_FRAME_LENGTH 0x00000034 // 13 Number of lines in a frame
#define CHAN_TX_PreAmblePat 0x00000038 // 14 PreAmble Control Word
#define CHAN_TX_PreAmbleLen 0x0000003C // 15 PreAmble number of Pixels
#define CHAN_TX_SyncPat 0x00000040 // 16 Sync Control Word
#define CHAN_TX_SyncLen 0x00000044 // 17 Sync Number of Pixels
#define CHAN_TX_IdlePat 0x00000048 // 18 Idle Control Word
#define CHAN_TX_DataPat 0x0000004C // 19 Data Control Word
Figure 5 PcieBiSerialDb37BA22 Channel Address Map

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Programming
Programming the PcieBiSerialDb37BA22 requires only the ability to read and write data
in the host's PCIe space.
Once the initialization process has occurred, and the system has assigned addresses to
the PcieBiSerialDb37BA22 card the software will need to determine what the address
space is for the PCI interface [BAR0]. The offsets in the address tables are relative to
the system assigned BAR0 base address.
The next step is to initialize the PcieBiSerialDb37BA22. The PLL will need to be
programmed to use the loop-back function or to transmit in the system. The Cypress
CyberClocks software can be used to create new .JED files if desired. PLLA should be
set to the transmit reference frequency output by the transmitter.
The driver comes with a .JED file prepared. The driver has a utility to load the PLL and
read back. The reference application software has an example of the use of PLL
programming. The reference application software also includes XLATE.c which
converts the .JED file from the CyberClocks tool to an array that can be programmed
into the PLL.
The IO for the BA22 direction and termination are hardwired in this design. The ports
are unidirectional and initialization is simplified with this approach.
The control bits for the BA22 will select how the data is transmitted – ordering, size of
transfer etc.
For Windows XP™ systems the Dynamic Driver can be used. The driver will take care
of finding the hardware and provide an easy to use mechanism to program the
hardware. The Driver comes with reference software showing how to use the card and
reference frequency files to allow the user to duplicate the test set-up used in
manufacturing at Dynamic Engineering. Using simple, known to work routines is a good
way to get acquainted with new hardware.
To use the BA22 specific functions the Channel Control, and PLL interface plus DMA
will need to be programmed. To use DMA, memory space from the system should be
allocated and the link list stored into memory. The location of the link list is written to
the BA22 to start the DMA. Please refer to the Burst IN and Burst Out register
discussions.
DMA should be set-up before starting the channel port function. For transmission this
will result in the FIFO being full or close to it when the transfer is started or at least the

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Packet loaded if shorter than the FIFO size. For reception it means that the FIFO is
under HW control and the delay from starting reception to starting DMA won’t cause an
overflow condition.
DMA can be programmed with a specific length. The length can be as long as you want
within standard memory limitations. At the end of the DMA transfer the Host will receive
an interrupt. The Transmitter can be stopped, and the FIFO reset to clear out any
untransmitted data. For on-the-fly processing multiple shorter DMA segments can be
programmed; at the interrupt restart DMA to point at the alternate segment to allow
processing on the previous one. This technique is sometimes referred to as “ping-
pong”.
Please see the channel control register bit maps for more information.

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Base Register Definitions
BA22_BASE_BASE
[$00 Base Control Register Port read/write]
DATA BIT DESCRIPTION
31-2 spare
1 ClrPll
0 PllProgEn
Figure 6 PcieBiSerialDb37BA22 Control Base Register Bit Map
This is the base control register for the BA22. The features common to all channels are
controlled from this port. Unused bits are reserved for additional new features. Unused
bits should be programmed ‘0’ to allow for future commonality.
PllProgEn: When this bit is set to a one, the state-machine used to program the PLL is
enabled to operate.
ClrPll: when set the PLL and associated memories are cleared. Must be returned to
cleared for normal operation.
The PLL is programmed with the output file generated by the Cypress PLL
programming tool. [CY3672 R3.01 Programming Kit or CyberClocks R3.20.00 Cypress
may update the revision from time to time.] The .JED file is used by the Dynamic Driver
to program the PLL. Programming the PLL is fairly involved and beyond the scope of
this manual. For clients writing their own drivers it is suggested to get the Engineering
Kit for this board including software, and to use the translation and programming files
ported to your environment. This procedure will save you a lot of time. For those who
want to do it themselves the Cypress PLL in use is the 22393. The output file from the
Cypress tool can be passed directly to the Dynamic Driver [Linux or Windows] and used
to program the PLL without user intervention.
The reference frequency for the PLL is 25 MHz.

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BA22_BASE_ID
[$04 Switch and Design number port read only]
DATA BIT DESCRIPTION
31-24 spare
23-8 Design ID and Revision
7-0 DIP switch
Figure 7 PcieBiSerialDb37BA22 ID and Switch Bit Map
The DIP Switch is labeled for bit number, and ‘1’ ‘0’ in the silk screen. The DIP Switch
can be read from this port and used to determine which PcieBiserialDb37BA22 physical
card matches each PCI address assigned in a system with multiple cards installed.
The DIPswitch can also be used for other purposes – software revision etc. The switch
shown would read back 0x12.
The Design ID and Revision are defined by a 16 bit field allowing for 256 designs and
256 revisions of each. The BA22 design is 0x03 the current revision is 0x01.
The PCI revision is updated in HW to match the design revision. The board ID will be
updated for major changes to allow drivers to differentiate between revisions and
applications.
1
7 0
0

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BA22_BASE_STATUS
[$08 Board level Status Port read only]
DATA BIT DESCRIPTION
31-19 set to ‘0
18-16 PllPckDnCnt
15-13 set to ‘0’
12 PllNakLat
11 PllPacketDoneLat
10 PllRdFifoMt
9 PllWrFifoMt
8 Pll Idle
7-1 set to ‘0’, reserved for additional channels
0 Unmasked Ch0 Interrupt
Figure 8 PcieBiSerialDb37BA22 Status Port Bit Map
Channel Interrupt – The local interrupt status from the channel. Each channel can have
different interrupt sources. DMA Write or DMA Read or IntForce or TX/RX request are
typical sources. Polling can be accomplished using the channel status register and
leaving the channel interrupt disabled.
Pll Idle when set indicates the PLL State-Machine is in the IDLE state.
PllWrFifoMt when set indicates the FIFO associated with writing data to the PLL is
empty. When cleared at least 1 location is filled.
PllRdFifoMt when set indicates the FIFO associated with reading data from the PLL is
empty. When cleared at least 1 location is filled.
PllPacketDoneLat is set and held when the PLL completes an operation. For example a
write to the PLL when completed will set this bit. This is a sticky bit. Cleared by writing
to the same address with this bit set.
PllNakLat when set indicates an operation to the PLL was not acknowledged. Usually
this is due to an improper address being used to communicate with the PLL. This is a
sticky bit. Clear by writing back with this bit position set.
PllPckDnCnt is a 3 bit count indicating how many operations have completed. Each
write operation takes 1 and each read takes 2 since the address is first written and then
the data read. The count can be used as a condition to know when a transfer is
completed. Count is cleared when the PllPacketDoneLat bit is cleared.