Dynamic Engineering PMC-BiSerial-III SDLC User manual

DYNAMIC ENGINEERING
150 DuBois, Suite C Santa Cruz, CA 95060
[phone], Fax: [phone]
www.dyneng.com
[email protected]
Est. 1988
User Manual
PMC-BiSerial-III SDLC
8 channel
SDLC Interface
PMC Module
Revision A1
Corresponding Hardware: Revision E
10-2005-0205
Corresponding Firmware: Revision B

Embedded Solutions Page 2 of 37
PMC-BiSerial-III SDLC
PMC Module
Dynamic Engineering
150 DuBois, Suite C
Santa Cruz, CA 95060
[phone]
FAX: [phone]
This document contains information of
proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the
recipient, by accepting this material, agrees that
the subject matter will not be copied or
reproduced, in whole or in part, nor its contents
revealed in any manner or to any person except
to meet the purpose for which it was delivered.
Dynamic Engineering has made every effort to
ensure that this manual is accurate and
complete. Still, the company reserves the right
to make improvements or changes in the
product described in this document at any time
and without notice. Furthermore, Dynamic
Engineering assumes no liability arising out of
the application or use of the device described
herein.
The electronic equipment described herein
generates, uses, and can radiate radio
frequency energy. Operation of this equipment
in a residential area is likely to cause radio
interference, in which case the user, at his own
expense, will be required to take whatever
measures may be required to correct the
interference.
Dynamic Engineering’s products are not
authorized for use as critical components in life
support devices or systems without the express
written approval of the president of Dynamic
Engineering.
This product has been designed to operate with
PMC Module carriers and compatible user-
provided equipment. Connection of
incompatible hardware is likely to cause serious
damage.
©2005-2015 by Dynamic Engineering.
Other trademarks and registered trademarks are
owned bytheir respective manufacturers.
Revised October 22, 2015.

Embedded Solutions Page 3 of 37
Table of Contents
PRODUCT DESCRIPTION 6
THEORY OF OPERATION 9
ADDRESS MAP 12
PROGRAMMING 13
REGISTER DEFINITIONS 14
BIS3_BASE 14
BIS3_ID 15
BIS3_IO_DATA 15
BIS3_IO_DIR 16
BIS3_IO_TERM 16
BIS3_IO_MUX 17
BIS3_IO_UCNTL 17
BIS3_IO_RDBK 18
BIS3_IO_RDBKUPR 18
BIS3_SWITCH 19
BIS3_PLL_CMD, PLL_RDBK 20
BIS3_SDLC_CNTL7-0 21
BIS3_INT_STAT 24
BIS3_I2OAR 24
Mode Resource Mapping 25
Channel I/O Line Mapping 26
Interrupts 27
Loop-back 28
PMC PCI PN1 INTERFACE PIN ASSIGNMENT 30
PMC PCI PN2 INTERFACE PIN ASSIGNMENT 31
BISERIAL III FRONT PANEL I/O PIN ASSIGNMENT 32
APPLICATIONS GUIDE 33

Embedded Solutions Page 4 of 37
Interfacing 33
CONSTRUCTION AND RELIABILITY 34
THERMAL CONSIDERATIONS 34
WARRANTY AND REPAIR 35
SERVICE POLICY 35
OUT OF WARRANTY REPAIRS 35
FOR SERVICE CONTACT: 35
SPECIFICATIONS 36
ORDER INFORMATION 37
SCHEMATICS 37

Embedded Solutions Page 5 of 37
List of Figures
FIGURE 1 PMC BISERIAL-III BASE BLOCK DIAGRAM 6
FIGURE 2 PMC BISERIAL-III SDLC BLOCK DIAGRAM 8
FIGURE 3 PMC BISERIAL-III SDLC INTERNAL ADDRESS MAP 12
FIGURE 4 PMC BISERIAL-III SDLC BASE CONTROL REGISTER BIT MAP 14
FIGURE 5 PMC BISERIAL-III SDLC DESIGN ID REGISTER BIT MAP 15
FIGURE 6 PMC BISERIAL-III SDLC PARALLEL OUTPUT DATA BIT MAP 15
FIGURE 7 PMC BISERIAL-III SDLC DIRECTION CONTROL PORT 16
FIGURE 8 PMC BISERIAL-III SDLC TERMINATION CONTROL PORT 16
FIGURE 9 PMC BISERIAL-III SDLC MUX CONTROL PORT 17
FIGURE 10 PMC BISERIAL-III SDLC UPPER CONTROL PORT 17
FIGURE 11 PMC BISERIAL-III SDLC I/O READBACK PORT 18
FIGURE 12 PMC BISERIAL-III SDLC I/O READBACK PORT 18
FIGURE 13 PMC BISERIAL-III SDLC SWITCH PORT 19
FIGURE 14 PMC BISERIAL-III SDLC PLL CONTROL 20
FIGURE 15 PMC BISERIAL-III SDLC CONTROL REGISTERS 21
FIGURE 16 PMC BISERIAL-III SDLC INTERRUPT STATUS REGISTER 24
FIGURE 17 PMC BISERIAL-III SDLC I2O ADDRESS REGISTER 24
FIGURE 18 PMC BISERIAL-III PN1 INTERFACE 30
FIGURE 19 PMC BISERIAL-III PN2 INTERFACE 31
FIGURE 20 PMC BISERIAL-III FRONT PANEL INTERFACE 32

Embedded Solutions Page 6 of 37
Product Description
The PMC BiSerial-III-SDLC is part of the PMC Module family of modular I/O
components by Dynamic Engineering. The PMC BiSerial-III is capable of providing
multiple serial protocols. The SDLC protocol implemented provides 8 full-duplex SDLC
I/O channels.
Other custom interfaces are available. We will redesign the state machines and create
a custom interface protocol. That protocol will then be offered as a “standard” special
order product. Please see our web page for current protocols offered. Please contact
Dynamic Engineering with your custom application.
485/LVDS buffers
termination
PCI IF
FIFO B
128K x32 FIFO A
128K x32
State
Machine
B
State
Machine
A
Data Flow
Control
PLL
FIGURE 1 PMC BISERIAL-III BASE BLOCK DIAGRAM

Embedded Solutions Page 7 of 37
The PMC BiSerial-III conforms to the PMC and CMC draft standards. This guarantees
compatibility with multiple PMC Carrier boards. Because the PMC may be mounted on
different form factors, while maintaining plug and software compatibility, system
prototyping may be done on one PMC Carrier board, with final system implementation
uses a different one. Contact Dynamic Engineering for a copy of this specification. It is
assumed that the reader is at least casually familiar with this document and basic logic
design.
In standard configuration, the PMC BiSerial-III is a Type 1 mechanical with only low-
profile components on the back of the board and one slot wide, with 10 mm inter-board
height for the front panel, standoffs, and PMC connectors. The 10 mm height is the
"standard" height and will work in most systems with most carriers. If your carrier has
non-standard connectors (height) to mate with the PMC BiSerial-III, please let us know.
We may be able to do a special build with a different height connector to compensate.
The standard configuration shown in Figure 1 makes use of two external (to the Xilinx)
FIFOs. The FIFOs can be as large as 128K deep x 32 bits wide. Some designs do not
require so much memory, and are more efficiently implemented using the Xilinx internal
memory.
The SDLC implementation has sixteen 4 Kbyte Dual Port RAM (DPR) blocks
implemented using the Xilinx internal block RAM. Each channel has two associated
DPRs. Each DPR is configured to have a 32-bit port on the PCI side, and a 16-bit port
on the I/O side. See Figure 2 for a representation of the SDLC circuit.
The SDLC interface uses programmable PLL clock A as a reference frequency to
sample the internal or external transmitter clock. Clock and data in and out comprise
the four I/O lines of each SDLC channel. The two DPRs are partitioned into one block
each for transmit and receive. The RAM blocks are used as circular buffers that have
independently specified start and stop addresses and separate transmit and receive
interrupts.
All the data I/O lines on the SDLC are programmable to be register controlled or state-
machine controlled. Any or all of the bits can be used as a parallel port instead of being
dedicated to a specific I/O protocol. Thirty-four differential I/O are provided at the front
bezel (32 of the 34 at Pn4) for the serial signals. The drivers and receivers conform to
the RS-485 specification (exceeds RS-422 specification). The RS-485 input signals are
selectively terminated with 100Ω. The termination resistors are in two-element
packages to allow flexible termination options for custom formats and protocols.
Optional pull-up/pull-down resistor packs can also be installed to provide a logic ‘1’
when the lines are not driven. The terminations and transceivers are programmable
through the Xilinx device to provide the proper mix of outputs and inputs and
terminations needed for a specific protocol implementation. The terminations are
programmable for all I/O.

Embedded Solutions Page 8 of 37
All configuration registers support read and write operations for maximum software
convenience, and all addresses are long word aligned.
Interrupts are supported by the PMC BiSerial-III-SDLC. An interrupt can be configured
to occur at the end of each transmitted message-frame, at the end of all message-
frames transmitted, at the end of a received message-frame or when an abort character
has been received. All interrupts can be individually masked, and a master interrupt
enable is also provided to disable all interrupts simultaneously. The current interrupt
status is available whether an individual interrupt is enabled or not making it possible to
operate in polled mode. I2O interrupt processing is also implemented.
FIGURE 2 PMC BISERIAL-III SDLC BLOCK DIAGRAM

Embedded Solutions Page 9 of 37
Theory of Operation
The PMC BiSerial-III-SDLC features a Xilinx FPGA. The FPGA contains all of the
registers and protocol controlling elements of the BiSerial III design. Only the PLL,
transceivers, and switches are external to the Xilinx device.
The PCI interface to the host CPU is controlled by a logic block within the Xilinx. The
BiSerial III design requires one wait state for read or write cycles to any address. The
PMC BiSerial-III is capable of supporting 40M Bytes per second into and out of the
DPR. With a Windows® read/write loop better than 20 MB/sec is attained on most
computers. The wait states refer to the number of clocks after the PCI core decode
before the “terminate with data” state is reached. Two additional clock periods account
for the 1 clock delay to decode the signals from the PCI bus and to convert the
terminate-with-data state into the TRDY signal.
The BiSerial III can support many protocols. The PMC BiSerial-III-SDLC supports
eight-channel full-duplex SDLC interfaces. This is a synchronous interface with
separate clock and data inputs and outputs. Each message is delimited by eight-bit
flag characters. The beginning flag and the ending flag enclose the SDLC frame. Both
beginning and ending flags have the binary format 01111110. The ending flag for one
frame may serve as the beginning flag for the next frame. Alternatively, the ending zero
of an ending flag may serve as the beginning zero of a beginning flag, thus forming the
pattern ‘011111101111110’. Also, the transmitter may insert multiple flags between
frames to maintain the active state of the link if time fill between message frames is
required. In order to avoid false flag detection from the data pattern, the SDLC
interface uses zero insertion. If five consecutive ones appear anywhere in the data
stream, a zero is inserted to avoid having six consecutive one bits. On the receive side,
when five ones are received the sixth bit is monitored. If it is a zero, it is removed from
the data stream, if it is a one then either a start/stop flag or an abort character (0xFE)
has been detected. Any ending flag may be followed by a frame, by another flag, or by
an idle condition. The idle condition is signaled by a minimum of 15 consecutive one
bits. As long as one bits continue to be sent, the link remains in the idle state.
To send a message, write the message data to the transmit DPRs, specify the start and
stop addresses and configuration control bits, then enable the transmitter. The state-
machine will load the start address, send the beginning flag character and then send
the data sequentially LSB first until the end address is reached and the ending flag is
sent. As soon as the beginning flag is sent, the sending status bit will be asserted. At
that time the ending address will be latched in the transmitter and new addresses can
be written for the next message to be sent. This message will be sent as soon as the
current message completes. If a new transmit starting address is not written, the
transmitter will continue reading data with the next address after the stop address of the
current frame. A new transmit end address must be written to trigger sending an
additional message-frame.

Embedded Solutions Page 10 of 37
If the TX clear is enabled, the transmitter will be automatically disabled and the TX
interrupt will be asserted when no more message frames have been requested. If the
TX clear is not enabled, the transmitter will remain enabled after the last message, but
the TX interrupt will still be asserted. When multiple frames are being sent, the frame
done interrupt will be asserted at the end of each message-frame. The TX interrupt will
only occur after the last frame and the transmitter will wait, pointing at the next address
after the end address. If additional data has been or is later written to the DPR, a new
message can be started by entering a new end address (and optionally a new start
address). The transmit state-machine will then start the new message and continue
sending data until the new end address has been reached. If the end address of the
message is less than the start address of the message, when the end of the DPR is
reached the transmitter will proceed to the beginning of the DPR and continue until the
end address is reached.
To receive a message the receiver must be enabled, but only the starting address of
the receive buffer is specified. Data will be stored sequentially in the next address after
that starting address and so on until the closing flag is detected. This will latch a
receiver done interrupt status and can cause an interrupt if enabled. The last address
that data was stored in is written to the starting address location for that message-
frame. This allows any received message to be quickly accessed in the received data
by reading the address pointer in the message start location, which points to the end
address of the first message-frame. The memory location following the end of the first
message-frame contains the end address of the second message-frame. This process
can be repeated as many times as needed to find the message of interest. At the end
of each frame, the end address is also latched and can be read from the control
register as a read-only field, but this will be overwritten as subsequent frames complete.
The transmit interrupt is mapped to the first interrupt line of the selected channel, the
transmit frame done interrupt is mapped to the second interrupt line, the receive
interrupt is mapped to the third interrupt line and the abort received interrupt is mapped
to the fourth interrupt line of the selected channel.
When a frame completes and no more message-frames are pending, the bus can stay
active by continually sending flags or it can go idle by sending ones. The SDLC Idle
After Frame Done control bit determines this behavior for the transmitter. If this bit is
not set and the bus remains active by sending multiple flags, the Repeated Flags Share
Zero control bit determines whether the transmitter sends a ‘0111111001111110’ or a
‘011111101111110’ pattern while waiting for a new message-frame to be requested.
When the transmitter is disabled the bus defaults to a high state, which is equivalent to
the idle condition.

Embedded Solutions Page 11 of 37
The PLL is configured to supply a 48 MHz signal on its clock A output. This is used to
sample the transmit reference clock to detect transitions. These transitions are used to
determine when to drive the next data bit onto the transmit data I/O line. The
transmitter clock reference can be supplied by an external source or an internal clock
reference provided by PLL clock B. For test purposes, a substitute external clock is
created by routing the output from PLL clock B onto I/O 32 and 33 configured as
outputs. These clocks may be connected externally to any or all selected channels for
loopback testing. A control bit in each channels control register is used to select
between these two options. When the internal clock mode is selected the transmit
clock line is configured as an output, but when the external clock mode is selected the
transmit clock line is configured as an input. The transmit data line is always an output
and the receive clock and data lines are always inputs.

Embedded Solutions Page 12 of 37
Address Map
BIS3_BASE 0x0000 0 Base control register
BIS3_ID 0x0004 1 ID register
BIS3_IO_DATA 0x0010 4 Data register 31 - 0
BIS3_IO_DIR 0x0014 5 Direction register 31 - 0
BIS3_IO_TERM 0x0018 6 Termination register 31 - 0
BIS3_IO_MUX 0x001C 7 Mux register 31 - 0
BIS3_IO_UCNTL 0x0020 8 Upper control register 33, 32
BIS3_SWITCH 0x0024 9 User switch value
BIS3_PLL_CMD 0x0028 10 PLL control register and read-back of PLL data
BIS3_PLL_RDBK 0x002C 11 PLL control register read-back
BIS3_SDLC_CNTL_0 0x0040 16 Chan 0 SDLC control read/write port
BIS3_SDLC_CNTL_1 0x0050 20 Chan 1 SDLC control read/write port
BIS3_SDLC_CNTL_2 0x0060 24 Chan 2 SDLC control read/write port
BIS3_SDLC_CNTL_3 0x0070 28 Chan 3 SDLC control read/write port
BIS3_SDLC_CNTL_4 0x0080 32 Chan 4 SDLC control read/write port
BIS3_SDLC_CNTL_5 0x0090 36 Chan 5 SDLC control read/write port
BIS3_SDLC_CNTL_6 0x00A0 40 Chan 6 SDLC control read/write port
BIS3_SDLC_CNTL_7 0x00B0 44 Chan 7 SDLC control read/write port
BIS3_IO_RDBK 0x00C0 48 External I/O read register
BIS3_IO_RDBKUPR 0x00C4 49 External I/O upper bits read register
BIS3_INT_STAT 0x00CC 51 Interrupt status and clear register
BIS3_I2OAR 0x00D4 53 I2O address storage register
BIS3_TX_MEM_0 0x01000 Dual-port RAM 0 read/write port
BIS3_RX_MEM_0 0x02000 Dual-port RAM 1 read/write port
BIS3_TX_MEM_1 0x03000 Dual-port RAM 2 read/write port
BIS3_RX_MEM_1 0x04000 Dual-port RAM 3 read/write port
BIS3_TX_MEM_2 0x05000 Dual-port RAM 4 read/write port
BIS3_RX_MEM_2 0x06000 Dual-port RAM 5 read/write port
BIS3_TX_MEM_3 0x07000 Dual-port RAM 6 read/write port
BIS3_RX_MEM_3 0x08000 Dual-port RAM 7 read/write port
BIS3_TX_MEM_4 0x09000 Dual-port RAM 8 read/write port
BIS3_RX_MEM_4 0x0A000 Dual-port RAM 9 read/write port
BIS3_TX_MEM_5 0x0B000 Dual-port RAM 10 read/write port
BIS3_RX_MEM_5 0x0C000 Dual-port RAM 11 read/write port
BIS3_TX_MEM_6 0x0D000 Dual-port RAM 12 read/write port
BIS3_RX_MEM_6 0x0E000 Dual-port RAM 13 read/write port
BIS3_TX_MEM_7 0x0F000 Dual-port RAM 14 read/write port
BIS3_RX_MEM_7 0x10000 Dual-port RAM 15 read/write port
FIGURE 3 PMC BISERIAL-III SDLC INTERNAL ADDRESS MAP
The address map provided is for the local decoding performed within the PMC BiSerial-
III-SDLC. The addresses are all offsets from a base address, which is assigned by the
system when the PCI bus is configured.

Embedded Solutions Page 13 of 37
Programming
Programming the PMC BiSerial-III-SDLC requires only the ability to read and write data
from the host. The base address of the module refers to the first user address for the
slot in which the PMC is installed. This address is determined during system
configuration of the PCI bus.
Depending on the software environment it may be necessary to set-up the system
software with the PMC BiSerial-III "registration" data. For example in WindowsNT there
is a system registry, which is used to identify the resident hardware.
In order to receive data the software is only required to initialize the receiver buffer start
address and enable the Rx channel. To transmit the software will need to load the
message into the appropriate Dual Port RAM, set the transmitter buffer start and end
address and any configuration parameters and enable the transmitter.
When a received message completes, the end address of the message will be written
to the receiver buffer start address with the received data stored starting with the next
address. The next message will be stored starting with the following address unless a
new starting address has been written after the first message has begun. The end
address of each received message can also be read from the address field of the
channel control register, but this will be over-written when the next message completes.
Once the transmitter starts sending a message, a new end address (and optionally a
new start address) can be written to send subsequent messages. Multiple messages
can be loaded into the transmitter RAM and sent in any order desired.
The interrupt service routine should be loaded and the interrupt mask set. The interrupt
service routine can be configured to respond to the channel interrupts on an individual
basis. After the interrupt is received, the data can be retrieved. An efficient loop can
then be implemented to fetch the data. New messages can be received even as the
current one is read from the Dual Port RAM.
The TX interrupt indicates that a message has been sent and that the message has
completed. If more than one interrupt is enabled, then the interrupt service routine
(ISR) needs to read the status to see which source caused the interrupt. The status
bits are latched, and are explicitly cleared by writing a one to the corresponding bit. It is
a good idea to read the status register and write that value back to clear all the latched
interrupt status bits before starting a transfer. This will insure that the interrupt status
values read by the ISR came from the current transfer.
VendorId = 0xDCBA, CardId = 0x005A
Flash design ID = 0x0003, Current Flash revision = 0x0002

Embedded Solutions Page 14 of 37
Register Definitions
BIS3_BASE
[$00] BiSerial III Base Control Register Port read/write
Base Control Register
DATA BIT DESCRIPTION
31-4 Spare
3 I2O CLR
2 I2O EN
1 Interrupt Set
0 Interrupt Enable Master
FIGURE 4 PMC BISERIAL-III SDLC BASE CONTROL REGISTER BIT MAP
All bits are active high and are reset on power-up or reset command.
Interrupt Enable Master: When '1' allows interrupts generated by the
PMC-BiSerial-III-SDLC to be driven onto the carrier (INTA). When '0' the interrupts can
be individually enabled and used for status without driving the backplane. Polled
operation can be performed in this mode.
Interrupt Set: When '1' and the Master is enabled, this bit forces an interrupt request.
This feature is useful for testing and software development.
I2O EN: When ‘1’ allows the I2O interrupts to be activated. Interrupt requests are
routed to the address stored in the I2O Address Register (I2OAR). When ‘0’ the I2O
function is disabled.
I2O CLR: When ‘1’ this bit will cause the current data stored in the I2O collection
register to be cleared. It is recommended that this register clear bit be used
immediately before enabling I2O operation to prevent previously stored events from
causing interrupts.

Embedded Solutions Page 15 of 37
BIS3_ID
[$04] BiSerial III FLASH status/Driver Status Port read only
Design Number / FLASH Revision
DATA BIT DESCRIPTION
31-16 Design/Driver ID
15-0 FLASH revision
FIGURE 5 PMC BISERIAL-III SDLC DESIGN ID REGISTER BIT MAP
The Design/Driver ID for the SDLC project is 0x0003. The FLASH revision is currently
0x0001, but will be updated as features are added or revisions made.
BIS3_IO_DATA
[$10] BiSerial III Parallel Data Output Register read/write
Parallel Data Output Register
DATA BIT DESCRIPTION
31-0 parallel output data
FIGURE 6 PMC BISERIAL-III SDLC PARALLEL OUTPUT DATA BIT MAP
There are 32 potential output bits in the parallel port. The Direction, Termination, and
Mux Control registers are also involved. When the direction is set to output, and the
Mux control set to parallel port the bit definitions from this register are driven onto the
corresponding parallel port lines.
This port is direct read/write of the register. The I/O side is read-back from the
BIS3_IO_RDBK port. It is possible that the output data does not match the I/O data in
the case of the Direction bits being set to input or the Mux control set to state-machine.

Embedded Solutions Page 16 of 37
BIS3_IO_DIR
[$14] BiSerial III Direction Port read/write
Direction Control Port
DATA BIT DESCRIPTION
31-0 Parallel Port Direction Control bits
FIGURE 7 PMC BISERIAL-III SDLC DIRECTION CONTROL PORT
When set (‘1’) the corresponding bit in the parallel port is a transmitter. When cleared
(‘0’) the corresponding bit is a receiver. The corresponding Mux control bits must also
be configured for parallel port.
BIS3_IO_TERM
[$18] BiSerial III Termination Port read/write
Termination Control Port
DATA BIT DESCRIPTION
31-0 Parallel Port Termination Control bits
FIGURE 8 PMC BISERIAL-III SDLC TERMINATION CONTROL PORT
When set (‘1’) the corresponding I/O line will be terminated. When cleared (‘0’) the
corresponding I/O line is not terminated. These bits are independent of the Mux control
definitions. When a bit is set to be terminated; the analog switch associated with that
bit is closed to create a parallel termination of approximately 100 Ω. In most systems
the receiving side is terminated, and the transmitting side is not. The drivers can
handle termination on both ends.

Embedded Solutions Page 17 of 37
BIS3_IO_MUX
[$1C] BiSerial III Mux Port read/write
Multiplexor Control Port
DATA BIT DESCRIPTION
31-0 Parallel Port Mux Control bits
FIGURE 9 PMC BISERIAL-III SDLC MUX CONTROL PORT
When set (‘1’) the corresponding bit is set to State-Machine control. When cleared (‘0’)
the corresponding bit is set to parallel port operation. The Mux control definition along
with the Data, Direction and Termination registers allows for a bit-by-bit selection of
operation under software control.
BIS3_IO_UCNTL
[$20] BiSerial III Upper Control Port read/write
Upper Bits Control Port
DATA BIT DESCRIPTION
25-24 Mux 33, 32
17-16 Termination 33, 32
9-8 Direction 33, 32
1-0 Data 32, 32
FIGURE 10 PMC BISERIAL-III SDLC UPPER CONTROL PORT
The BiSerial III has 34 transceivers. The upper control bits are concentrated within this
register to cover the top 2 bits not controlled within the other control registers. The
upper bits are only useable on the Bezel I/O connector. Pn4 has only 64 connections
and doesn’t support the upper lines. The definitions are the same as the Data, Term,
Dir and Mux port definitions for bit operation.
Data = Data transmitted when the Mux is set to ‘0’ and the direction is set to ‘1’.
Termination when set to ‘1’ causes the parallel termination to be engaged. Setting the
Mux control bits to ‘0’ creates a parallel port for those bits. Setting the Mux control bits
to ‘1’ enables the state-machine to control the direction and data lines. The termination
control is independent.

Embedded Solutions Page 18 of 37
BIS3_IO_RDBK
[$C0] BiSerial III I/O Read-Back Port read only
I/O Read-Back Port
DATA BIT DESCRIPTION
31-0 I/O Data 31-0
FIGURE 11 PMC BISERIAL-III SDLC I/O READBACK PORT
The I/O lines can be read at any time. The value is not filtered in any way. If the
transceivers are set to TX by the parallel port or state-machine then the read-back
value will be the transmitted value. If the transceivers are set to receive then the port
values will be those received by the transceivers from the external I/O.
BIS3_IO_RDBKUPR
[$C4] BiSerial III I/O Upper Read-Back Port read only
I/O Upper Read-Back Port
DATA BIT DESCRIPTION
1-0 I/O Data 33-32
FIGURE 12 PMC BISERIAL-III SDLC I/O READBACK PORT
The I/O lines can be read at any time. The value is not filtered in any way. If the
transceivers are set to TX by the parallel port or state-machine then the read-back
value will be the transmitted value. If the transceivers are set to receive then the port
values will be those received by the transceivers from the external I/O. The upper bits
are presented on this port.

Embedded Solutions Page 19 of 37
1
7 0
0
BIS3_SWITCH
[$24] BiSerial III Switch Port read only
User Switch Port
DATA BIT DESCRIPTION
31-24 Spare
23-16 sw7-0
15-0 Spare
FIGURE 13 PMC BISERIAL-III SDLC SWITCH PORT
The Switch Read Port has the user bits. The user bits are connected to the eight dip-
switch positions. The switches allow custom configurations to be defined by the user
and for the software to identify a particular board by its switch settings and to configure
it accordingly.
The Dip-switch is marked on the silk-screen with the positions of
the digits and the '1' and '0' definitions. The numbers are hex
coded. The example shown would produce 0x12 when read (and
shifted down).

Embedded Solutions Page 20 of 37
BIS3_PLL_CMD, PLL_RDBK
[$28, 2C] BiSerial III PLL Control
PLL Command Register, PLL CMD Read-back
DATA BIT DESCRIPTION
3 PLL Enable
2 PLL S2
1 PLL SCLK
0 PLL SDAT
FIGURE 14 PMC BISERIAL-III SDLC PLL CONTROL
The register bits for PLL Enable, PLL S2, and PLL SCLK are unidirectional from the
Xilinx to the PLL –always driven. SDAT is open drain. The SDAT register bit when
written low and enabled will be reflected with a low on the SDAT signal to the PLL.
When SDAT is taken high or disabled the SDAT signal will be tri-stated by the Xilinx,
and can be driven by the PLL. The SDAT register bit when read reflects the state of the
SDAT signal between the Xilinx and PLL and can be in a different state than the written
SDAT bit. To read back the contents of the CMD port use the RDBK port.
PLL Enable: When this bit is set to a one, SDAT is enabled. When set to ‘0’ SDAT is
tri-stated by the Xilinx.
PLL SCLK/SDAT: These signals are used to program the PLL over the I2C serial
interface. SCLK is always an output whereas SDAT is bi-directional. When SDAT is to
be read from the PLL
PLL S2: This is an additional control line to the PLL that can be used to select
alternative pre-programmed frequencies.
The PLL is a separate device controlled by the Xilinx. The PLL has a fairly complex
programming requirement which is simplified by using the Cypress® CyberClocks utility,
and then programming the resulting control words into the PLL using this PLL Control
port. The interface can be further simplified by using the Dynamic Engineering driver to
take care of the low-level bit manipulation requirements.