ELTEC BAB 912 Operator's manual

PowerPC 750 Based PCI Real-Time CPU Board
hardware documentation
linux documentation
Revision 0B

Revision
Revision Changes Date / Name
0A First Edition 2003 GM/UW
0B Disclaimer new 08.11.06 hh

DISCLAIMER
Copyright
© 2006 ELTEC Elektronik AG. The information, data, and figures in this document including respective references have
been verified and found to be legitimate. In particular in the event of error they may, therefore, be changed at any time
without prior notice. The complete risk inherent in the utilization of this document or in the results of its utilization
shall be with the user; to this end, ELTEC Elektronik AG shall not accept any liability. Regardless of the applicability of
respective copyrights, no portion of this document shall be copied, forwarded or stored in a data reception system or
entered into such systems without the express prior written consent of ELTEC Elektronik AG, regardless of how such acts
are performed and what system is used (electronic, mechanic, photocopying, recording, etc.). All product and company
names are registered trademarks of the respective companies.
Our General Business, Delivery, Offer, and Payment Terms and Conditions shall otherwise apply.
Federal communications commission statement
Þ This device complies with FCC Rules Part 15. Operation is subject to the following two conditions:
Þ This device may not cause harmful interference, and
Þ This device must accept any interference received including interference that may cause undesired operation.
Þ This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15
of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a
residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed
and used in accordance with manufacturer’s instructions, may cause harmful interference to radio communications.
However, there is no guarantee that interference will not occur in a particular installation. If this equipment does
cause harmful interference to radio or television reception, which can be determined by turning the equipment off
and on, the user is encouraged to try correct the interference by one or more of the following measures:
Þ Reorient or relocate the receiving antenna.
Þ Increase the separation between the equipment and receiver.
Þ Connect the equipment to an outlet on a circuit different from that to which the receiver is connected.
Þ Consult the dealer or an experienced radio/TV technician for help.
Þ The us of shielded cables for connection of the monitor to the graphics card is required to assure compliance with
FCC regulations. Changes or modifications to this unit not expressly approved by the party responsible for
compliance could void the user’s authority to operate this equipment.
Canadian department of communications statement
Þ This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in
the Radio Interference Regulations of the Canadian Department of Communications.
Þ This class B digital apparatus complies with Canadian ICES-003
SAFETY INFORMATION
Electrical safety
Þ To prevent electrical shock hazard, disconnect the power cable from the electrical outlet before reloading the
system.
Þ When adding or removing devices to or from the system, ensure that the power cables for the devices are
unplugged before the signal cables are connected. If possible, disconnect all power cables from the existing system
before you add device.
Þ Before connecting or removing signals cables from motherboard, ensure that all power cables are unplugged.

Þ Make sure that your power supply is set to the correct voltage in your area. If you are not sure about the voltage of
the electrical outlet you are using, contact your local power company.
Þ If the power supply is broken, do not try to fix it by yourself. Contact a qualified service technician or your retailer.
Operation safety
Þ Before installing the motherboard and adding devices on it, carefully read the manuals that came with the
package.
Þ Before using the product, make sure all cables are correctly connected and the power cables are not damaged. If
you detect any damage, contact your dealer immediately.
Þ To avoid short circuits, keep paper clips, screws, and staples away from connectors, slots sockets and circuitry.
Þ Avoid dust, humidity, and temperature extremes. Do not place the product in any area where it may become wet.
Þ Place the product on a stable surface.
Þ If you encounter technical problems with the product, contact a qualified service technician or your retailer.
EMC Rules
This unit has to be installed in a shielded housing. If not installed in a properly shielded enclosure, and used in
accordance with the instruction manual, this product may cause radio interference in which case the user may be
required to take adequate measures at his or her own expense.
IMPROTANT INFORMATION
This product is not an end user product. It was developed and manufactured for further processing by trained personnel.
RECYCLING
Please recycle packaging environmentally friendly:
Packaging materials are recyclable. Please do not dispose packaging into domestic waste but recycle it.
Please recycle old or redundant devices environmentally friendly:
Old devices contain valuable recyclable materials that should be reutilized. Therefore please dispose
.... old devices at collection points which are suitable.

Table of Contents
Disclaimer/Copyrightnotice i
Aboutthisdocument ii
Hardwarepart iii
1.Specification 4
1.1.MainFeatures 4
1.2.SpecificationDetails 4
1.2.1.CPUKernel 4
1.2.2.MemoryConfiguration 4
1.2.3.Chipset 4
1.2.4.BootPROM 5
1.2.5.EthernetInterface 5
1.2.6.SerialI/O 5
1.2.7.PCISAInterface 5
1.2.8.Timer 5
1.2.9.Non-volatileMemory/RTC 6
1.2.10.Operatingsystems 6
1.2.11.On-boardI/O 6
1.2.12.Miscellaneous 6
1.2.13.RelatedDocuments 6
1.2.14.BlockDiagram 7
2.Installation 8
2.1.What'sneededforInstallation 8
2.2.SODIMMInstallation 8
2.3.StatusLEDs 8
2.4.EthernetStatusLEDs 9
2.5.BAB912I/O 10
3.ConnectorAssignments 11
3.1.FrontPanelConnectors 11
3.1.1.EthernetConnector 11
3.1.2.SerialPorts1and2Connectors 11
3.2.PISAConnector 11
4.BoardParameters 14
4.1.HostBus 14
4.2.PCILocalBus 14
4.3.Network 14
4.4.SerialI/O 14
4.5.MTBFValues 14
4.6.ESDValues 15
4.7.EnvironmentalConditions 15
4.8.MaximumOperatingHumidity: 15
4.9.PowerRequirements 15
5.Jumpers 16
5.1.On-boardJumpers 16
5.1.1.User-settableJumpers 16
LINUXpart xvii
6.Prepareyourdevelopementsystem 18
6.1.Serialterminalprogram 18
6.1.1.InstallationofminicomunderSuSELinux 18
6.1.2.Minicomsetup 18
6.2.Bootpserver 20
6.2.1.InstallingthebootpdaemonunderSuSELinux 20
6.2.2.Importantconfigurationfiles 20
6.2.3.Restartinginetd 21
iv

6.3.ELinOSInstallation 21
6.4.InstallationofBAB912kernelsources 21
6.5.BAB912sampleprojects 22
6.6.Downloadingandrunningthesampleproject 23
7.U-Boot 24
7.1.WhatisPPCBoot/U-Boot? 24
7.2.CommonU-Bootcommands 24
7.3.U-BootEnvironment 25
7.3.1.StandardEnvironment 25
7.3.2.ExtentedEnvironment 27
7.4.Flash-ROMmappingforBAB912 28
7.5.StandaloneBoot 28
7.6.U-BootUpdate 29
8.UsingELinOSdemonstrationprojects 30
8.1.Cloningaproject 30
A.Appendix 36
A.1.DescriptionofOn-boardDevices 36
A.2.MemoryAddressMap 36
A.3.InterruptController 37
A.3.1.Watchdog 37
A.3.2.ConfigurationSwitch 38
A.3.3.StatusDisplay 38
A.3.4.NonVolatileRAM 39
A.3.5.SerialController 39
A.3.6.SoftReset 39
BAB 912
v

List of Tables
2.1.EthernetStatusLEDs 9
3.1.ETHERNET(8-pinTelephoneJackConnector) 11
3.2.COM1,COM2(9-pinmin-DConnector) 11
3.3.PISAConnector 11
5.1.BootROMSelect(J1001_1) 16
5.2.AuxilaryROMSelect(J1001_2) 16
7.1.CommonU-Bootcommands 24
7.2.StandardU-Bootenvironment 25
7.3.ExtentedU-Bootenvironment(ELTEC) 27
7.4.BAB912FlashROMmapping 28
A.1.MemoryAddressMap 36
A.2.WatchdogAddressAssignment 37
A.3.ConfigurationSwitchAddressAssignment 38
A.4.StatusDisplayAddressAssignment 38
A.5.NonVolatileRAMAddressAssignment 39
vi

About this document
This document describes the ELTEC BAB912 running under LINUX.
The BAB912 is a PowerPC based PCISA board for use in a passive backplane.
Chapter 1 to 5 describe the hardware of the BAB912 in detail.
Chapter 6 describes how to prepare your development system for ELINOS cross development. It explains
the first steps needed to compile and start the sample project available.
Chapter 7 describes the bootloader PPC Boot / U-Boot and its configuration.
Chapter 8 shows how to clone ELinOS sample projects and use them with the BAB912.
ii

Hardware part
iii

Chapter 1. Specification
1.1. Main Features
• PowerPC-based PCISA CPU board
• PCI master interface
• CPU PowerPC 750FX 600 - 1000 MHz
• 512 KB on-chip L2-cache
• Up to 256 MByte SDRAM on SODIMM
• Two 10 / 100 Mbit/s network interface (10BaseT / 100BaseTX)
• Two serial channels
• 8 KB NVRAM with RTC for storing application- / process-data
• PCISA (PISA) format with PCI interface for up to 4 slots
• Embedded Linux, VxWorks, OS-9 BSP support
• IDE Controller, one channel for CompactFlash, the other for ATA disks
1.2. Specification Details
The BAB 912 is a PowerPC-based single board computer with a PCISA interface. The small format
permits setting up small industrial realtime systems. The board is based on the Motorola MPC 107 chip,
the reference for PowerPC designs. Also, availability for longer periods than what is common in the PC
market is guaranteed.
1.2.1. CPU Kernel
An up-to-date PowerPC CPU is supported: PowerPC 750FX, compatible to the PowerPC 750 at 600
MHz. The CPU has FPU, MMU, first level cache (32KB each for instruction and data) and a L2 cache
(512 KB unified) on the chip. It contains dual integer units, that can operate in parallel for certain
instructions; the floating point unit is optimized for fast single precision multiply-add operations.
Performance is characterized by the SPECint numbers of 39.9 and SPECfp 21.8 at 900 MHz.
1.2.2. Memory Configuration
The 64-bit wide memory allows configurations of up to 256 (512 when available) MByte with 100 MHz
SDRAMs in a single SODIMM module. The implementation in SODIMM has been selected due to the
smaller size and thus shorter signals, compared to standard DIMM modules. Memory size is detected
automatically. The second-level cache, due to its location in the CPU itself, runs with the full CPU clock.
1.2.3. Chip set
The chip set, a Motorola MPC 107, contains the SDRAM memory controller, the interrupt controller, and
the PCI host bridge for 32-bit/33-MHz PCI. Additionally, it has logic to access an 8-bit wide ROM, it has
timers, a DMA controller, and it generates clocks.
4

1.2.4. Boot PROM
Boot code is stored in a Flash EPROM (size 4 MB) which enables easy code updates.
The current boot proms contains the "PPCBoot/U-Boot" boot loader with self test code, PCI initialization
routines, as well as code for starting operating systems via Ethernet (BootP/DHCP), from IDE, or from
User Flash memory. Operating systems that can be booted this way include Elinos (Embedded Linux),
OS-9, and PxROS. Additionally there are 4 MB user Flash EPROM.
1.2.5. Ethernet Interface
The network interface uses two network controller: i82559ER for 10/100 Mbit/s transfers with 10BaseT
(twisted pair) or 100Base TX connectivity. Automatic speed detection is included. A Link LED and an
Activity LED allow an easy check whether the Ethernet connection works.
1.2.6. Serial I/O
Two asynchronous 16550-compatible serial channels with up to 115 KBaud transfer rate and 16-byte
FIFO with RS232 levels are available.
1.2.7. PCISA Interface
The PCISA interface is implemented with system slot capabilities for 32-bit PCI systems. It features
transfer rates of up to 128 MByte/s between board-internal resources and PCISA devices. The PCISA
interface uses only the PCI bus signals. The board must occupy the PCI system slot and it will set up all
PCI peripherals on the PCI back plane. The board can drive PCI buses (passive back planes) with up to 4
peripheral slots, all of them can obtain bus mastership (DMA).
1.2.8. Timer
The BAB 912 has four programmable timers, located in the MPC 107, for timing interrupts in the 1 µs to
1000 ms range. Three of these timers are intended for use with user-written drivers, they are not used by
the operating system or the BSP, one may be used by the OS. The additional CPU-internal decrementer
is used for generating the OS ticker interrupt.
Chapter 1. Specification
5

1.2.9. Non-volatile Memory / RTC
A real-time clock chip (M48T59) supplies time-of-day data, a crucial feature for networked file systems.
The same chip also has non-volatile memory (4 kB available for the user). Data transfer rate is 5 MByte/s.
Only byte-access is allowed.
1.2.10. Operating systems
Compliant with the ELTEC Linux Initiative, the BAB 912 supports implementations of Elinos and PxROS -
applications for both operating systems can be designed under Linux. Elinos is best when an Embedded
Linux is needed with a compact implementation and full Linux capabilities. PxROS is for hard real-time
applications with the smallest footprint.
Other software support for the BAB 912 includes the board support package for Enhanced OS-9 for
PowerPC.
1.2.11. On-board I/O
All on-board-I/O (2 * serial and 2 * 100BaseTx) is routed to the front panel.
1.2.12. Miscellaneous
Due to the use of a PCISA connector the number of external PCI slots is limited to 4. If more than 4
external slots are needed, a back plane with an integrated PCI-PCI bridge must be used.
1.2.13. Related Documents
IBM PowerPC 750FX RISC Microprocessor User's Manual. This is the CPU manufacturer's description of
the PowerPC itself and the assembly language command set. Motorola MPC 107 PCI Bridge/Memory
Controller User's Manual.
Chapter 1. Specification
6

1.2.14. Block Diagram
Chapter 1. Specification
7

Chapter 2. Installation
2.1. What's needed for Installation
The BAB 912 must be installed into a PCISA backplane. A terminal (or a PC with a terminal emulator
program) connected to serial #1 and set to 9600 baud, 8 bit, no parity, is needed to check boot messages
and to change boot settings. If the operating system is booted over Ethernet, a network connection is
needed.
2.2. SODIMM Installation
The BAB 912 requires one 144-pin SODIMM SDRAM module, that supports CAS-latency 2 at 100 MHz,
to be fitted into the SODIMM socket X701. These modules are currently available with a capacity of up to
256 Mbyte. In the near future there may also be 512 Mbyte modules that are supported by the BAB 912.
The firmware reads the type and size of the SODIMM from the SPD (Serial Presence Detect) EEPROM
installed on the memory module, and tests the module. If the test fails or the firmware reports the wrong
size the module is not suitable for the BAB 912.
2.3. Status LEDs
There are six status LEDs on the BAB 912. The LEDs are controlled by software.
8

2.4. Ethernet Status LEDs
At the ethernet connector there are two LEDs indicating link status and network activity.
Table 2.1. Ethernet Status LEDs
LED Color Description
Activity Green Ethernet1: HD or CF activity
Ethernet2: Board power ok; network not initialized or no link pulses
Yellow Network activity
off Link pulses detected; no network activity
Link Green 100 Mbit/s link pulses detected
Yellow 10 Mbit/s link pulses detected
off No link pulses detected
Chapter 2. Installation
9

2.5. BAB 912 I/O
Connection Diagram
Chapter 2. Installation
10

Chapter 3. Connector Assignments
Please check the connector assignments before using any interface.
3.1. Front Panel Connectors
3.1.1. Ethernet Connector
Table 3.1. ETHERNET (8-pin Telephone Jack Connector)
Pin Signal
1 TXD+
2 TXD-
3 RXD+
4 nc
5 nc
6 RXD-
7 nc
8 nc
3.1.2. Serial Ports 1 and 2 Connectors
Table 3.2. COM1, COM2 (9-pin min-D Connector)
Pin Signal
1 DCD
2 RXD
3 TXD
4 DTR
5 GND
6 DSR
7 RTS
8 CTS
9 RI
3.2. PISA Connector
Table 3.3. PISA Connector
Pin ISA-Bus top layer up
row ISA-Bus bot layer up row PCIbus top layer low row PCIbus bot layer low row
1 GND I2CLK I2DAT
2 GND GND
11

Pin ISA-Bus top layer up
row ISA-Bus bot layer up row PCIbus top layer low row PCIbus bot layer low row
3 VCC INTB# INTA#
4 INTD# INTC#
5 VCC VCC
6
7 -12V VCC VI/O
8 PCIRST# PCICLK2
9 +12V GNT#0 GND
10 GND REQ#0 GNT#1
11 GND GND
12 PCICLK1 REQ#1
13 GND AD31
14 REQ#2 PCICLK3
16
17 GNT#2 PCICLK4
18 AD28 AD27
19 AD26 AD25
20 AD24 CBE#3
21 AD22 AD23
22 AD20 AD21
23 AD18 AD19
24 PWRGDIN REQ#3
25
26 GND GNT#3
27 AD16 AD17
28 FRAME# IRDY#
29 VCC CBE#2 DEVSEL#
30 TRDY# LOOK#
31 GND STOP# PERR#
32
33 GND SERR#
34 AD15
35 CBE#1 AD14
36 PAR AD12
37 GND GND
38
39 GND M66EN
40 AD13 AD10
41 AD11 AD8
42 AD9 AD7
43 CBE#0 AD5
Chapter 3. Connector Assignments
12

Pin ISA-Bus top layer up
row ISA-Bus bot layer up row PCIbus top layer low row PCIbus bot layer low row
44 AD6 AD3
45 AD4 AD1
46 AD2 AD0
47
48 VCC VI/O
49 VCC VCC
50 VCC GND GND
51 GND GND
52 GND
Chapter 3. Connector Assignments
13

Chapter 4. Board Parameters
4.1. Host Bus
100 MHz
4.2. PCI Local Bus
CPU to PCI Transfer Options:
Write post buffer
Max. 120 MByte/s (peak)
PCI to Memory Transfer Options:
Max. 120 MByte/s (peak)
Clock Speed:
33.3 MHz
IRQs:
Four PCI interrupts
4.3. Network
10BaseT/100BaseTx (twisted-pair)
Transfer Speed:
max. 10/100 Mbit/s
4.4. Serial I/O
2 Channels:
Full duplex, asynchronous
50 b/s - 115.2 Kbit/s
16 Byte Transmit and Receive FIFO
RS232 level
4.5. MTBF Values
Include one 64 MByte SODIMM:
64568 h(computed after MIL HDBK-217E)
865208 h (realistic value from industry stand experience)
14