Espressif Systems ESP8684 Series Instruction Manual

ESP8684 Series
Hardware Design Guidelines
Introduction
Hardware design guidelines give advice on how to integrate ESP8684 into other products.
ESP8684 is a series of ultra-low-power Wi-Fi and Bluetooth®5 (LE) SoCs.
These guidelines will help to ensure optimal performance of your product with respect to tech-
nical accuracy and conformity to Espressif’s standards.
Version 1.1
Espressif Systems
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Contents
Contents
1 Overview 5
2 Schematic Checklist 6
2.1 Power Supply 7
2.1.1 Digital Power Supply 7
2.1.2 Analog Power Supply 7
2.2 Power-on Sequence and System Reset 8
2.2.1 Power-on Sequence 8
2.2.2 System Reset 8
2.2.3 Power-up and Reset Timing 9
2.3 Flash 9
2.4 Clock Source 9
2.4.1 External Clock Source (compulsory) 9
2.4.2 RTC (optional) 10
2.5 RF 10
2.6 UART 11
2.7 ADC 11
2.8 Strapping Pins 11
2.9 GPIO 12
3 PCB Layout Design 15
3.1 General Principles of PCB Layout 15
3.2 Positioning a Module on a Base Board 15
3.3 Power Supply 17
3.4 Crystal Oscillator 18
3.5 RF 19
3.6 UART 21
3.7 Typical Layout Problems and Solutions 21
3.7.1 Q: The current ripple is not large, but the TX performance of RF is rather poor. 21
3.7.2 Q: The power ripple is small, but RF TX performance is poor. 22
3.7.3 Q: When ESP8684 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. 22
3.7.4 Q: TX performance is not bad, but the RX sensitivity is low. 22
4 Hardware Development 23
4.1 ESP8684 Modules 23
4.2 ESP8684 Development Boards 23
5 Hardware Design Checklist Form 24
6 Related Documentation and Resources 25
Glossary 26
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Contents
Revision History 27
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List of Illustrations
List of Tables
1 Description of ESP8684 Power-up and Reset Timing Parameters 9
2 Strapping Pins 12
3 Parameter Descriptions of Setup and Hold Times for the Strapping Pins 12
4 IO MUX Pin Functions 13
List of Figures
1 ESP8684 Schematic 6
2 Schematic for the Digital Power Supply Pins 7
3 Schematic for the Analog Power Supply Pins 8
4 ESP8684 Power-up and Reset Timing 9
5 Schematic for the Crystal 10
6 Schematic for the Oscillator 10
7 Schematic for RF Matching 11
8 Setup and Hold Times for the Strapping Pins 12
9 ESP8684 PCB Layout 15
10 Placement of ESP8684 Modules on Base Board 16
11 Keepout Zone for ESP8684 Module’s Antenna on the Base Board 17
12 ESP8684 Power Traces in a Four-layer PCB Design 17
13 ESP8684 Analog Power Traces in a Four-layer PCB Design 18
14 ESP8684 Crystal Oscillator Layout 19
15 ESP8684 RF Layout in a Four-layer PCB Design 20
16 ESP8684 PCB Stack up Design 20
17 ESP8684 Stub in a Four-layer PCB Design 21
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1 Overview
1 Overview
Note:
Check the link or the QR code to make sure that you use the latest version of this document:
https://espressif.com/sites/default/files/documentation/esp8684_hardware_design_guidelines_en.pdf
ESP8684 series is an ultra-low-power MCU-based SoC solution that supports 2.4 GHz Wi-Fi and Bluetooth®
Low Energy (Bluetooth LE). With its state-of-the-art power and RF performance, this SoC is an ideal choice for a
wide variety of application scenarios relating to Internet of Things (IoT), smart home, industrial automation, health
care, and consumer electronics.
At the core of this chip is a 32-bit RISC-V single-core processor that operates at up to 120 MHz. The chip
supports application development, without the need for a host MCU.
ESP8684 series provides a highly-integrated way to implement Wi-Fi and Bluetooth LE technologies using a
complete RF subsystem, including a antenna switch, RF balun, power amplifier, low noise amplifier (LNA), filter,
power management unit, calibration circuits, etc. As a result, PCB size has been greatly reduced.
With its advanced calibration circuitry, ESP8684 can dynamically adjust itself to remove external circuit
imperfections or adapt to changes in external conditions. As such, the mass production of ESP8684 series does
not require expensive and specialized Wi-Fi test equipment.
For more information about ESP8684 series, please refer to ESP8684 Series Datasheet.
Note:
Unless otherwise specified, ”ESP8684” used in this document refers to the series of chips, instead of a specific chip
variant.
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2 Schematic Checklist
2 Schematic Checklist
The integrated circuitry of ESP8684 requires only 15 electrical components (resistors, capacitors, and inductors)
and one crystal. The high integration of ESP8684 allows for simple peripheral circuit design. This chapter details
ESP8684 schematics.
ESP8684 schematic is shown in Figure 1.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C8, L2 and C9
vary with the a tual PCB board.
The values of C1 and C2 vary with
the sele tion of the rystal.
The value of R1 varies with the a tual
PCB board.
ESP8684-MINI-1(pin-out)
NC: No omponent. ESP8684H2
ESP8684H1
ESP8684H4
CHIP_EN
GPIO4
GPIO5
GPIO6
U0RXD
ANT
GPIO0
GPIO1
GPIO2
GPIO3
RF_ANT
U0TXD
GPIO2
GPIO3
CHIP_EN
GPIO1 GPIO0 GPIO10 GPIO6 GPIO7 GPIO8 GPIO9
GPIO18
U0RXD
U0TXD
GPIO4 GPIO5
GPIO7
GPIO8
GPIO9
GPIO10
GPIO18
GND
VDD33
GND
GNDGND GND
GND GND
GND
VDD33
GND GNDGND
VDD33
VDD33
GND
GND
GND
GND GND VDD33
GND
GND
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C1
TBD
R1 0(1%)
R2 499(1%)
Y1
40MHz
XIN
1
GND
2XOUT 3
GND 4
L1 2.0nH(0.1nH)
C9
TBD
U2
ANT
1
VDDA3P3
2
VDDA3P3
3
GPIO0
4
GPIO1
5
GPIO2
6
CHIP_EN
7
MTMS
9
MTDI
10
VDD3P3_RTC
11
MTCK
12
MTDO 13
GPIO8 14
GPIO9 15
GPIO10 16
VDD3P3_CPU 17
U0RXD 19
U0TXD 20
XTAL_N 22
XTAL_P 23
GND 25
GPIO3
8VDDA 24
VDDA 21
GPIO18 18
C6
0.1uF/6.3V(10%) D1
ESD
C3
1uF/6.3V(20%)
C4
10nF/6.3V(10%)
C10
0.1uF/6.3V(10%)
C7
0.1uF/6.3V(10%)
ANT1
PCB_ANT
1
2
U3
ESP8684-MINI-1
GND
1
3V3
3
IO9
23
NC
4
IO2
5
IO3
6
NC
7
NC
9
NC
10
NC
15
IO10
16
NC
17
IO4
18
IO5
19
NC 32
TXD0 31
RXD0 30
NC 34
NC 33
IO18 26
NC 29
NC 28
NC 27
IO7
21
IO8
22
IO0
12
IO1
13
GND
52
IO6
20
NC 35
NC
24
EPAD 49
GND
2
GND
53
GND 51
GND 50
EN
8
GND 36 GND 37 GND 38 GND 39 GND 40 GND 41 GND 42 GND 43 GND 44 GND 45 GND 46 GND 47 GND 48
GND
14
GND
11 NC 25
C2
TBD
C8
TBD
C12
0.1uF/6.3V(10%)
L2 TBD
C5
10uF/6.3V(20%)
Figure 1: ESP8684 Schematic
Any basic ESP8684 circuit design may be broken down into the following major sections:
• Power supply
• Power-on sequence and system reset
• Flash
• Clock source
• RF
• UART
• ADC
• Strapping pins
• GPIO
The rest of this document details the specifics of circuit design for each of these sections.
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2 Schematic Checklist
2.1 Power Supply
Details of using power supply pins can be found in Section Power Scheme in ESP8684 Series Datasheet.
2.1.1 Digital Power Supply
ESP8684 has pin 11 VDD3P3_RTC and pin 17 VDD3P3_CPU that supply power to RTC IO and CPU IO
respectively, in a voltage range of 3.0 V ~3.6 V. It is recommended to add an extra 0.1 µF filter capacitor close to
each digital power supply pin.
The schematic for the digital power supply pins is shown in Figure 2.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C8, L2 and C9
vary with the a tual PCB board.
The values of C1 and C2 vary with
the sele tion of the rystal.
The value of R1 varies with the a tual
PCB board.
ESP8684-MINI-1(pin-out)
NC: No omponent.
ESP8684H2
ESP8684H1
ESP8684H4
CHIP_EN
GPIO4
GPIO5
GPIO6
U0RXD
ANT
GPIO0
GPIO1
GPIO2
GPIO3
RF_ANT
U0TXD
GPIO2
GPIO3
CHIP_EN
GPIO1 GPIO0 GPIO10 GPIO6 GPIO7 GPIO8 GPIO9
GPIO18
U0RXD
U0TXD
GPIO4 GPIO5
GPIO7
GPIO8
GPIO9
GPIO10
GPIO18
GND
VDD33
GND
GNDGND GND
GND GND
GND
VDD33
GND GNDGND
VDD33
GND
GND
GND
GND GND VDD33
GND
GND
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C1
TBD
R1 0(1%)
R2 499(1%)
Y1
40MHz
XIN
1
GND
2XOUT 3
GND 4
L1 2.0nH(0.1nH)
C9
TBD
U2
ANT
1
VDDA3P3
2
VDDA3P3
3
GPIO0
4
GPIO1
5
GPIO2
6
CHIP_EN
7
MTMS
9
MTDI
10
VDD3P3_RTC
11
MTCK
12
MTDO 13
GPIO8 14
GPIO9 15
GPIO10 16
VDD3P3_CPU
17
U0RXD 19
U0TXD 20
XTAL_N 22
XTAL_P 23
GND 25
GPIO3
8VDDA 24
VDDA 21
GPIO18
18
C6
0.1uF/6.3V(10%) D1
ESD
C3
1uF/6.3V(20%)
C4
10nF/6.3V(10%)
C10
VDD33
C7
0.1uF/6.3V(10%)
ANT1
PCB_ANT
1
2
U3
ESP8684-MINI-1
GND
1
3V3
3
IO9
23
NC
4
IO2
5
IO3
6
NC
7
NC
9
NC
10
NC
15
IO10
16
NC
17
IO4
18
IO5
19
NC 32
TXD0 31
RXD0 30
NC 34
NC 33
IO18 26
NC 29
NC 28
NC 27
IO7
21
IO8
22
IO0
12
IO1
13
GND
52
IO6
20
NC 35
NC
24
EPAD 49
GND
2
GND
53
GND 51
GND 50
EN
8
GND 36 GND 37 GND 38 GND 39 GND 40 GND 41 GND 42 GND 43 GND 44 GND 45 GND 46 GND 47 GND 48
GND
14
GND
11 NC 25
C2
TBD
C8
TBD
C12
0.1uF/6.3V(10%)
L2 TBD
C5
10uF/6.3V(20%)
0.1uF/6.3V(10%)
Figure 2: Schematic for the Digital Power Supply Pins
2.1.2 Analog Power Supply
Pin 2 and 3 (both labelled VDDA3P3), pin 21 and 24 (both VDDA) are the analog power supply pins, working at
3.0 V ~3.6 V.
It should be noted that the sudden increase in current draw, when ESP8684 is transmitting signals, may cause a
power rail collapse. Therefore, it is highly recommended to add another 10 µF capacitor to the power trace,
which can work in conjunction with the 0.1 µF capacitor. In addition, a LC filter circuit needs to be added near
VDDA3P3 pins so as to suppress high-frequency harmonics. The recommended rated current of the inductor is
500 mA or above. Refer to Figure 3and place the appropriate decoupling capacitor near each analog power
pin.
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C8, L2 and C9
vary with the a tual PCB board.
The values of C1 and C2 vary with
the sele tion of the rystal.
The value of R1 varies with the a tual
PCB board.
ESP8684-MINI-1(pin-out)
NC: No omponent.
ESP8684H2
ESP8684H1
CHIP_EN
GPIO4
GPIO5
GPIO6
U0RXD
ANT
GPIO0
GPIO1
GPIO2
GPIO3
RF_ANT
U0TXD
GPIO2
GPIO3
CHIP_EN
GPIO1 GPIO0 GPIO10 GPIO6 GPIO7 GPIO8 GPIO9
GPIO18
U0RXD
U0TXD
GPIO4 GPIO5
GPIO7
GPIO8
GPIO9
GPIO10
GPIO18
GND
VDD33
GND
GNDGND GND
GND GND
GND
VDD33
GND GNDGND
VDD33
VDD33
GND
GND
GND
GND GND VDD33
GND
GND
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C1
TBD
R2 499(1%)
R1 0(1%)
Y1
40MHz
XIN
1
GND
2XOUT 3
GND 4
L1 2.0nH(0.1nH)
D1
ESD
C6
0.1uF/6.3V(10%)
U2
ANT
1
VDDA3P3
2
VDDA3P3
3
GPIO0
4
GPIO1
5
GPIO2
6
CHIP_EN
7
MTMS
9
MTDI
10
VDD3P3_RTC
11
MTCK
12
MTDO 13
GPIO8 14
GPIO9 15
GPIO10 16
VDD3P3_CPU 17
U0RXD 19
U0TXD 20
XTAL_N 22
XTAL_P 23
GND 25
GPIO3
8VDDA 24
VDDA 21
GPIO18 18
C9
TBD
C3
1uF/6.3V(20%)
C10
0.1uF/6.3V(10%)
C4
10nF/6.3V(10%)
U3
ESP8684-MINI-1
GND
1
3V3
3
IO9
23
NC
4
IO2
5
IO3
6
NC
7
NC
9
NC
10
NC
15
IO10
16
NC
17
IO4
18
IO5
19
NC 32
TXD0 31
RXD0 30
NC 34
NC 33
IO18 26
NC 29
NC 28
NC 27
IO7
21
IO8
22
IO0
12
IO1
13
GND
52
IO6
20
NC 35
NC
24
EPAD 49
GND
2
GND
53
GND 51
GND 50
EN
8
GND 36 GND 37 GND 38 GND 39 GND 40 GND 41 GND 42 GND 43 GND 44 GND 45 GND 46 GND 47 GND 48
GND
14
GND
11 NC 25
ANT1
PCB_ANT
1
2
C7
0.1uF/6.3V(10%)
C8
TBD
C2
TBD
C12
0.1uF/6.3V(10%)
C5
10uF/6.3V(20%)
L2 TBD
Figure 3: Schematic for the Analog Power Supply Pins
Notice:
• The recommended power supply voltage for ESP8684 is 3.3 V and the output current is no less than 500 mA.
• It is suggested to add an ESD protection diode at the power entrance.
2.2 Poweron Sequence and System Reset
2.2.1 Poweron Sequence
ESP8684 uses a 3.3 V system power supply. The chip should be activated after the power rails have stabilized.
This is achieved by delaying the activation of CHIP_EN after the 3.3 V rails have been brought up. More details
can be found in Section 2.2.3.
Notice:
To ensure that stable power is supplied to the chip during power-up, it is advised to add an RC delay circuit at the CHIP_EN
pin. The recommended setting for the RC delay circuit is usually R = 10 kΩand C = 1 µF. However, specific parameters
should be adjusted based on the power-up timing of the power supply and the power-up and reset sequence timing of
the chip.
2.2.2 System Reset
CHIP_EN serves as the reset pin of ESP8684. The reset voltage (VI L_nRST ) should be in the range of (–0.3 ~
0.25 × VDD) V. VDD is the I/O voltage for a particular power domain of pins. To avoid reboots caused by external
interferences, make the CHIP_EN trace as short as possible. Also, add a pull-up resistor as well as a capacitor to
the ground whenever possible.
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2 Schematic Checklist
Notice:
CHIP_EN pin must not be left floating.
2.2.3 Powerup and Reset Timing
Figure 4shows the power-up and reset timing of ESP8684 series of SoCs. Details about the parameters are
listed in Table 1.
VDDA,
VDDA3P3,
VDD3P3_RTC,
VDD3P3_CPU
CHIP_EN
t0t1
VIL_nRST
2.8 V
Figure 4: ESP8684 Powerup and Reset Timing
Table 1: Description of ESP8684 Powerup and Reset Timing Parameters
Min
Parameter Description (µs)
t0
Time between bringing up the VDDA, VDDA3P3, VDD3P3_RTC, and
VDD3P3_CPU rails, and activating CHIP_EN 50
t1Duration of CHIP_EN signal level < VIL_nRST to reset the chip 50
2.3 Flash
ESP8684 series is embedded with 1 MB, 2 MB, or 4 MB flash. It doesn’t need to connect to external flash for
firmware.
2.4 Clock Source
ESP8684 has two clock sources:
• External crystal oscillator clock source
• RTC clock source
2.4.1 External Clock Source (compulsory)
Currently, the ESP8684 firmware only supports 40 MHz crystal or oscillator.
Crystal
The circuit for the crystal is shown in Figure 5. The specific capacitive values of C1 and C2 depend on further
testing of, and adjustment to, the overall performance of the whole circuit. In order to reduce the drive strength of
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2 Schematic Checklist
the crystal and minimize the impact of crystal harmonics on RF performance, please add a series inductor (initially
of 24 nH) on the XTAL_P clock trace. Note that the accuracy of the selected crystal should be within ±10
ppm.
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
The values of C8, L2 and C9 vary with the a tual PCB board.
The values of C1 and C2 vary with the sele tion of the rystal. The value of R1 varies with the a tual PCB board.
ESP8684-MINI-1(pin-out)
NC: No omponent. ESP8684H2
ESP8684H1 ESP8684H4
CHIP_EN GPIO4 GPIO5 GPIO6
U0RXD
ANT GPIO0 GPIO1 GPIO2 GPIO3
RF_ANT
U0TXD
GPIO2 GPIO3 CHIP_EN
GPIO1
GPIO0
GPIO10
GPIO6
GPIO7
GPIO8
GPIO9
GPIO18 U0RXD U0TXD
GPIO4
GPIO5
GPIO7 GPIO8 GPIO9 GPIO10 GPIO18
GND
VDD33
GND
GNDGND GND
GND GND
GND
VDD33
GND GNDGND
VDD33 VDD33
GND
GND
GND
GND GND VDD33
GND
GND
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C1
TBD
R1 0(1%)
R2 499(1%)
Y1 40MHz
XIN
1
GND
2XOUT 3
GND 4
L1 2.0nH(0.1nH)
C9
TBD
U2
ANT
1
VDDA3P3
2
VDDA3P3
3
GPIO0
4
GPIO1
5
GPIO2
6
CHIP_EN
7
MTMS
9
MTDI
10
VDD3P3_RTC
11
MTCK
12
MTDO 13
GPIO8 14 GPIO9 15
GPIO10 16
VDD3P3_CPU 17
U0RXD 19
U0TXD 20
XTAL_N 22
XTAL_P 23
GND 25
GPIO3
8VDDA 24
VDDA 21
GPIO18 18
C6 0.1uF/6.3V(10%) D1
ESD
C3
1uF/6.3V(20%)
C4
10nF/6.3V(10%)
C10 0.1uF/6.3V(10%)
C7 0.1uF/6.3V(10%)
ANT1 PCB_ANT
1 2
U3
ESP8684-MINI-1
GND
1
3V3
3
IO9
23
NC
4
IO2
5
IO3
6
NC
7
NC
9
NC
10
NC
15
IO10
16
NC
17
IO4
18
IO5
19
NC 32
TXD0 31
RXD0 30
NC 34 NC 33
IO18 26
NC 29 NC 28 NC 27
IO7
21
IO8
22
IO0
12
IO1
13
GND
52
IO6
20
NC 35
NC
24
EPAD 49
GND
2
GND
53
GND 51 GND 50
EN
8
GND 36
GND 37
GND 38
GND 39
GND 40
GND 41
GND 42
GND 43
GND 44
GND 45
GND 46
GND 47
GND 48
GND
14
GND
11 NC 25
C2 TBD
C8
TBD
C12 0.1uF/6.3V(10%)
L2 TBD
C5
10uF/6.3V(20%)
Figure 5: Schematic for the Crystal
Oscillator
If an oscillator is used, its output should be connected to XTAL_P on the chip through a series inductor (a 20 nH
inductor can be used initially). XTAL_N can be floating. Make sure that the oscillator output is stable and its
accuracy is within ±10 ppm. It is recommended that the circuit design for the oscillator is compatible with the
crystal. In case of defects in the circuit design, you can still use the crystal. The circuit for the oscillator is shown
in Figure 6.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NC: No component.
The values of C8, L2 and C9
vary with the actual PCB board.
The values of C1 and C2 vary with
the selection of the crystal.
The value of R1 varies with the actual
PCB board.
If using ESP32-C3FN4 or ESP32-C3FH4,
flash is not mounted.
GPIO19
CHIP_EN
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
U0RXD
GPIO18
LNA_IN
GPIO9
GPIO10
GPIO0
GPIO1
SPICS0
SPID
SPIQ
SPICLK
SPIWP
SPIHDGPIO2
GPIO3
RF_ANT
U0TXD
SPICLK
SPICS0
SPIHD SPIWP
SPID
SPIQ
XTAL_P
GND
VDD33
GND
GND
GNDGND GND
GND GND
GND
VDD33
GND GNDGND
VDD33
VDD_SPI
VDD33
GND
VDD_SPI
GND
GND
GND GND
GND
VDD33
GND
C1
TBD
C9
TBD
R4 0
U3 FLASH-3V3
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
L3 TBD
R7 0
R6 0
ANT1
PCB_ANT
1
2
R1 0
C12
0.1uF
C3
1uF
C10
0.1uF
R5 0
R1 0
R3 0
R2 499
C1
10nF
C8
TBD
C2
TBD
L1 2.0nH
C6
0.1uF
Y1
40MHz(±10ppm)
VCC
4
NC
1GND 2
OUT 3
C5
10uF
L2 TBD
C7
1uF
C4
10nF
U2 ESP32-C3
LNA_IN
1
VDD3P3
2
VDD3P3
3
XTAL_32K_P
4
XTAL_32K_N
5
GPIO2
6
CHIP_EN
7
MTMS
9
MTDI
10
VDD3P3_RTC
11
MTCK
12
MTDO
13
GPIO8
14
GPIO9
15
GPIO10
16
VDD3P3_CPU 17
VDD_SPI 18
SPIHD 19
SPIWP 20
SPICS0 21
SPICLK 22
SPID 23
SPIQ 24
U0RXD 27
U0TXD 28
XTAL_N 29
XTAL_P 30
GND 33
GPIO3
8
VDDA 32 VDDA 31
GPIO19 26 GPIO18 25
C11
1uF
R8
10K
U1
40MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
Figure 6: Schematic for the Oscillator
Notice:
Defects in the manufacturing of crystal and oscillators (for example, large frequency deviation of more than ±10 ppm,
unstable performance within operating temperature range, etc) may lead to the malfunction of ESP8684, resulting in a
decrease of the RF performance.
2.4.2 RTC (optional)
ESP8684 supports an external clock signal (e.g., an oscillator) input through GPIO0 to act as the RTC sleep
clock and the typical clock frequency is 32.768 kHz. The amplitude of the input clock signal should be the same
as the amplitude requirement of the GPIO input signal.
2.5 RF
Aπ-type matching network is essential for antenna matching in the circuit design. CLC structure is
recommended for the matching network. The parameters of the components in the matching network are
Espressif Systems 10
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ESP8684 Series Hardware Design Guidelines v1.1