EPC EPC9004C User manual

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Figure 15: EPC9004C Main schematic
Logic Supply
10-15 VDC
i
NetC lass
ClassName: HighVoltageGate
Intermediate Capacitors
V I NV I N V I N V I N V I N V I N V IN V I N V I N V I N
Gate Driver
GND
VSW
V dd12
GND
V dd12
GND
V dd12
SW Output
Main Supply Input
GND
VCC
5 V
GND
V CC
V 1
AP1006_Rev2_01_12Vto5VlinPSU.SCHDOC
GND
Heatspreader Mount
V I N
V SW
V I N
V I NV I N
V I NV I N
V I NV I N
V SW
V SWV SW
V SWV SW
V SWV SW
FD1
PC
FD2
PC
FD3
PCB Fiducial
1 2
3
5
7
4
6
8
Amphenol
67997-272HL F
J3A
17 18
19
21
23
20
22
24
Bottom Side install
Bottom Side install
Bottom Side install
J3C
9 10
11
13
15
12
14
16
J3B
1
2
100 mil TH
100 mil TH
100 mil TH
J90
0603
0 Ω 0.1W
R90
0603
1 μF 25 V
C11
Sync Buck Output
V OUT
Power Stage
V SW
V I N V I N
V SW
Switch-node
V OUT
SMD MMCX
J32
E MPT Y
TB D
L 1
E MPT Y
TB D
Cout
E MPT Y
1
2
7.62 mm T H
J9
E MPT Y
SM D T P
Keystone5015
TP2
SM D T P
Keystone5015
TP4
SM D T P
Keystone5015
T P3SM D T P
Keystone5015
TP1
1
2
Hole 100mil 1 row, 2 pos.
J33
V SW
Upper Gate
SMD MMCX
J1
E MPT Y 0402
0 Ω 1/16 W
R11
E MPT Y
V Gl
Lower Gate
SMD MMCX
J2
E MPT Y
0402
R22
E MPT Y
1
2
Hole 100mil 1 row, 2 pos.
J22
PWM1
PWM2
GND
V CC
In1
In2
Qup
Qlow
DT
AP1010_Rev3_02_GeneralDeadtime.SCHDOC
PWM1
PWM2
L I N
HI N
Dead-time and buers
GND GND
V CC
GND
Signal Inputs
1
2
3
4
J80
5 V Logic Regulator
GND
Vdd12
PWMH
PWML
VSW
VGuH
VGlH
VGuL
VGlLEN
GNDP
GD
P1029_Rev2_0_NCP51820_GateDriver.SCHDOC
EN
EN
GNDP
V I N
VGuH
VGlH
SW
VGuL
VGlL
VGu
VGl
PS
EPC2012C_Rev1_0_PhaseLeg.SCHDOC
V Gu
VGl
V Gu
9774010243R
Spacer M2 1 mm Spacer M2 1 mm Spacer M2 1 mm
SO1
9774010243R
SO2
9774010243R
SO3
1210
150 nF 500 V
Cm1
1210
150 nF 500 V
Cm2
1210
150 nF 500 V
Cm3
1210
150 nF 500 V
Cm4
1210
150 nF 500 V
Cm5
1210
150 nF 500 V
Cm6
1210
150nF 500V
Cm7
1210
150 nF 500 V
Cm8
1210
150 nF 500 V
Cm9
1210
150 nF 500 V
Cm10
0402
0 Ω 1/16 W
0 Ω 1/16 W
R85
GNDPGND
Ground Connect
GND
1
2
J81
E MPT Y
GNDP GNDP GNDP GNDP
GNDP GNDP GNDP GNDP
GNDP
GNDP GNDP
GNDP
GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP
GNDP
i NetC lass
ClassName: HighVoltage
i
NetC lass
ClassName: HighVoltage
i
NetC lass
ClassName: HighVoltage
ATTENTION
ELECTROSTATIC
SENSITIVE DEVICE
ATTENTION
ELECTROSTATIC
SENSITIVE DEVICE
HIGH VOLTAGE
HIGH VOLTAGE
ATTENTION
HOT SURFACE

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Figure 16: EPC9004C Power Stage schematic
Vin
GNDP
DC Input
160 Vmax.
V I N
HF Loop Capacitors
SBR1U400P1-7
400 V, 1 A
D1
E MPT Y
SBR1U400P1-7
400 V, 1 A
D2
E MPT Y
0805
22 nF 500 V
Ci3
0805
22 nF 500 V
Ci4
0805
22 nF 500 V
Ci5
0805
22 nF 500 V
Ci6
0805
22 nF 500 V
Ci7
0805
22 nF 500 V
Ci1
0805
22 nF 500 V
Ci2
V I N V I N V I N V I N V I N V I N VIN
i Net Class
ClassName: HighVoltage
Net Class
ClassName: HighVoltage
i
i
Net Class
ClassName: HighVoltageGate
Power Stage
SW
V I N
Optional Diodes
SW
V I N
VGlH
VGuH
VGu
VGl
VGlL
VGuL
VGl
VGu
0402
20 Ω 16 W
20 Ω 16 W
R80
0402
2 Ω
2 Ω
1/16 W
R81
0402
R82
0402
1/16 W
R83
200 V 100 mΩ 5 A
Q2
EPC2012C
200 V 100 mΩ 5 A
Q1
EPC2012C
GNDP GNDP GNDP GNDP GNDP GNDP GNDP
GNDPGNDP
GNDP

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Figure 17: EPC9004C Gate Driver schematic
Gate Driver
0603
100 nF 25 V
C87
E MPT Y
0402
10 k 0.1 W
R73
0603
10 k 0.1 W
R84
E MPT Y
0603
0 Ω 0.1 W
R86
0402
15 pF 50 V
C76
GND
VSW
0402
2 1/16 W
R60
Vdd12
GND
Vdd12
RFU02VSM6STR
600 V 200 mA
D62
i
NetClass
ClassName: HighVoltageGate
VSW
EN
GNDP
VGlH
VGlL
VGuL
VGuH
VGuL
VGlH
VGlL
VGuH
GNDP
GND
Vdd12
GND
GND
Vdd12
GND
Vdd12
Vdd12
Vdd12
GNDP GNDPGND
GND
Vdd12
PWML
GND
GND
PWMH
0402
2.2 0.1 W
R70
0402
2.2 0.1W
R75
GND
GND
0402
10 k 1/16 W
R71
0402
10 k 1/16 W
R76
0402
100 pF 50 V
C70
EMPTY
0402
100 pF 50 V
C75
E MPT Y
Default = Mode A: R77 = 0
External dead-time
Cross conduction protection
0402
1 μF 25 V
C80
0402
100 nF 25 V
C60
0402
470 nF 25 V
C82
0402
1 μF 25 V
C81
0402
1 μF 25 V
C83
0402
2.2 0.1 W
R77
5
1
2
312
11
8
7
14
4
6
13
10
9
15
Hin
Lin
Bst
Logic
&
Dead-
Time
Level
Shift
UVLO
UVLO
PGND
VDD
Reg
DT
EN
SGND
Level
Shift
Reg
NCP51820AMNTWG
U80

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Figure 18: EPC9004C Dead-time and Bypass schematic
GND
GND
V CC
GND
V CC
GND
0402
100 nF 25 V
C610
V CCV CC
GND
GND
V CCV CC
GND
0402
100 nF 25 V
C612
V CC
0402
100 nF 25 V
C614
Qlow
Qup
0402
R602
0402
47 pF 50 V
C602
GND GND
0402
10 k 1/16 W
R601
0402
47 pF 50 V
C601
GND GND
In1
In2
0402
100 pF 50 V
C620
SDM03U40-7
30 V 30 mA
D620
0603
120 0.1 W
R620
GND
0402
R604
GND
0402
10 k 1/16 W
10 k 1/16 W10 k 1/16 W
10 k 1/16 W
R603
GND
0402
100nF 25V
C611
Deadtime Lower
Deadtime Upper
Signal Polarity and Input Buers
Bypass Mode Select
Polarity 0=Non-invert, 1= Invert
Polarity 0=Non-invert, 1= Invert
PolQup
PolQlow
DT Qlow
Dual/Single PWM, Buck, and Boost Mode Selector
50 mil
JP630
M50-2030005
Buck Single Signal
Boost Single Signal
Dual Signal
V CC
V CC
V CC
Full Bypass
No Bypass
DT Bypass
In1
In2
InBufQup
InBufQlow
0402
100 pF 50 V
C625
SDM03U40-7
30 V 30 mA
D625
0603
120 0.1 W
R625
GND
Default = 10 ns
Default = 10 ns
DT Qup
GND
GND
Dual
In1
In1
In2
1 2
3
5
4
6
50 mil TH
J630
GRPB032VWVN-RC
0402
R605
GND
GND
V CC
GND
GND
0402
100 nF 25 V
C615
V CC
GND
V CC
In1
V CC
V CC
V CC
1 2
3
5
4
6
50 mil TH
J640
GRPB032VWVN-RC
GND
V CCV CC
GND
GND
0402
10 k 1/16 W
R621
GND
SWbyp
SW byp
0402
10 k 1/16 W
R641
GND
GND
0402
100 nF 25 V
C616
V CC
GND
V CC
In2
SW byp
0402
10 k 1/16 W
R643
GND
UseDT
GND
0402
10 k 1/16 W
R626
GND
UseDT
SWbyp
SWbyp
UseDT
Output Buers and Signal Select
PolQlow
PolQup
Dual
50 mil
JP640
M50-2020005
G ND
4
2
3
7
V C C
8
5
1
6
74LVC1G99GN,115
U612
G ND
4
2
3
7
V C C
8
5
1
6
U610
74LVC1G99GN,115
G ND
4
2
3
7
V C C
8
5
1
6
74LV C1G99GN,115
U611
G ND
4
2
3
7
V C C
8
5
1
6
74LV C1G99GN,115
U614
V CC
G ND
SN74LVC1G66DBV
Bi directional SW 5 Ω 5.5 V
U615
V C C
G ND
SN74LVC1G66DBV
Bi directional SW 5 Ω 5.5 V
U616

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Figure 19: EPC9004C Logic Supply Regulator schematic
GND GND
V CC
GND
5 V
GND
0603
1 μF 25 V
C100
0603
1 μF 25 V
C101
0603
0 Ω 0.1W
R100
GND
OUT
G ND
IN
G ND
MCP1703T-5002E/MC
5.0 V 250 mA DFN
U100