Epson E0C6006 User manual

MF1114-01
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
E0C6006 T ECHNICAL M ANUAL
E0C6006 Technical Hardware

NOTICE
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permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material
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note that "E0C" is the new name for the old product "SMC". If "SMC" appears in other manuals understand that
it now reads "E0C".
© SEIKO EPSON CORPORATION 1998 All rights reserved.

E0C6006 TECHNICAL MANUAL EPSON i
CONTENTS
CONTENTS
CHAPTER 1INTRODUCTION ____________________________________________ 1
1.1 Features......................................................................................................... 1
1.2 Block Diagram .............................................................................................. 2
1.3 Pin Layout ..................................................................................................... 3
1.4 Pin Description ............................................................................................. 4
CHAPTER 2POWER SUPPLY AND INITIAL RESET ____________________________ 5
2.1 Power Supply ................................................................................................5
2.1.1 Voltage <VS1> for oscillation circuit and internal circuits ...................... 5
2.1.2 Voltage <VL1–VL3> for LCD driving ......................................................... 5
2.2 Initial Reset ................................................................................................... 6
2.2.1 Reset at power-on....................................................................................... 6
2.2.2 RESET pin .................................................................................................. 6
2.2.3 Oscillation detection circuit....................................................................... 7
2.2.4 Watchdog timer ........................................................................................... 7
2.2.5 Initialization by initial reset....................................................................... 7
2.3 Test Input Pin (TEST) ................................................................................... 7
CHAPTER 3 CPU, ROM, RAM________________________________________ 8
3.1 CPU............................................................................................................... 8
3.2 ROM .............................................................................................................. 8
3.3 RAM .............................................................................................................. 8
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 9
4.1 Memory Map ................................................................................................. 9
4.2 Watchdog Timer ........................................................................................... 11
4.2.1 Configuration of watchdog timer .............................................................. 11
4.2.2 I/O memory of watchdog timer ................................................................. 11
4.2.3 Programming note..................................................................................... 11
4.3 Oscillation Circuit ....................................................................................... 12
4.3.1 Configuration of oscillation circuit .......................................................... 12
4.3.2 OSC1 oscillation circuit ............................................................................ 12
4.3.3 OSC3 oscillation circuit ............................................................................ 12
4.3.4 Switching the system clock ........................................................................ 13
4.3.5 Clock frequency and instruction execution time....................................... 13
4.3.6 I/O memory of oscillation circuit.............................................................. 14
4.3.7 Programming notes ................................................................................... 14
4.4 Input Ports (K00–K03, K10–K13) ............................................................... 15
4.4.1 Configuration of input port ....................................................................... 15
4.4.2 Interrupt function ...................................................................................... 15
4.4.3 Mask option ............................................................................................... 16
4.4.4 I/O memory of input port .......................................................................... 16
4.4.5 Programming notes ................................................................................... 17
4.5 Output Ports (R00–R03) ..............................................................................18
4.5.1 Configuration of output port ..................................................................... 18
4.5.2 Mask option ............................................................................................... 18
4.5.3 Special output ............................................................................................ 19
4.5.4 I/O memory of output ports....................................................................... 21
4.5.5 Programming note..................................................................................... 21

ii EPSON E0C6006 TECHNICAL MANUAL
CONTENTS
4.6 I/O Ports (P00–P03) .................................................................................... 22
4.6.1 Configuration of I/O port .......................................................................... 22
4.6.2 I/O control register and I/O mode ............................................................ 22
4.6.3 I/O memory of I/O port ............................................................................. 22
4.6.4 Programming notes ................................................................................... 23
4.7 LCD Driver .................................................................................................. 24
4.7.1 Configuration of LCD driver .................................................................... 24
4.7.2 Mask option ............................................................................................... 26
4.7.3 Programming note..................................................................................... 26
4.8 Clock Timer .................................................................................................. 27
4.8.1 Configuration of clock timer ..................................................................... 27
4.8.2 Interrupt function ...................................................................................... 27
4.8.3 I/O memory of clock timer ........................................................................ 28
4.8.4 Programming notes ................................................................................... 29
4.9 Remote Controller (REM)............................................................................ 30
4.9.1 Configuration of remote controller........................................................... 30
4.9.2 Carrier ....................................................................................................... 31
4.9.3 Soft-timer mode ......................................................................................... 33
4.9.4 Hard-timer mode and REM interrupt ....................................................... 34
4.9.5 I/O memory of remote controller .............................................................. 38
4.9.6 Programming notes ................................................................................... 41
4.10 Interrupt and HALT .....................................................................................42
4.10.1 Interrupt request...................................................................................... 42
4.10.2 Interrupt mask register............................................................................ 44
4.10.3 Interrupt vector ....................................................................................... 44
4.10.4 Programming notes ................................................................................. 45
4.11 Lower Current Dissipation ..........................................................................46
CHAPTER 5BASIC EXTERNAL WIRING DIAGRAM ____________________________ 47
CHAPTER 6ELECTRICAL CHARACTERISTICS ________________________________ 48
6.1 Absolute Maximum Rating...........................................................................48
6.2 Recommended Operating Conditions.......................................................... 48
6.3 DC Characteristics ...................................................................................... 48
6.4 Analog Circuit Characteristics and Power Current Consumption ............. 49
6.5 Oscillation Characteristics.......................................................................... 49
6.6 Input Current Characteristics (For Reference) ..........................................50
6.7 Output Current Characteristics (For Reference) .......................................51
CHAPTER 7PACKAGE ________________________________________________ 52
7.1 Plastic Package ............................................................................................ 52
7.2 Ceramic Package for Test Samples .............................................................. 53
CHAPTER 8PAD LAYOUT _____________________________________________ 54
8.1 Diagram of Pad Layout................................................................................ 54
8.2 Pad Coordinates .......................................................................................... 54
CHAPTER 9PRECAUTIONS ON MOUNTING _________________________________ 55

E0C6006 TECHNICAL MANUAL EPSON 1
CHAPTER 1: INTRODUCTION
CHAPTER 1INTRODUCTION
The E0C6006 is a single-chip microcomputer which uses an E0C6200B CMOS 4-bit CPU as the core. It
contains a 2,048 (words) ×12 (bits) ROM, 128 (words) ×4 (bits) RAM, LCD driver circuit, remote-control
carrier output circuit, time base counter and watchdog timer.
The E0C6006 offers a superb solution to infrared remote controller and other applications requiring low
power consumption.
1.1 Features
Core CPU ........................................... E0C6200B
ROM size .......................................... 2,048 words ×12 bits
RAM size ........................................... 128 words ×4 bits
Clock .................................................. 32.768 kHz crystal oscillation circuit
455 kHz ceramic or CR oscillation circuit (selectable by mask option)
Instruction execution time ............ 32 kHz operation: 153, 214 or 366 µsec (depending on instructions)
455 kHz operation: 11, 15 or 26 µsec (depending on instructions)
Instruction set .................................. 100 instructions
Input port .......................................... 8 ports (with or without pull-up resistor)
Output ports ..................................... 4 ports (clock and buzzer outputs are possible by mask option)
I/O port .............................................. 4 ports
Infrared remote-control output .... 1 output
LCD driver ........................................ 20 segments ×3 or 4 commons
(1/3 or 1/4 duty are selectable by mask option)
Clock timer ....................................... Built-in
Watchdog timer ................................ Built-in
Interrupt ............................................ External: 2 input interrupts
Internal: 3 timer interrupts (32 Hz, 8 Hz or 2 Hz)
1 remote control output control interrupt
Supply voltage ................................. 3 V (2.2 V to 3.5 V)
Current consumption (Typ.) ......... 32 kHz operation: 2 µA in halt mode
9 µA in full run mode
455 kHz operation: 130 µA
Supply form ..................................... Die form, QFP6-60pin plastic package or QFP13-64pin plastic package

2EPSON E0C6006 TECHNICAL MANUAL
CHAPTER 1: INTRODUCTION
1.2 Block Diagram
OSC1
OSC2
OSC3
OSC4
COM0–3
SEG0–19
V DD , V SS
V L1– V L3 , V ADJ
CA, CB
V S1
K00–K03
K10–K13
TEST
RESET
P00–P03
R00, R01
R02 (FOUT, BZ)
∗1
R03 (BZ)
∗1
R33 (REM)
∗1: Terminal specifications can be selected by mask option.
Core CPU E0C6200B
ROM
2,048 words ×12 bits
System Reset
Control
Interrupt
Generator
RAM
128 words ×4 bits
LCD Driver
20 SEG ×4 COM
Power
Controller
OSC
Clock
Timer
Watchdog
Timer FOUT & Buzzer
Input Port
I/O Port
Output Port
REM
Fig. 1.2.1 E0C6006 block diagram

E0C6006 TECHNICAL MANUAL EPSON 3
CHAPTER 1: INTRODUCTION
1.3 Pin Layout
QFP6-60pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin name
N.C.
N.C.
N.C.
K00
K01
K02
K03
K10
K11
K12
K13
R00
R01
R02
R03
No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin name
R33(REM)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
N.C.
SEG11
TEST
No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Pin name
RESET
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
COM3
COM2
COM1
COM0
V
L1
V L2
No.
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin name
V
L3
V ADJ
CA
CB
V
SS
OSC4
OSC3
V
S1
OSC2
OSC1
V
DD
P03
P02
P01
P00
N.C. = No connection
3145
16
30
INDEX
151
60
46
Fig. 1.3.1 E0C6006 pin layout (QFP6-60pin)
QFP13-64pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin name
N.C.
N.C.
N.C.
N.C.
K00
K01
K02
K03
K10
K11
K12
K13
R00
R01
R02
R03
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin name
N.C.
R33(REM)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
N.C.
TEST
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
RESET
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
COM3
COM2
COM1
COM0
V L1
V L2
V L3
No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin name
N.C.
V ADJ
CA
CB
V SS
OSC4
OSC3
V S1
OSC2
OSC1
V DD
P03
P02
P01
P00
N.C.
N.C. = No connection
3348
17
32
INDEX
161
64
49
Fig. 1.3.2 E0C6006 pin layout (QFP13-64pin)

4EPSON E0C6006 TECHNICAL MANUAL
CHAPTER 1: INTRODUCTION
1.4 Pin Description
Table 1.4.1 Pin description
Pin name
V
DD
V SS
V S1
V L1
V L2
V L3
CA, CB
V
ADJ
OSC1
OSC2
OSC3
OSC4
K00–K03
K10–K13
P00–P03
R00, R01
R02
R03
R33(REM)
SEG0–19
COM0–3
RESET
TEST
Pin No. Function
Power supply pin (+)
Power supply pin (-)
Oscillation and internal logic system voltage output pin
LCD drive voltage output pin
LCD drive voltage output pin
LCD drive voltage output pin
Boost capacitor connecting pin
V
L1 adjustment input pin
Oscillation input pin (crystal)
Oscillation output pin (crystal)
Oscillation input pin (ceramic or CR *)
Oscillation output pin (ceramic or CR *)
Input port pin
Input port pin
I/O port pin
Output port pin
Output port pin, BZ or FOUT output pin *
Output port pin or BZ output pin *
Remote control carrier output port pin
LCD segment output pin
or DC output pin *
LCD common output pin (1/3 duty or 1/4 duty are selectable *)
Initial reset input pin
Input pin for test
QFP6-60
56
50
53
44
45
46
48, 49
47
55
54
52
51
4–7
8–11
60–57
12, 13
14
15
16
17–27, 29,
32–39
43–40
31
30
QFP13-64
59
53
56
46
47
48
51, 52
50
58
57
55
54
5–8
9–12
63–60
13, 14
15
16
18
19–30,
34–41
45–42
33
32
I/O
(I)
(I)
–
–
–
–
–
I
I
O
I
O
I
I
I/O
O
O
O
O
O
O
I
I
∗Can be selected by mask option

E0C6006 TECHNICAL MANUAL EPSON 5
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2POWER SUPPLY AND INITIAL RESET
2.1 Power Supply
With a single external power supply (∗) supplied to VDD through VSS, the E0C6006 generates the neces-
sary internal voltages with the regulated voltage circuit (<VS1> for oscillator and internal circuit) and the
LCD voltage circuit (<VL2 and VL3 or VL1 and VL3> for LCD).
∗Supply voltage: 3 V (2.2 to 3.5 V)
Note: External loads cannot be driven by the output voltage of the regulated voltage circuit and LCD
voltage circuit.
2.1.1Voltage <VS1> for oscillation circuit and internal circuits
VS1 is a voltage for the oscillation circuit and the internal logic circuits, and is generated by the voltage
regulator for stabilizing the oscillation.
2.1.2Voltage <VL1–VL3> for LCD driving
The on-chip LCD voltage circuit generates the voltage levels (VDD, VL1, VL2 and VL3) needed to drive the
LCD panel.
Figure 2.1.2.1 shows the external connection diagram.
V DD
V S1
V L1
V L2
V L3
CA
CB
V SS
3 V
Fig. 2.1.2.1 External connection in each LCD operation mode
For LCD driving, the internal voltage regulator generates the VL1 voltage. The VL2 and VL3 voltage levels
are generated by boosting the VL1 voltage.
The VL1 voltage can be adjusted by feeding it back to the VADJ pin through RA1 and RA2 as shown in
Figure 2.1.2.2. VL(≈VDD - VL1) is defined by following equation:
VL≈1 ×(RA1 + RA2) / RA1
Example:
V L
≈1 V
≈1.5 V
R A1
∞
2 MΩ
R A2
0 Ω
1 MΩ
An LCD driving voltage suited to each
LCD panel can be obtained by adjusting
VLat the VADJ pin.
R A1
V ADJ V L1
(1 MΩ)
(2 MΩ)
V ADJ V L1
R A2
Fig. 2.1.2.2 LCD voltage adjustment circuit

6EPSON E0C6006 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
The E0C6006 must be initially reset to initialize its circuits. Initial reset is triggered by an external reset
(RESET) signal, oscillation detector signal, or watchdog timer signal. The RESET input is needed for
initialization at power-on.
OSC1
oscillation
circuit Watchdog
timer
Oscillation
detector
WDRST
Initial reset
V
DD
f OSC1
OSC1
OSC2
E0C6006
RESET
Fig. 2.2.1 Initial reset circuit configuration
2.2.1 Reset at power-on
At power-on, the initial reset signal has two functions. One function is to initialize a circuit and the other
to sustain the initializing function until the OSC3 oscillation is stabilized. Thus, the RESET input must be
held at low level for at least 0.5 second after power-on.
After the RESET input reaches the high level and the OSC1 oscillation circuit starts operating, several
milliseconds later, the system is released from internal reset and starts to operate.
V DD
OSC3
RESET
Detect oscillation
Watchdog timer
Internal initial reset (Vss : GND)
Fig. 2.2.1.1 Initial reset sequence at power-on
2.2.2 RESET pin
The RESET signal directly initializes the E0C6006. The system is reset when RESET = L, and released from
the reset state when RESET = H. As the RESET pin is pulled up and receives a schmitt trigger input, it can
be used as a power-on reset circuit if the RESET pin is connected with the VSS pin via a capacitor as
shown in Figure 2.2.2.1. A reset switch must be provided to obtain an assured reset effect at power-on
without being influenced by possible power. This is especially important for a reset operation without the
use of the OSC3 oscillation circuit, in which case the system clock (OSC1) must be ON before the system
is released from the reset state.
To reset circuit
C
RESET
SR
E0C6006
V DD
V SS
V SS
Fig. 2.2.2.1 Power-on reset circuit

E0C6006 TECHNICAL MANUAL EPSON 7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.3 Oscillation detection circuit
With RESET = H, the oscillation detection circuit receives fOSC1 and makes a f-V conversion. If the OSC1
frequency is greater than a certain value, the oscillation output goes to L to clear the reset state. The time
required for f-V conversion depends on fOSC1, and is several milliseconds with fOSC1 = 32 kHz. This time
gives a delay for clearing the reset state from the RESET input going to H.
The oscillation detection circuit may sometimes not operate normally with the initial resetting due to the
circuit, depending on the method of making the power, you should utilize the initial resetting method by
the RESET pin.
2.2.4Watchdog timer
The watchdog timer guards the CPU against an unexpected overrun. It uses the OSC1 clock as the source
oscillation frequency to perform the increment operation. If the watchdog timer fails to be reset in 3–4
seconds with fOSC1 = 32 kHz, the CPU will be initialized at initial reset.
See Section 4.2, "Watchdog Timer", for details.
2.2.5 Initialization by initial reset
When the E0C6006 is initially reset, its internal registers are set as follows:
Table 2.2.5.1 Initial status
∗See Section 4.1, "Memory Map".
Name
Program counter step
Program counter page
New page pointer
Stack pointer
Index register X
Index register Y
Register pointer
General-purpose register A
General-purpose register B
Interrupt flag
Decimal flag
Zero flag
Carry flag
CPU Core
Symbol
PCS
PCP
NPP
SP
X
Y
RP
A
B
I
D
Z
C
Bit size
8
4
4
8
8
8
4
4
4
1
1
1
1
Initial value
00H
1H
1H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
0
Undefined
Undefined
Name
RAM
Display memory
Other peripheral circuits
Peripheral Circuits
Bit size
128×4
20×4
–
Initial value
Undefined
Undefined
∗
2.3 Test Input Pin (TEST)
This pin is used when IC is inspected for shipment.
During normal operation connect it to VDD.

8EPSON E0C6006 TECHNICAL MANUAL
CHAPTER 3: CPU, ROM, RAM
CHAPTER 3 CPU, ROM, RAM
3.1 CPU
The E0C6006 employs the E0C6200B core CPU, so that register configuration, instructions, and so forth
are virtually identical to those in other processors in the family using the E0C6200/6200A/6200B. Refer to
the "E0C6200/6200A Core CPU Manual" for details of the E0C6200B.
Note the following points with regard to the E0C6006:
(1) The E0C6006 does not support the SLEEP function, therefore the SLP instruction cannot be used.
(2) Because the ROM capacity is 2,048 words, 12 bits per word, bank bits are unnecessary, and PCB and
NBP are not used.
(3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is
invalid.
PUSH XP POP XP LD XP,r LD r,XP
PUSH YP POP YP LD YP,r LD r,YP
3.2 ROM
The built-in ROM, a mask ROM for the program, has a capacity of 2,048 ×12-bit steps. The program area
is 8 pages (0–7), each consisting of 256 steps (00H–FFH). After an initial reset, the program start address is
set to page 1, step 00H. The interrupt vectors are allocated to page 1, steps 01H–07H.
Step 00H
Step 07H
Step 08H
Step FFH
12 bits
Program start address
Interrupt vector area
Bank 0
Program area
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Step 01H
Page 6
Page 7
Fig. 3.2.1 ROM configuration
3.3 RAM
The RAM, a data memory for storing a variety of data, has a capacity of 128 words, 4-bit words. When
programming, keep the following points in mind:
(1) Part of the data memory is used as stack area when saving subroutine return addresses and registers,
so be careful not to overlap the data area and stack area.
(2) Subroutine calls and interrupts take up three words on the stack.
(3) Data memory 000H–00FH is the memory area pointed by the register pointer (RP).

E0C6006 TECHNICAL MANUAL EPSON 9
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION
Peripheral circuits (timer, I/O, and so on) of the E0C6006 are memory mapped. Thus, all the peripheral
circuits can be controlled by using memory operations to access the I/O memory. The following sections
describe how the peripheral circuits operate.
4.1 Memory Map
The data memory of the E0C6006 has an address space of 175 words, of which 32 words are allocated to
display memory and 15 words, to I/O memory. Figure 4.1.1 show the overall memory map for the
E0C6006, and Table 4.1.1, the memory maps for the peripheral circuits (I/O space).
Address
Page High
Low 0123456789ABCDEF
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
3
0
1
2
4
5
6
7
8
9
A
B
C
D
E
F
0
RAM area (000H–07FH)
128 words ×4 bits (R/W)
Display memory area (0D0H–0EFH)
32 words ×4 bits (W only)
Unused area
I/O memory See Table 4.1.1
Fig. 4.1.1 Memory map
Note: Memory is not mounted in unused area within the memory map and in memory area not indicated
in this chapter. For this reason, normal operation cannot be assured for programs that have been
prepared with access to these areas.

10 EPSON E0C6006 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 I/O memory map
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
0FAH K03 K02 K01 K00
R
K03
K02
K01
K00
– ∗2
– ∗2
– ∗2
– ∗2
High
High
High
High
Low
Low
Low
Low
K0 input port data
0FBH K13 K12 K11 K10
R
K13
K12
K11
K10
– ∗2
– ∗2
– ∗2
– ∗2
High
High
High
High
Low
Low
Low
Low
K1 input port data
0FCH
R03
BZ
R02
BZ
FOUT R01 R00
R/W
R03
BZ
R02
BZ/FOUT
R01
R00
0
0
0
0
0
0
High
On
High
On
High
High
Low
Low
Low
Low
Low
Low
R03 output port data
Signal on/off when BZ is selected. (mask option)
R02 output port data
Signal on/off when BZ/FOUT is selected. (mask option)
R01 output port data
R00 output port data
0FFH 0 0 IOC 0
R/W RR
0 ∗3
0 ∗3
IOC
0 ∗3
– ∗2
– ∗2
0
– ∗2
–
–
Output
–
–
–
Input
–
Unused
Unused
I/O port I/O control
Unused
0FEH P03 P02 P01 P00
R/W
P03
P02
P01
P00
– ∗2
– ∗2
– ∗2
– ∗2
High
High
High
High
Low
Low
Low
Low
P0 I/O port data
0F8H RIC3 RIC2 RIC1 RIC0
W
RIC3
RIC2
RIC1
RIC0
– ∗5
– ∗5
– ∗5
– ∗5
REM interrupt counter (0τto 14τ)
0F9H ROUT1 ROUT0 MF91 MF90
R/W
ROUT1
ROUT0
MF91
MF90
0
0
– ∗5
– ∗5
REM output duration setting (0τto 3τ)
General-purpose register
General-purpose register
0F4H TM03 TM02 TM01 TM00
R
TM03
TM02
TM01
TM00
0
0
0
0
Timer data (16 Hz)
Timer data (32 Hz)
Timer data (64 Hz)
Timer data (128 Hz)
0F5H TM13 TM12 TM11 TM10
R
TM13
TM12
TM11
TM10
0
0
0
0
Timer data (1 Hz)
Timer data (2 Hz)
Timer data (4 Hz)
Timer data (8 Hz)
0F7H RCDIV RCDUTY RT1 RT0
R/W
RCDIV
RCDUTY
RT1
RT0
– ∗5
– ∗5
– ∗5
– ∗5
REM carrier interval
and duty ratio setting
τcycle (division ratio) setting
0: 1/12, 1: 1/16, 2: 1/20, 3: 1/32
0F2H REMC EIREM EIK1 EIK0
R/W
REMC
EIREM
EIK1
EIK0
1
0
0
0
On
Enable
Enable
Enable
Off
Mask
Mask
Mask
REM carrier generation on/off
Interrupt mask register (REM)
Interrupt mask register (K10–K13)
Interrupt mask register (K00–K03)
0F0H REMSO IREM IK1 IK0
R/W R
REMSO
IREM ∗4
IK1 ∗4
IK0 ∗4
0
– ∗5
0
0
On
Yes
Yes
Yes
Off
No
No
No
Forced REM output (on/off)
Interrupt factor flag (REM)
Interrupt factor flag (K10–K13)
Interrupt factor flag (K00–K03)
0F3H TMRUN EIT2 EIT8 EIT32
R/W
TMRUN
EIT2
EIT8
EIT32
0
0
0
0
Run
Enable
Enable
Enable
Reset,Stop
Mask
Mask
Mask
Timer run/reset & stop
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
0F6H 0 0 CLKCHG OSCC
R R/W
0 ∗3
0 ∗3
CLKCHG
OSCC
– ∗2
– ∗2
0
1
–
–
OSC1
On
–
–
OSC3
Off
Unused
Unused
CPU clock change
OSC3 oscillation on/off
0F1H WDRST IT2 IT8 IT32
WR
WDRST
IT2 ∗4
IT8 ∗4
IT32 ∗4
Reset
0
0
0
Reset
Yes
Yes
Yes
–
No
No
No
Watchdog timer reset
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
∗1
∗2Initial value at initial reset Not set in the circuit ∗5 Undefined∗3 ∗4Always "0" being read Reset (0) immediately after being read
D3
0
0
1
1
D2
0
1
0
1
Div. ratio
1/8
1/8
1/12
1/12
Duty
1/4
3/8
1/3
1/4

E0C6006 TECHNICAL MANUAL EPSON 11
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
4.2 Watchdog Timer
4.2.1 Configuration of watchdog timer
The E0C6006 has a built-in watchdog timer that operates with a divided clock from the OSC1 as the
source clock. The watchdog timer must be reset cyclically by the software while it operates. If the watch-
dog timer is not reset in at least 3–4 seconds (when fOSC1 is 32.768 kHz), it resets the CPU.
Figure 4.2.1.1 is the block diagram of the watchdog timer.
Watchdog timer
Initial reset
signal
OSC1 dividing clock
Watchdog timer reset signal
Fig. 4.2.1.1 Watchdog timer block diagram
Watchdog timer reset processing in the program's main routine enables detection of program overrun,
such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is
incorporated where periodic processing takes place, just as for the timer interrupt routine.
The watchdog timer operates in the HALT mode. If a HALT status continues for 3–4 seconds, the watch-
dog timer generates a CPU reset signal.
The watchdog timer function can be nullified by using the mask option.
4.2.2 I/O memory of watchdog timer
Table 4.2.2.1 shows the I/O address and control bit for the watchdog timer.
Table 4.2.2.1 Control bit of watchdog timer
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
0F1H WDRST IT2 IT8 IT32
WR
WDRST
IT2
∗4
IT8
∗4
IT32
∗4
Reset
0
0
0
Reset
Yes
Yes
Yes
–
No
No
No
Watchdog timer reset
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
∗1
∗2Initial value at initial reset Not set in the circuit ∗5 Undefined∗3 ∗4Always "0" being read Reset (0) immediately after being read
WDRST: Watchdog timer reset (0F1H•D3)
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading: Always "0"
When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0"
is written, no operation results.
This bit is dedicated for writing, and is always "0" for reading.
4.2.3 Programming note
When the watchdog timer is being used, the software must reset it within 3-second cycles.

12 EPSON E0C6006 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3 Oscillation Circuit
4.3.1 Configuration of oscillation circuit
The E0C6006 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that
supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscilla-
tion circuit. When processing with the E0C6006 requires high-speed operation, the CPU operating clock
can be switched from OSC1 to OSC3 by the software. Figure 4.3.1.1 is the block diagram of this oscillation
system.
Oscillation circuit control signal
CPU clock selection signal
To CPU
To peripheral circuits
Clock
switch
OSC3
oscillation circuit
OSC1
oscillation circuit Divider
Fig. 4.3.1.1 Oscillation system block diagram
4.3.2 OSC1 oscillation circuit
The OSC1 crystal oscillation circuit generates the main clock for the CPU and the peripheral circuits. The
oscillation frequency is 32.768 kHz (Typ.). Figure 4.3.2.1 is the block diagram of the OSC1 oscillation
circuit.
VDD
VDD
OSC2
OSC1
X'tal
CGX To CPU and
peripheral circuits
RFX
CDX
RDX
Fig. 4.3.2.1 OSC1 oscillation circuit (crystal)
As shown in Figure 4.3.2.1, the crystal oscillation circuit can be configured simply by connecting the
crystal oscillator (X'tal) of 32.768 kHz (Typ.) between the OSC1 and OSC2 terminals and the trimmer
capacitor (CGX) between the OSC1 and VDD terminals.
4.3.3 OSC3 oscillation circuit
The E0C6006 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Typ. 455 kHz)
for high speed operation and the source clock for peripheral circuits needing a high speed clock (REM
circuit). The mask option enables selection of either the CR or ceramic oscillation circuit. When CR
oscillation is selected, only a resistance is required as an external element. When ceramic oscillation is
selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are required.
Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.
OSC4
OSC3
R
CR
C CR
OSCC
To CPU and
REM circuit
(a) CR oscillation circuit

E0C6006 TECHNICAL MANUAL EPSON 13
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
V DD
OSC4
OSC3
C
DC
C GC
OSCC
Ceramic
To CPU and
REM circuit
R
FC
R
DC
(b) Ceramic oscillation circuit
OSC4
OSC3 V
DD
V S1
(c) When "Not Use" is selected by mask option
Fig. 4.3.3.1 OSC3 oscillation circuit
As shown in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor
RCR between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 6, "Electrical
Characteristics" for resistance value of RCR.
When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Typ. 455 kHz) between the OSC3 and OSC4 terminals, capacitor CGC between the
OSC3 and VDD terminals, and capacitor CDC between the OSC4 and VDD terminals. For both CGC and
CDC, connect capacitors that are about 100 pF.
The OSC3 ocsillation circuit can be controlled (on and off) using the OSCC register. To reduce current
consumption, the OSC3 oscillation circuit should be stopped by the software (OSCC register) if unneces-
sary.
When "Not Use" is selected by mask option, do not connect anything to the OSC3 and OSC4 terminals.
4.3.4 Switching the system clock
The CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register).
When OSC3 is to be used as the CPU clock, it should be done as the following procedure using the
software: turn the OSC3 oscillation ON and wait at least 5 msec for oscillation stabilization, then switch
the CPU clock after waiting 5 msec or more.
When switching from OSC3 to OSC1, switch the CPU clock, then turn the OSC3 oscillation circuit off.
OSC1
→ OSC3 OSC3 → OSC1
1. Set OSCC to "1" (OSC3 oscillation ON). 1. Set CLKCHG to "0" (OSC3 →OSC1).
2. Maintain 5 msec or more. 2. Set OSCC to "0" (OSC3 oscillation OFF).
3. Set CLKCHG to "1" (OSC1 →OSC3).
4.3.5 Clock frequency and instruction execution time
Table 4.3.5.1 shows the instruction execution time according to each frequency of the system clock.
Table 4.3.5.1 Clock frequency and instruction execution time
Clock frequency
OSC1: 32.768 kHz
OSC3: 455 kHz
5-clock instruction
152.6
11.0
7-clock instruction
213.6
15.4
12-clock instruction
366.2
26.4
Instruction execution time (µsec)

14 EPSON E0C6006 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.6 I/O memory of oscillation circuit
Table 4.3.6.1 shows the I/O address and the control bits for the oscillation circuit.
Table 4.3.6.1 Control bits of oscillation circuit
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
0F6H 0 0 CLKCHG OSCC
R R/W
0
∗3
0
∗3
CLKCHG
OSCC
–
∗2
–
∗2
0
1
–
–
OSC1
On
–
–
OSC3
Off
Unused
Unused
CPU clock change
OSC3 oscillation on/off
∗1
∗2Initial value at initial reset Not set in the circuit ∗5 Undefined∗3 ∗4Always "0" being read Reset (0) immediately after being read
OSCC: OSC3 oscillation control register (0F6H•D0)
Controls oscillation for the OSC3 oscillation circuit.
When "1" is written: OSC3 oscillation ON
When "0" is written: OSC3 oscillation OFF
Reading: Valid
When it is necessary to operate the CPU at high speed or output a remote control carrier signal, set OSCC
to "1". At other times, set it to "0" to reduce current consumption.
At initial reset, this register is set to "1".
CLKCHG: CPU system clock switching register (0F6H•D1)
The CPU's operation clock is selected with this register.
When "1" is written: OSC1 clock is selected
When "0" is written: OSC3 clock is selected
Reading: Valid
When the CPU clock is to be OSC3, set CLKCHG to "0"; for OSC1, set CLKCHG to "1".
After turning the OSC3 oscillation ON (OSCC = "1"), switching of the clock should be done after waiting
5 msec or more.
At initial reset, this register is set to "0".
4.3.7 Programming notes
(1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes on until the oscillation stabi-
lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went on.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(2) When switching the clock from OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation off. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.

E0C6006 TECHNICAL MANUAL EPSON 15
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4 Input Ports (K00–K03, K10–K13)
4.4.1 Configuration of input port
The E0C6006 has two 4-bit general-purpose input ports (K00–K03 and K10–K13). As shown in Figure
4.4.1.1, each input port terminal is provided with a pull-up and a feedback pull-up so that the port is
suitable for push switch or key matrix switch input. As the pull-up can be removed by using mask
option, the input port can also be used for slide switch input or interface with another LSI.
V DD
K
Data bus
Input
control
V
Interrupt
request
Mask option
SS
nm
Fig. 4.4.1.1 Configuration of input port
Input port data can be read on a 4-bit basis (K00–K03, K10–K13) addressed 0FAH and 0FBH.
4.4.2 Interrupt function
All input port bits (K00–K03, K10–K13) provide the interrupt function.
The interrupt mask registers (EIK0, EIK1) enable the interrupt mask to be selected individually for K0
and K1 terminal groups. An interrupt occurs at the falling edge of an input signal which is not masked
and the interrupt factor flags (IK0, IK1) is set to "1".
Input interrupt programming related precautions
Factor flag
is set Not set
Mask register
➀
K port input Active status
When the content of the mask register is rewritten, while the port K input is in the active status.
The input interrupt factor flag is set at ➀.
Fig. 4.4.2.1 Input interrupt timing
When using an input interrupt, if you rewrite the content of the mask register, when the value of the
input terminal which becomes the interrupt input is in the active status (input terminal = low status), the
factor flag for input interrupt may be set.
For example, a factor flag is set with the timing of ➀shown in Figure 4.4.2.1. However, when clearing the
content of the mask register with the input terminal kept in the low status and then setting it, the factor
flag of the input interrupt is again set at the timing that has been set.
Consequently, when the input terminal is in the active status (low status), do not rewrite the mask
register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in
this case. When clearing, then setting the mask register, set the mask register, when the input terminal is
not in the active status (high status).

16 EPSON E0C6006 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4.3 Mask option
An internal pull-up resistor can be selected for each of the eight bits of the input ports (K00–K03, K10–
K13). Having selected "pull-up resistor disabled", take care that the input does not float. Select "pull-up
resistor enabled" for input ports that are not being used.
4.4.4 I/O memory of input port
Table 4.4.4.1 shows the I/O addresses and the control bits for the input port.
Table 4.4.4.1 Control bits of input port
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
0FAH K03 K02 K01 K00
R
K03
K02
K01
K00
– ∗2
– ∗2
– ∗2
– ∗2
High
High
High
High
Low
Low
Low
Low
K0 input port data
0FBH K13 K12 K11 K10
R
K13
K12
K11
K10
– ∗2
– ∗2
– ∗2
– ∗2
High
High
High
High
Low
Low
Low
Low
K1 input port data
0F2H REMC EIREM EIK1 EIK0
R/W
REMC
EIREM
EIK1
EIK0
1
0
0
0
On
Enable
Enable
Enable
Off
Mask
Mask
Mask
REM carrier generation on/off
Interrupt mask register (REM)
Interrupt mask register (K10–K13)
Interrupt mask register (K00–K03)
0F0H REMSO IREM IK1 IK0
R/W R
REMSO
IREM ∗4
IK1 ∗4
IK0 ∗4
0
– ∗5
0
0
On
Yes
Yes
Yes
Off
No
No
No
Forced REM output (on/off)
Interrupt factor flag (REM)
Interrupt factor flag (K10–K13)
Interrupt factor flag (K00–K03)
∗1
∗2Initial value at initial reset Not set in the circuit ∗5 Undefined∗3 ∗4Always "0" being read Reset (0) immediately after being read
K00–K03: Input port data (0FAH)
K10–K13: Input port data (0FBH)
The input data of the input port terminals can be read with these registers.
When "1" is read: High level
When "0" is read: Low level
Writing: Invalid
The value read is "1" when the terminal voltage of the input port (K00–K03, K10–K13) goes high (VDD),
and "0" when the voltage goes low (VSS). These bits are reading only, so writing cannot be done.
EIK0, EIK1: Interrupt mask registers (0F2H•D0, D1)
Masking the interrupt of the input port terminal groups can be done with these registers.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
With these registers, masking of the input port bits can be done for each of the four-bit terminal groups.
At initial reset, these registers are all set to "0".