Epson S1C17704 User manual

TECHNICAL MANUAL
S1C17704
CMOS 16-BIT SINGLE CHIP MICROCOMPUTER

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©SEIKO EPSON CORPORATION 2008, All rights reserved

S1C17704 Technical Manual Revision History
Code No. Page Chapter/Section Contents
411511901 1-2 1.1 Features Descriptions modified.
Shipping form
Part number for plastic package modified.
Part number for package modified.
Descriptions added.
• VFBGA10H-144 package
(10 mm  10 mm  1.0 mm, ball pitch: 0.8 mm)
1-4 1.3.1 Pin Arrangement Part number added.
TQFP24-144-pin
Figure 1.3.1.1
Part number modified.
QFP24-144-pin→TQFP24-144-pin
1-6 Part number modified.
VFBGA7HX161→VFBGA7H-161
Figure 1.3.1.3
Part number modified.
VFBGA7HX161→VFBGA7H-161
1-7 Figure 1.3.1.4 added.
1-8 1.3.2 Pin Descriptions Table 1.3.2.1 modified.
1-9 Descriptions modified.
Numbers and names of pins
6-15 6.7 Details of Control Registers Description deleted.
(The interrupts can be used to clear standby mode even if
the corresponding interrupt enable bit is set to disable
interrupt.)
11-9 11.7 16-bit Timer Output Signal Numerical value modified.
Expression for I2C
22-3 22.3.2 Frame Signal Description deleted.
(see Table 22.3.1.)
22-9 22.6.1 Turning Display On and Off Table 22.6.1.1 modified.
Description modified.
22-15 22.8 Details of Control Registers Table 22.8.2 modified.
Description modified.
26-7 26.6.3 External Clock
Input AC Characteristics
Table modified.
27-1 27 Package Part number modified.
QFP24-144-pin package→TQFP24-144-pin package
27-3 Part number modified.
VFBGA7HX161 Package→VFBGA7H-161 Package
27-4 Figure added.
VFBGA10H-144 Package
28-2 28.2 Pad Coordinates Table modified.
Coordinates modified.
AP-36 Appendix D Precautions on
Mounting
Description for Noise-Induced Erratic Operations modified.
10-11 10.8 Details of Control Registers Description modified.
The PxIN[7:0] bits correspond to the Px[7:0] ports respectively
and the voltage level on the port pin is read out in the input
mode...In the output mode, an indefinite value is read out.

Devices
S1 C 17xxx F 00E1
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G: TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M: TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q: TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 17000 H2 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Dx : Evaluation board
Ex : ROM emulation board
Mx: Emulation memory for external ROM
Tx : A socket for mounting
Cx : Compiler package
Sx : Middleware package
Corresponding model number
17xxx: for S1C17xxx
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
Configuration of product number

CONTENTS
S1C17704 TECHNICAL MANUAL EPSON i
– Contents –
1 Overview........................................................................................................................1-1
1.1 Features ...........................................................................................................................1-2
1.2 Block Diagram..................................................................................................................1-3
1.3 Pins ..................................................................................................................................1-4
1.3.1 Pin Arrangement ................................................................................................1-4
1.3.2 Pin Description...................................................................................................1-8
2 CPU................................................................................................................................2-1
2.1 Features of the S1C17 Core ............................................................................................2-1
2.2 CPU Registers .................................................................................................................2-2
2.3 Instruction Set ..................................................................................................................2-3
2.4 Vector Table .....................................................................................................................2-7
2.5 Processor Information ......................................................................................................2-8
3 Memory Map, Bus Control ...........................................................................................3-1
3.1 Bus Cycle .........................................................................................................................3-2
3.1.1 Restrictions on Access Size...............................................................................3-2
3.1.2 Restrictions on Instruction Execution Cycles.....................................................3-2
3.2 Flash Area ........................................................................................................................3-3
3.2.1 Internal Flash Memory .......................................................................................3-3
3.2.2 Flash Programming ..........................................................................................3-3
3.2.3 Protect Bits ........................................................................................................3-3
0x17ffc–0x17ffe: Flash Protect Bits ........................................................................................... 3-3
3.2.4 Access Control for the Flash Controller ............................................................3-4
0x5320: FLASHC Control Register (MISC_FL)......................................................................... 3-4
3.3 Internal RAM Area............................................................................................................3-5
3.3.1 Internal RAM......................................................................................................3-5
3.4 Display RAM Area ............................................................................................................3-6
3.4.1 Display RAM ......................................................................................................3-6
3.4.2 Access Control for the SRAM Controller ...........................................................3-6
0x5321: SRAMC Control Register (MISC_SR) ......................................................................... 3-6
3.5 Internal Peripheral Area ...................................................................................................3-7
3.5.1 Internal Peripheral Area 1 (0x4000–).................................................................3-7
3.5.2 Internal Peripheral Area 2 (0x5000–).................................................................3-7
3.5.3 I/O Map ..............................................................................................................3-8
3.6 S1C17 Core I/O Area ......................................................................................................3-11
4 Power Supply ................................................................................................................4-1
4.1 Power Supply Voltage ......................................................................................................4-1
4.2 Internal Power Supply Circuit...........................................................................................4-2
4.3 Controlling the Power Supply Circuit................................................................................4-3
4.4 Heavy Load Protection Function ......................................................................................4-5
4.5 Details of Control Registers .............................................................................................4-6
0x5120: VD1 Control Register (VD1_CTL)................................................................................. 4-7
0x50a3: LCD Voltage Regulator Control Register (LCD_VREG) .............................................. 4-8
0x50a4: LCD Power Voltage Booster Control Register (LCD_PWR) ........................................ 4-9
4.6 Precautions .....................................................................................................................4-10

CONTENTS
ii EPSON S1C17704 TECHNICAL MANUAL
5 Initial Reset ...................................................................................................................5-1
5.1 Initial Reset Sources ........................................................................................................5-1
5.1.1 #RESET Pin.......................................................................................................5-1
5.1.2 P0 Port Key-Entry Reset ...................................................................................5-2
5.1.3 Resetting by the Watchdog Timer......................................................................5-2
5.2 Initial Reset Sequence .....................................................................................................5-3
5.3 Initial Settings After an Initial Reset .................................................................................5-4
6 Interrupt Controller (ITC) .............................................................................................6-1
6.1 Configuration of ITC .........................................................................................................6-1
6.2 Vector Table .....................................................................................................................6-2
6.3 Control of Maskable Interrupts .........................................................................................6-3
6.3.1 Enabling ITC ......................................................................................................6-3
6.3.2 Interrupt Request from Peripheral Module and Interrupt Flag ...........................6-3
6.3.3 Enabling/Disabling Interrupts.............................................................................6-4
6.3.4 Processing when Multiple Interrupts Occur .......................................................6-5
6.3.5 Interrupt Trigger Mode .......................................................................................6-6
6.3.6 Interrupt Processing by the S1C17 Core ...........................................................6-8
6.4 NMI...................................................................................................................................6-9
6.5 Software Interrupts..........................................................................................................6-10
6.6 Clearing HALT and SLEEP Modes by Interrupt Causes .................................................6-11
6.7 Details of Control Registers ............................................................................................6-12
0x4300: Interrupt Flag Register (ITC_IFLG)............................................................................. 6-13
0x4302: Interrupt Enable Register (ITC_EN) ........................................................................... 6-15
0x4304: ITC Control Register (ITC_CTL)................................................................................. 6-16
0x4306: External Interrupt Level Setup Register 0 (ITC_ELV0) ............................................... 6-17
0x4308: External Interrupt Level Setup Register 1 (ITC_ELV1) ............................................... 6-18
0x430a: External Interrupt Level Setup Register 2 (ITC_ELV2) ............................................... 6-19
0x430c: External Interrupt Level Setup Register 3 (ITC_ELV3) ............................................... 6-20
0x430e: Internal Interrupt Level Setup Register 0 (ITC_ILV0).................................................. 6-21
0x4310: Internal Interrupt Level Setup Register 1 (ITC_ILV1).................................................. 6-22
0x4312: Internal Interrupt Level Setup Register 2 (ITC_ILV2).................................................. 6-23
0x4314: Internal Interrupt Level Setup Register 3 (ITC_ILV3).................................................. 6-24
6.8 Precautions .....................................................................................................................6-25
7 Oscillator (OSC)............................................................................................................7-1
7.1 Configuration of OSC Module ..........................................................................................7-1
7.2 OSC3 Oscillator ...............................................................................................................7-2
7.3 OSC1 Oscillator ...............................................................................................................7-4
7.4 Switching the System Clock.............................................................................................7-5
7.5 Controlling the LCD Clock................................................................................................7-6
7.6 Controlling the 8-bit OSC1 Timer Clock ...........................................................................7-7
7.7 External Output Clock (FOUT3, FOUT1) .........................................................................7-8
7.8 Noise Filters for RESET and NMI Inputs.........................................................................7-10
7.9 Details of Control Registers ............................................................................................7-11
0x5060: Clock Source Select Register (OSC_SRC) ................................................................ 7-12
0x5061: Oscillation Control Register (OSC_CTL) .................................................................... 7-13
0x5062: Noise Filter Enable Register (OSC_NFEN)................................................................ 7-14
0x5063: LCD Clock Setup Register (OSC_LCLK) ................................................................... 7-15
0x5064: FOUT Control Register (OSC_FOUT)........................................................................ 7-16
0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1)...................................................... 7-17
7.10 Precautions ...................................................................................................................7-18

CONTENTS
S1C17704 TECHNICAL MANUAL EPSON iii
8 Clock Generator (CLG).................................................................................................8-1
8.1 Configuration of Clock Generator.....................................................................................8-1
8.2 Controlling the CPU Core Clock (CCLK)..........................................................................8-2
8.3 Controlling the Peripheral Module Clock (PCLK) .............................................................8-3
8.4 Details of Control Registers .............................................................................................8-4
0x5080: PCLK Control Register (CLG_PCLK) .......................................................................... 8-5
0x5081: CCLK Control Register (CLG_CCLK).......................................................................... 8-6
8.5 Precautions ......................................................................................................................8-7
9 Prescaler (PSC).............................................................................................................9-1
9.1 Configuration of the Prescaler..........................................................................................9-1
9.2 Details of Control Register ...............................................................................................9-2
0x4020: Prescaler Control Register (PSC_CTL)....................................................................... 9-2
9.3 Precaution ........................................................................................................................9-3
10 I/O Ports (P)................................................................................................................10-1
10.1 Structure of I/O Port ......................................................................................................10-1
10.2 Selecting I/O Pin Functions (Port MUX) .......................................................................10-2
10.3 Data Input/Output..........................................................................................................10-3
10.4 Pull-Up Control..............................................................................................................10-4
10.5 Input Interface Level .....................................................................................................10-5
10.6 Chattering Filter for P0 Ports.........................................................................................10-6
10.7 Port Input Interrupt ........................................................................................................10-7
10.8 Details of Control Registers .........................................................................................10-10
0x5200/0x5210/0x5220/0x5230: PxPort Input Data Registers (Px_IN) ................................. 10-11
0x5201/0x5211/0x5221/0x5231: PxPort Output Data Registers (Px_OUT) ........................... 10-12
0x5202/0x5212/0x5222/0x5232: PxPort I/O Direction Control Registers (Px_IO) ................. 10-13
0x5203/0x5213/0x5223/0x5233: PxPort Pull-up Control Registers (Px_PU)......................... 10-14
0x5204/0x5214/0x5224/0x5234: PxPort Schmitt Trigger Control Registers (Px_SM)............ 10-15
0x5205/5215: PxPort Interrupt Mask Registers (Px_IMSK) ................................................... 10-16
0x5206/5216: PxPort Interrupt Edge Select Registers (Px_EDGE) ....................................... 10-17
0x5207/5217: PxPort Interrupt Flag Registers (Px_IFLG)...................................................... 10-18
0x5208: P0 Port Chattering Filter Control Register (P0_CHAT).............................................. 10-19
0x5209: P0 Port Key-Entry Reset Configuration Register (P0_KRST) ................................... 10-20
0x52a0: P0 Port Function Select Register (P0_PMUX) .......................................................... 10-21
0x52a1: P1 Port Function Select Register (P1_PMUX) .......................................................... 10-22
0x52a2: P2 Port Function Select Register (P2_PMUX) .......................................................... 10-23
0x52a3: P3 Port Function Select Register (P3_PMUX) .......................................................... 10-24
10.9 Precautions ..................................................................................................................10-25
11 16-bit Timers (T16).....................................................................................................11-1
11.1 Outline of the 16-bit Timers ...........................................................................................11-1
11.2 16-bit Timer Operating Mode.........................................................................................11-2
11.2.1 Internal Clock Mode ........................................................................................11-2
11.2.2 External Clock Mode.......................................................................................11-3
11.2.3 Pulse Width Measurement Mode ....................................................................11-4
11.3 Count Mode...................................................................................................................11-5
11.4 16-bit Timer Reload Register and Underflow Period .....................................................11-6
11.5 Resetting the 16-bit Timer .............................................................................................11-7
11.6 16-bit Timer Run/Stop Control .......................................................................................11-8
11.7 16-bit Timer Output Signal.............................................................................................11-9
11.8 16-bit Timer Interrupt ....................................................................................................11-10

CONTENTS
iv EPSON S1C17704 TECHNICAL MANUAL
11.9 Details of Control Registers..........................................................................................11-11
0x4220/0x4240/0x4260: 16-bit Timer Ch.xInput Clock Select Registers (T16_CLKx) ........... 11-12
0x4222/0x4242/0x4262: 16-bit Timer Ch.xReload Data Registers (T16_TRx) ...................... 11-13
0x4224/0x4244/0x4264: 16-bit Timer Ch.xCounter Data Registers (T16_TCx) ..................... 11-14
0x4226/0x4246/0x4266: 16-bit Timer Ch.xControl Registers (T16_CTLx)............................. 11-15
11.10 Precautions ................................................................................................................11-17
12 8-bit Timer (T8F).........................................................................................................12-1
12.1 Outline of the 8-bit Timer...............................................................................................12-1
12.2 Count Mode of the 8-bit Timer.......................................................................................12-2
12.3 Count Clock...................................................................................................................12-3
12.4 8-bit Timer Reload Register and Underflow Period.......................................................12-4
12.5 Resetting the 8-bit Timer ...............................................................................................12-5
12.6 8-bit Timer Run/Stop Control.........................................................................................12-6
12.7 8-bit Timer Output Signal ..............................................................................................12-7
12.8 Fine Mode .....................................................................................................................12-8
12.9 8-bit Timer Interrupt.......................................................................................................12-9
12.10 Details of Control Registers .......................................................................................12-10
0x4200: 8-bit Timer Input Clock Select Register (T8F_CLK)................................................... 12-11
0x4202: 8-bit Timer Reload Data Register (T8F_TR).............................................................. 12-12
0x4204: 8-bit Timer Counter Data Register (T8F_TC) ............................................................ 12-13
0x4206: 8-bit Timer Control Register (T8F_CTL) .................................................................... 12-14
12.11 Precautions ................................................................................................................12-16
13 PWM & Capture Timer (T16E) ...................................................................................13-1
13.1 Outline of the PWM & Capture Timer............................................................................13-1
13.2 PWM & Capture Timer Operating Mode .......................................................................13-2
13.3 Setting/Resetting the Counter Value .............................................................................13-3
13.4 Setting Compare Data...................................................................................................13-4
13.5 PWM & Capture Timer Run/Stop Control......................................................................13-5
13.6 Controlling Clock Output ...............................................................................................13-6
13.7 PWM & Capture Timer Interrupt....................................................................................13-9
13.8 Details of Control Registers .........................................................................................13-11
0x5300: PWM Timer Compare Data A Register (T16E_CA) ................................................... 13-12
0x5302: PWM Timer Compare Data B Register (T16E_CB)................................................... 13-13
0x5304: PWM Timer Counter Data Register (T16E_TC) ........................................................ 13-14
0x5306: PWM Timer Control Register (T16E_CTL) ................................................................ 13-15
0x5308: PWM Timer Input Clock Select Register (T16E_CLK)............................................... 13-17
0x530a: PWM Timer Interrupt Mask Register (T16E_IMSK)................................................... 13-18
0x530c: PWM Timer Interrupt Flag Register (T16E_IFLG) ..................................................... 13-19
13.9 Precautions ..................................................................................................................13-20
14 8-bit OSC1 Timer (T8OSC1) ......................................................................................14-1
14.1 Outline of the 8-bit OSC1 Timer ....................................................................................14-1
14.2 Count Mode of the 8-bit OSC1 Timer............................................................................14-2
14.3 Count Clock...................................................................................................................14-3
14.4 Resetting the 8-bit OSC1 Timer ....................................................................................14-4
14.5 Setting Compare Data...................................................................................................14-5
14.6 8-bit OSC1 Timer Run/Stop Control..............................................................................14-6
14.7 8-bit OSC1 Timer Interrupt ............................................................................................14-7
14.8 Details of Control Registers ..........................................................................................14-9
0x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL) .................................................. 14-10
0x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT)........................................ 14-11

CONTENTS
S1C17704 TECHNICAL MANUAL EPSON v
0x50c2: 8-bit OSC1 Timer Compare Data Register (T8OSC1_CMP) ..................................... 14-12
0x50c3: 8-bit OSC1 Timer Interrupt Mask Register (T8OSC1_IMSK)..................................... 14-13
0x50c4: 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG) ....................................... 14-14
14.9 Precautions ..................................................................................................................14-15
15 Clock Timer (CT) ........................................................................................................15-1
15.1 Outline of the Clock Timer.............................................................................................15-1
15.2 Operating Clock ............................................................................................................15-2
15.3 Resetting the Clock Timer .............................................................................................15-3
15.4 Clock Timer Run/Stop Control.......................................................................................15-4
15.5 Clock Timer Interrupt.....................................................................................................15-5
15.6 Details of Control Registers ..........................................................................................15-7
0x5000: Clock Timer Control Register (CT_CTL)..................................................................... 15-8
0x5001: Clock Timer Counter Register (CT_CNT) ................................................................... 15-9
0x5002: Clock Timer Interrupt Mask Register (CT_IMSK) ...................................................... 15-10
0x5003: Clock Timer Interrupt Flag Register (CT_IFLG)......................................................... 15-11
15.7 Precautions ..................................................................................................................15-12
16 Stopwatch Timer (SWT).............................................................................................16-1
16.1 Outline of the Stopwatch Timer .....................................................................................16-1
16.2 BCD Counters ...............................................................................................................16-2
16.3 Operating Clock ............................................................................................................16-3
16.4 Resetting the Stopwatch Timer .....................................................................................16-4
16.5 Stopwatch Timer Run/Stop Control...............................................................................16-5
16.6 Stopwatch Timer Interrupt .............................................................................................16-6
16.7 Details of Control Registers ..........................................................................................16-8
0x5020: Stopwatch Timer Control Register (SWT_CTL).......................................................... 16-9
0x5021: Stopwatch Timer BCD Counter Register (SWT_BCNT) ............................................ 16-10
0x5022: Stopwatch Timer Interrupt Mask Register (SWT_IMSK) ........................................... 16-11
0x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG).............................................. 16-12
16.8 Precautions ..................................................................................................................16-13
17 Watchdog Timer (WDT)..............................................................................................17-1
17.1 Outline of the Watchdog Timer......................................................................................17-1
17.2 Operating Clock ............................................................................................................17-2
17.3 Controlling the Watchdog Timer ....................................................................................17-3
17.3.1 Selecting NMI/Reset Mode .............................................................................17-3
17.3.2 Watchdog Timer Run/Stop Control .................................................................17-3
17.3.3 Resetting the Watchdog Timer........................................................................17-3
17.3.4 Operation in Standby Mode ............................................................................17-3
17.4 Details of Control Registers ..........................................................................................17-4
0x5040: Watchdog Timer Control Register (WDT_CTL) .......................................................... 17-5
0x5041: Watchdog Timer Status Register (WDT_ST).............................................................. 17-6
17.5 Precautions ...................................................................................................................17-7
18 UART...........................................................................................................................18-1
18.1 Outline of the UART ......................................................................................................18-1
18.2 UART Pins.....................................................................................................................18-2
18.3 Transfer Clock ...............................................................................................................18-3
18.4 Setting Transfer Data Conditions ..................................................................................18-4
18.5 Data Transmit/Receive Control .....................................................................................18-5
18.6 Receive Errors ..............................................................................................................18-8
18.7 UART Interrupt ..............................................................................................................18-9

CONTENTS
vi EPSON S1C17704 TECHNICAL MANUAL
18.8 IrDA Interface ...............................................................................................................18-11
18.9 Details of Control Registers .........................................................................................18-13
0x4100: UART Status Register (UART_ST)............................................................................ 18-14
0x4101: UART Transmit Data Register (UART_TXD)............................................................. 18-16
0x4102: UART Receive Data Register (UART_RXD) ............................................................. 18-17
0x4103: UART Mode Register (UART_MOD) ......................................................................... 18-18
0x4104: UART Control Register (UART_CTL) ........................................................................ 18-19
0x4105: UART Expansion Register (UART_EXP) .................................................................. 18-20
18.10 Precautions ................................................................................................................18-21
19 SPI...............................................................................................................................19-1
19.1 Configuration of the SPI ................................................................................................19-1
19.2 SPI I/O Pins...................................................................................................................19-2
19.3 SPI Clock ......................................................................................................................19-3
19.4 Setting the Data Transfer Conditions ............................................................................19-4
19.5 Data Transmit/Receive Control .....................................................................................19-5
19.6 SPI Interrupt ..................................................................................................................19-8
19.7 Details of Control Registers .........................................................................................19-10
0x4320: SPI Status Register (SPI_ST) ................................................................................... 19-11
0x4322: SPI Transmit Data Register (SPI_TXD)..................................................................... 19-12
0x4324: SPI Receive Data Register (SPI_RXD) ..................................................................... 19-13
0x4326: SPI Control Register (SPI_CTL)................................................................................ 19-14
19.8 Precautions ..................................................................................................................19-16
20 I2C................................................................................................................................20-1
20.1 Configuration of the I2C.................................................................................................20-1
20.2 I2C I/O Pins ...................................................................................................................20-2
20.3 I2C Clock .......................................................................................................................20-3
20.4 Setting before Starting Data Transfer............................................................................20-4
20.5 Data Transmit/Receive Control .....................................................................................20-5
20.6 I2C Interrupt..................................................................................................................20-11
20.7 Details of Control Registers .........................................................................................20-13
0x4340: I2C Enable Register (I2C_EN) ................................................................................... 20-14
0x4342: I2C Control Register (I2C_CTL)................................................................................. 20-15
0x4344: I2C Data Register (I2C_DAT)..................................................................................... 20-17
0x4346: I2C Interrupt Control Register (I2C_ICTL) ................................................................. 20-19
21 Remote Controller (REMC) .......................................................................................21-1
21.1 Outline of the REMC ....................................................................................................21-1
21.2 REMC I/O Pins..............................................................................................................21-2
21.3 Carrier Generator ..........................................................................................................21-3
21.4 Setting Clock for Data Length Counter .........................................................................21-4
21.5 Controlling Data Transmission/Reception .....................................................................21-5
21.6 REMC Interrupt .............................................................................................................21-8
21.7 Details of Control Registers .........................................................................................21-10
0x5340: REMC Configuration Register (REMC_CFG) ............................................................ 21-11
0x5341: REMC Prescaler Clock Select Register (REMC_PSC) ............................................. 21-12
0x5342: REMC H Carrier Length Setup Register (REMC_CARH).......................................... 21-13
0x5343: REMC L Carrier Length Setup Register (REMC_CARL)........................................... 21-14
0x5344: REMC Status Register (REMC_ST).......................................................................... 21-15
0x5345: REMC Length Counter Register (REMC_LCNT)....................................................... 21-16
0x5346: REMC Interrupt Mask Register (REMC_IMSK)......................................................... 21-17
0x5347: REMC Interrupt Flag Register (REMC_IFLG) ........................................................... 21-18
21.8 Precaution ....................................................................................................................21-19

CONTENTS
S1C17704 TECHNICAL MANUAL EPSON vii
22 LCD Driver (LCD).......................................................................................................22-1
22.1 Configuration of LCD Driver ..........................................................................................22-1
22.2 LCD Power Supply........................................................................................................22-2
22.3 LCD Clock .....................................................................................................................22-3
22.3.1 LCD Operating Clock .....................................................................................22-3
22.3.2 Frame Signal ..................................................................................................22-3
22.4 Switching Drive Duty .....................................................................................................22-4
22.5 Display Memory ............................................................................................................22-7
22.6 Display Control..............................................................................................................22-9
22.6.1 Turning Display On and Off.............................................................................22-9
22.6.2 LCD Contrast Adjustment ..............................................................................22-9
22.6.3 Reverse Display..............................................................................................22-9
22.6.4 Controlling Gray Scale Display .....................................................................22-10
22.7 LCD Interrupt................................................................................................................22-11
22.8 Details of Control Registers .........................................................................................22-13
0x50a0: LCD Display Control Register (LCD_DCTL).............................................................. 22-14
0x50a1: LCD Contrast Adjust Register (LCD_CADJ).............................................................. 22-16
0x50a2: LCD Clock Control Register (LCD_CCTL)................................................................. 22-17
0x50a3: LCD Voltage Regulator Control Register (LCD_VREG) ............................................ 22-18
0x50a4: LCD Power Voltage Booster Control Register (LCD_PWR) ...................................... 22-19
0x50a5: LCD Interrupt Mask Register (LCD_IMSK)................................................................ 22-20
0x50a6: LCD Interrupt Flag Register (LCD_IFLG) .................................................................. 22-21
22.9 Precautions ..................................................................................................................22-22
23 Supply Voltage Detector (SVD).................................................................................23-1
23.1 Outline of the SVD module............................................................................................23-1
23.2 Setting a Compare Voltage ..........................................................................................23-2
23.3 Controlling the SVD Operation......................................................................................23-3
23.4 SVD Interrupt ................................................................................................................23-4
23.5 Details of Control Registers ..........................................................................................23-6
0x5100: SVD Enable Register (SVD_EN)................................................................................ 23-7
0x5101: SVD Compare Voltage Register (SVD_CMP) ............................................................ 23-8
0x5102: SVD Detection Result Register (SVD_RSLT)............................................................. 23-9
0x5103: SVD Interrupt Mask Register (SVD_IMSK) ............................................................... 23-10
0x5104: SVD Interrupt Flag Register (SVD_IFLG).................................................................. 23-11
23.6 Precautions ..................................................................................................................23-12
24 On-chip Debugger (DBG)..........................................................................................24-1
24.1 Resource Requirements and Debugging Tools.............................................................24-1
24.2 Operating Status after Debugging Break Occurs..........................................................24-2
24.3 Details of Control Registers ..........................................................................................24-3
0x5322: OSC1 Peripheral Control Register (MISC_OSC1) ..................................................... 24-4
0xffff90: Debug RAM Base Register (DBRAM) ........................................................................ 24-5
25 Basic External Wiring Diagram ................................................................................25-1
26 Electrical Characteristics..........................................................................................26-1
26.1 Absolute Maximum Rating ............................................................................................26-1
26.2 Recommended Operating Conditions ...........................................................................26-1
26.3 DC Characteristics ........................................................................................................26-2
26.4 Analog Circuit Characteristics .......................................................................................26-3
26.5 Current Consumption ....................................................................................................26-5

CONTENTS
viii EPSON S1C17704 TECHNICAL MANUAL
26.6 AC Characteristics.........................................................................................................26-6
26.6.1 SPI AC Characteristics ...................................................................................26-6
26.6.2 I2C AC Characteristics ....................................................................................26-6
26.6.3 External Clock Input AC Characteristics .........................................................26-7
26.6.4 System AC Characteristics .............................................................................26-7
26.7 Oscillation Characteristics.............................................................................................26-8
26.8 Characteristic Plots (reference values) .........................................................................26-9
27 Package ......................................................................................................................27-1
28 Pad Layout .................................................................................................................28-1
28.1 Diagram of Pad Layout .................................................................................................28-1
28.2 Pad Coordinates ...........................................................................................................28-2
Appendix A List of I/O Registers.................................................................................. AP-1
0x4020 Prescaler.................................................................................. AP-4
0x4100–0x4105 UART (with IrDA) ..................................................................... AP-5
0x4200–0x4206 8-bit Timer (with Fine Mode) .................................................... AP-6
0x4220–0x4266 16-bit Timer.............................................................................. AP-7
0x4300–0x4314 Interrupt Controller ................................................................... AP-9
0x4320–0x4326 SPI .......................................................................................... AP-11
0x4340–0x4346 I2C........................................................................................... AP-12
0x5000–0x5003 Clock Timer............................................................................. AP-13
0x5020–0x5023 Stopwatch Timer ..................................................................... AP-14
0x5040–0x5041 Watchdog Timer...................................................................... AP-15
0x5060–0x5065 Oscillator................................................................................. AP-16
0x5080–0x5081 Clock Generator...................................................................... AP-17
0x50a0–0x50a6 LCD Driver .............................................................................. AP-18
0x50c0–0x50c4 8-bit OSC1 Timer .................................................................... AP-19
0x5100–0x5104 SVD Circuit ............................................................................. AP-20
0x5120 Power Generator .................................................................... AP-21
0x5200–0x52a3 P Port & Port MUX.................................................................. AP-22
0x5300–0x530c PWM & Capture Timer............................................................ AP-24
0x5320–0x5322 MISC Registers....................................................................... AP-25
0x5340–0x5347 Remote Controller................................................................... AP-26
0xffff80–0xffff90 S1C17 Core I/O ...................................................................... AP-27
Appendix B Flash Programming................................................................................. AP-28
B.1 Programming from Debugger ....................................................................................... AP-28
B.2 Self-Programming by Application Program................................................................... AP-29
Appendix C Power Saving ........................................................................................... AP-30
C.1 Power Saving by Clock Control ................................................................................... AP-30
C.2 Power Saving by Power Supply Control....................................................................... AP-33
Appendix D Precautions on Mounting ....................................................................... AP-34
Appendix E Initialize Routine ...................................................................................... AP-38

1 OVERVIEW
S1C17704 TECHNICAL MANUAL EPSON 1-1
1 Overview
The S1C17704 is a 16-bit MCU that features high-speed operation, low power consumption, small size, large
address space, and on-chip ICE. The S1C17704 consists of an S1C17 CPU Core, a 64K-byte Flash memory,
a 4K-byte RAM, serial interface modules (UART that supports high bit rate and IrDA 1.0, SPI and I2C) for
connecting various sensor modules, 8-bit timers, 16-bit timers, a PWM & capture timer, a clock timer, a stopwatch
timer, a watchdog timer, 28 GPIO ports, an LCD driver with 56-segment ×32-common outputs and a voltage
booster, a supply voltage detector, 32 kHz (typ.) and 8.2 MHz (max.) oscillators, and a voltage regulator for
generating the 1.8 V internal voltage. The S1C17704 is capable of high-speed operation (8.2 MHz) with low
operating voltage (1.8 V). Its 16-bit RISC processor executes one instruction in 1 clock cycles.
The S1C17704 also provides an on-chip ICE function that allows on-board erasing/programming of the embedded
Flash memory, on-board debugging and evaluating the program by connecting the S1C17704 to the ICD Mini
(S5U1C17001H) with only three wires. The S1C17704 is suitable for battery driven applications with sensor
interfaces and up to 56 ×32-dot LCD display, such as remote controllers and sports watches.
The product lineup offers two S1C17704 models with a different main oscillator.
Main (OSC3) oscillator • Crystal/ceramic oscillator 8.2 MHz (max.)
• CR oscillator 2.2 MHz (max.)
∗This product uses SuperFlash®Technology licensed from Silicon Storage Technology, Inc.

1 OVERVIEW
1-2 EPSON S1C17704 TECHNICAL MANUAL
1.1 Features
The main functions and features of the S1C17704 are outlined below.
CPU • Seiko Epson original 16-bit RISC CPU core S1C17
Main (OSC3) oscillator • Crystal/ceramic oscillator 8.2 MHz (max.)
• CR oscillator 2.2 MHz (max.)
Sub (OSC1) oscillator • Crystal oscillator 32.786 kHz (typ.)
On-chip Flash memory • 64K bytes (for instructions and data)
• 1,000 erase/program cycles
• Read/program protection
• On-board programming by a debugging tool such as ICD Mini (S5U1C17704H)
and self-programming by software control
On-chip RAM • 4K bytes
On-chip display RAM • 576 bytes
I/O ports • Max. 28 general-purpose I/O ports (Pins are shared with the peripheral I/O.)
Serial interfaces • SPI (master/slave) 1 ch.
• I2C (master) 1 ch.
• UART (115200 bps, IrDA 1.0) 1 ch.
• Remote controller (REMC) 1 ch.
Timers • 8-bit timer (T8F) 1 ch.
• 16-bit timer (T16) 3 ch.
• PWM & capture timer (T16E) 1 ch.
• Clock timer (CT) 1 ch.
• Stopwatch timer (SWT) 1 ch.
• Watchdog timer (WDT) 1 ch.
• 8-bit OSC1 timer (T8OSC1) 1 ch.
LCD driver • 56 SEG ×32 COM or 72 SEG ×16 COM (1/5 bias)
• Built-in voltage booster
Supply voltage detector (SVD) • 13 programmable detection levels (1.8 V to 2.7 V)
Interrupts • Reset
• NMI
• 16 programmable interrupts (8 levels)
Power supply voltage • 1.8 V to 3.6 V (for normal (low-power) operation with the 1.8 V internal voltage)
• 2.7 V to 3.6 V (for Flash erasing/programming with the 2.5 V internal voltage)
Operating temperature • -20°C to 70°C
Current consumption • SLEEP state: 1 µA typ.
• HALT state: 2.6 µA typ. (32 kHz OSC1 crystal oscillator, LCD off)
• Run state: 17 µA typ. (32 kHz OSC1 crystal oscillator, LCD off)
1950 µA typ. (8 MHz OSC3 ceramic oscillator, LCD off)
Shipping form • TQFP24-144pin plastic package
(16 mm ×16 mm ×1.0 mm, lead pitch: 0.4 mm)
• PFBGA6U96 package*
(6 mm ×6 mm ×1.0 mm, ball pitch: 0.5 mm)
• VFBGA7H-161 package
(7 mm ×7 mm ×1.0 mm, ball pitch: 0.5 mm)
• VFBGA10H-144 package
(10 mm ×10 mm ×1.0 mm, ball pitch: 0.8 mm)
• Chip
Note: The LCD driver cannot be used with the PFBGA6U96 package. It should be used with COM31 to
16 left open.

1 OVERVIEW
S1C17704 TECHNICAL MANUAL EPSON 1-3
1.2 Block Diagram
CPU Core S1C17
Internal RAM
(4K bytes)
I2C
8-bit timer
16-bit timer
Prescaler
Oscillator/
Clock generator
Clock timer
Stopwatch timer
Watchdog timer
PWM & capture
timer
8-bit OSC1 timer
Remote controller
MISC register
LCD driver
SVD circuit
Power generator
Flash memory
(64K bytes)
32 bits
RD: 1 cycle, WR: 1 cycle
16 bits
1–5
cycles
Interrupt system
8/16 bits
3 cycles
DCLK, DST2,
DSIO(P31–33)
VDD, VSS,
VD1, VD2,
VC1–VC5,
CA–CG
SEG0–55/71,
COM0–31/15
OSC1–2, OSC3–4
FOUT1(P13),
FOUT3(P30)
EXCL3(P27),
TOUT(P26)
REMI(P04),
REMO(P05)
P00–07, P10–17,
P20–27, P30–33
TEST1–3
#RESET
EXCL0–2
(P16, P07, P06)
SIN, SOUT, SCLK
(P23–25)
SDI, SDO, SPICLK
(P20–22)
SDA, SCL
(P14–15)
Display RAM
(576 bytes)
Reset circuit
8 bits
2–5 cycles
8/16 bits
1 cycle
I/O 2 (0x5000–)
Interrupt controller
UART
SPI
I/O 1 (0x4000–)
I/O port/
I/O MUX
#TEST Test circuit
Figure 1.2.1 Block Diagram

1 OVERVIEW
1-4 EPSON S1C17704 TECHNICAL MANUAL
1.3 Pins
1.3.1 Pin Arrangement
TQFP24-144-pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52
VSS
VDD P03 P10 P11 P12 P13/FOUT1 P04/REMI P05/REMO P06/EXCL2 P07/EXCL1 P14/SDA P15/SCL P16/EXCL0 P17/#SPISS P20/SDI P21/SDO P22/SPICLK P23/SIN P24/SOUT P25/SCLK P26/TOUT P27/EXCL3 P30/FOUT3 DCLK/P31 DST2/P32 DSIO/P33 #RESET #TEST OSC2 OSC1 VD1 VSS OSC4 OSC3 VDD
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VC1
VC2
VC3
VC4
VC5
CA
CB
CC
CD
CE
CF
CG
VD2
TEST3
TEST2
TEST1
VSS
COM16/SEG71
COM17/SEG70
COM18/SEG69
COM19/SEG68
COM20/SEG67
COM21/SEG66
COM22/SEG65
COM23/SEG64
COM24/SEG63
COM25/SEG62
COM26/SEG61
COM27/SEG60
COM28/SEG59
COM29/SEG58
COM30/SEG57
COM31/SEG56
SEG55
SEG54
SEG53
P02
P01
P00
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
Figure 1.3.1.1 Pin Arrangement (TQFP24-144-pin)

1 OVERVIEW
S1C17704 TECHNICAL MANUAL EPSON 1-5
PFBGA6U96
Top View Bottom View
A1 Corner A1 Corner
Index
A
B
C
D
E
F
G
H
J
K
L
A
B
C
D
E
F
G
H
J
K
L
11109876543211234567891011
N.C. N.C. N.C.
N.C. N.C. N.C.
N.C. N.C. N.C.
A
B
C
D
E
F
G
H
J
K
L
A
B
C
D
E
F
G
H
J
K
L
1
1
CB VC5 VC4
TEST2 CG CC
COM16
SEG71
TEST1
COM21
SEG66
COM20
SEG67
COM19
SEG68
N.C.
COM27
SEG60
COM25
SEG62
COM30
SEG57
COM28
SEG59
COM26
SEG61
N.C.
COM29
SEG58
N.C.
N.C.
COM31
SEG56
N.C.
COM24
SEG63
COM23
SEG64
COM22
SEG65
DSIO
P33
#RESET
#TEST
COM17
SEG70
COM18
SEG69
N.C.
P24
SOUT
P27
EXCL3
DST2
P32
N.C.
N.C.
N.C.
P21
SDO
P22
SPICLK
P23
SIN
TEST3
VD2
N.C.
P00
P16
EXCL0
P17
#SPISS
CF
CD
CE
P02
P01
P15
SCL
VC1
VC3
CA
P12
P05
REMO
N.C.
OSC4
VC2
P03
P11
P04
REMI
VD1
OSC3
VDDVSS
VDD
VSS
VSS
P10
P13
FOUT1
P14
SDA
P07
EXCL1
P06
EXCL2
N.C. N.C.
P20
SDI
P26
TOUT
P25
SCLK
N.C.
DCLK
P31
P30
FOUT3
N.C.
OSC2 OSC1
234567891011
2345678
Top View
91011
Figure 1.3.1.2 Pin Arrangement（PFBGA6U96）
Note: The LCD driver cannot be used with the PFBGA6U96 package. It should be used with COM31 to
16 left open.

1 OVERVIEW
1-6 EPSON S1C17704 TECHNICAL MANUAL
VFBGA7H-161
Top View Bottom View
A1 Corner A1 Corner
Index
13 12 11 10 987654321
A
B
C
D
E
F
G
H
J
K
L
M
N
A
B
C
D
E
F
G
H
J
K
L
M
N
123456789
10 11 12 13
N.C.
A
B
C
D
E
F
G
H
J
K
L
M
N
A
B
C
D
E
F
G
H
J
K
L
M
N
1
1
CB
SEG17
SEG16
SEG15
SEG18
SEG22
SEG26
SEG29
SEG32
SEG36
SEG41
SEG45
SEG49
SEG51
SEG53
SEG12
SEG13
SEG14
SEG21
SEG25
SEG28
SEG34
SEG38
SEG42
SEG46
SEG10
SEG8
SEG11
SEG19
SEG7
SEG6
SEG9
SEG5
SEG3
SEG2
SEG4
SEG1 SEG0
COM13
COM14
COM15
COM11
COM10
COM9
COM12
COM8
COM5
COM7
COM6
COM2
COM1
COM3
COM4 COM0
SEG24
SEG31
SEG35
SEG39
SEG43
SEG48
SEG50
SEG54
SEG55
SEG20
SEG23
SEG27
SEG30
SEG33
SEG37
SEG40
SEG44
SEG47
SEG52
VC5
VC4
TEST2
CG
CCCOM16
SEG71
TEST1
COM21
SEG66
COM20
SEG67
COM19
SEG68
COM27
SEG60
COM25
SEG62
COM30
SEG57
COM28
SEG59
COM26
SEG61
COM29
SEG58
N.C. N.C.
N.C.
COM31
SEG56
COM24
SEG63
COM23
SEG64
COM22
SEG65
DSIO
P33
#RESET
#TEST
COM17
SEG70
COM18
SEG69
P24
SOUT
P27
EXCL3
DST2
P32
P21
SDO
P22
SPICLK
P23
SIN
TEST3
VD2
P00
P16
EXCL0
P17
#SPISS
CF
CD
CE
P02
P01
P15
SCL
VC1
VC3
CA
P12
P05
REMO
OSC4VC2
P03
P11
P04
REMI
VD1
VDD
VDD
VDD
VSS
VSS VSS
VSS
VSS
VSS VSS VSS
VSS
VDD
VSS
VSS
VSS VSS VSS
P10
P13
FOUT1
P07
EXCL1
P06
EXCL2
P20
SDI
P25
SCLK
P30
FOUT3
P14
SDA
P26
TOUT
DCLK
P31
OSC2 OSC1
OSC3
234567891011
2345678
Top View
91011
12
12
13
13
Figure 1.3.1.3 Pin Arrangement（VFBGA7H-161）

1 OVERVIEW
S1C17704 TECHNICAL MANUAL EPSON 1-7
VFBGA10H-144
Top View Bottom View
A1 Corner A1 Corner
Index
12 11 10 987654321
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
123456789
10 11 12
SEG17
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
1
1
SEG18
SEG14
SEG16
SEG19
SEG22
SEG26
SEG29
SEG33
SEG42
SEG45
SEG49
SEG51
SEG53
SEG11
SEG13
SEG15
SEG21
SEG25
SEG28
SEG35
SEG41
SEG44
SEG48
SEG06
SEG10
SEG09
SEG12
SEG03
SEG04
SEG05
SEG07
COM14
COM15
SEG00
SEG01 COM11
COM08
COM09
COM10
COM05
COM04
COM07
COM06
COM00
P06
EXCL2
COM01
COM02
P12
P13
FOUT1
P01
P00 P02
SEG24
SEG31
SEG36
SEG40
SEG46
COM31
SEG56
SEG54
SEG55
SEG20
SEG23
SEG27
SEG30
SEG34
SEG38
SEG43
SEG47
SEG50
SEG52
VC5COM18
SEG69
CB
CC
VC3VD2
CF
COM16
SEG71
COM17
SEG70
COM19
SEG68
COM26
SEG61
COM29
SEG58
COM27
SEG60
COM25
SEG62
COM30
SEG57
COM22
SEG65
COM24
SEG63
COM21
SEG66
COM23
SEG64
COM20
SEG67
OSC1
RESET
OSC4
CG
DCLK
P31
P24
SOUT
VDD
TEST
DST2
P32
OSC2
P22
SPICLK
P23
SIN
CE
P03
P20
SDI
P27
EXCL3
CA
CD
P10
VC1VC4
P11
VC2
P04
REMI
P14
SDA
OSC3
VDD
VDD
SEG08
SEG32 TEST2
SEG37
SEG39
COM28
SEG59
VSS
VSS
VSS
SEG02 COM12 COM03
P05
REMO
P16
EXCL0
P07
EXCL1
P17
SPISS
P21
SDO
P30
FOUT3
P15
SCL
P26
TOUT
VD1
234567891011
234567891011
12
12
TEST1
COM13
TEST3 P25
SCLK
DSIO
P33
Top View
Figure 1.3.1.4 Pin Arrangement（VFBGA10H-144）

1 OVERVIEW
1-8 EPSON S1C17704 TECHNICAL MANUAL
1.3.2 Pin Descriptions
Table 1.3.2.1 Pin Descriptions
Pin No. Name I/O Default
status Function
QFP PFBGA
VFBGA7 VFBGA10
1 to 39 – ∗1∗2
SEG17 to 55
OO（L）LCD segment output pin
40 to 55 ∗3 ∗4∗5
COM31 to 16/
SEG56 to 71
OO（L）LCD common output pin*/LCD segment output pin
56 F2 ∗6∗7VSS – – Power supply pin (GND)
57 F3 K8 G6 TEST1 – – Flash test pin (open in normal operation)
58 E1 K7 F6 TEST2 – – Flash test pin (fixed at High in normal operation)
59 J7 J8 G7 TEST3 – – Flash test pin (open in normal operation)
60 K7 N8 M8 VD2 – – LCD circuit power supply booster output pin
61 E2 L9 L8 CG – – Power supply booster capacitor connector pin
62 J8 M9 K8 CF – – Power supply booster capacitor connector pin
63 L8 N9 J8 CE – – LCD booster capacitor connector pin
64 K8 K9 J9 CD – – LCD booster capacitor connector pin
65 E3 M10 K9 CC – – LCD booster capacitor connector pin
66 D1 N10 L9 CB – – LCD booster capacitor connector pin
67 L9 L10 M9 CA – – LCD booster capacitor connector pin
68 D2 K10 K10 VC5 – – LCD circuit drive voltage output pin
69 D3 J10 L10 VC4 – – LCD circuit drive voltage output pin
70 K9 N11 M10 VC3 – – LCD circuit drive voltage output pin
71 L10 M11 M11 VC2 – – LCD circuit drive voltage output pin
72 J9 L11 L11 VC1 – – LCD circuit drive voltage output pin
73 L11 ∗8∗9VDD – – Power supply pin (+)
74 K11 N12 L12 OSC3 I I OSC3 oscillator input pin
75 K10 M12 K11 OSC4 O O OSC3 oscillator output pin
76 H9 ∗6∗7VSS – – Power supply pin (GND)
77 J11 L12 K12 VD1 – – Internal logic and oscillator circuit constant-voltage
circuit output pin
78 H11 K13 J12 OSC1 I I OSC1 oscillator input pin
79 H10 K12 J11 OSC2 O O OSC1 oscillator output pin
80 C4 K11 H8 #TEST
(PFBGA, VFBGA7)
VDD/#TEST
(VFBGA10)
II（Pull-UP）Test pin (fixed at High in normal operation)
81 B4 J12 H11 #RESET II（Pull-UP）Initial set input pin
82 A4 J13 H12 DSIO/P33 I/O I（Pull-UP）
On-chip debugger data input/output pin*/ input/output
port pin
83 C5 J11 H10 DST2/P32 I/O O（L） On-chip debugger status output pin*/ input/output
port pin
84 G9 H13 G12 DCLK/P31 I/O O（H）On-chip debugger clock output pin*/ input/output
port pin
85 G10 H12 H9 P30/FOUT3 I/O I（Pull-UP）Input/output port pin*/ OSC3 dividing clock output
pin
86 B5 H10 G10 P27/EXCL3 I/O I（Pull-UP）Input/output port pin*/T16E external clock input
pin
87 F9 H11 G9 P26/TOUT I/O I（Pull-UP）Input/output port pin*/T16E PWM signal output pin
88 F10 G13 G11 P25/SCLK I/O I（Pull-UP）Input/output port pin*/UART clock input pin
89 A5 G12 G8 P24/SOUT I/O I（Pull-UP）Input/output port pin*/UART data output pin
90 C6 G11 F9 P23/SIN I/O I（Pull-UP）Input/output port pin*/UART data input pin
91 B6 F13 F12 P22/SPICLK I/O I（Pull-UP）Input/output port pin*/SPI clock input/output pin
92 A6 F12 F11 P21/SDO I/O I（Pull-UP）Input/output port pin*/SPI data output pin
93 E11 F11 F10 P20/SDI I/O I（Pull-UP）Input/output port pin*/SPI data input pin
94 C7 G10 E10 P17/#SPISS I/O I（Pull-UP）Input/output port pin (with interrupt)*/SPI slave
select input pin
95 B7 F10 E11 P16/EXCL0 I/O I（Pull-UP）Input/output port pin (with interrupt)*/T16 Ch.0
external clock input pin