ESD electronic XMC-CPU/2041 User manual

XMC-CPU/2041
XMC/PMC Quad Core PowerPC™ CPU
with FPGA
Hardware Manual
to Product V.2029.01
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 1 of 29
esd electronic system design gmbh
Vahrenwalder Str. 207 • 30165 Hannover • ermany
http://www.esd.eu
Phone: [phone] • Fax: [phone]

N O T E
The information in this document has been carefully checked and is believed to be entirely reliable.
e d makes no warranty of any kind with regard to the material in this document, and assumes no
responsibility for any errors that may appear in this document. In particular descriptions and
technical data specified in this document may not be constituted to be guaranteed product features
in any legal sense.
e d reserves the right to make changes without notice to this, or any of its products, to improve
reliability, performance or design.
All rights to this documentation are reserved by e d. Distribution to third parties, and reproduction
of this document in any form, whole or in part, are subject to e d's written approval.
© 2015 esd electronic system design gmbh, Hannover
esd electronic system design gmbh
Vahrenwalder Str. 207
30165 Hannover
Germany
Phone: [phone]
Fax: [phone]
E-Mail: [email protected]
Internet: www.esd.eu
Trademark Notices
PowerPC™ and the PowerPC logo™ are trademarks of IBM in the United States and/or other countries.
VITA™ is a trademark of the VMEbus International Trade Association in the United States and other countries.
PCI Express® is a registered trademark of PCI-SIG.
Linux® is the registered trademark of Linus Torvalds in the United States and/or other countries.
VxWorks® is a registered trademark of Wind iver Systems, Inc.
QNX® is a registered trademark of QNX Software Systems Limited, and are registered trademark and/or used in certain
jurisdictions.
All other trademarks, product names, company names or company logos used in this manual are reserved by their
respective owners.
Page 2 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041

Document file: I:\Texte\Doku\MANUALS\PMC-XMC\XMC-CPU2041\Englisch\XMC-CPU2041_Manual_en_14.odt
Date of print: 2015-06-23
Document type
number: DOC0800
Hardware ver ion: 1.0
Document Hi tory
The changes in the document listed below affect changes in the hardware as well as changes in
the description of the facts, only.
Revi ion Chapter Change ver u previou ver ion Date
1.0 - First English manual 2014-03-13
1.1 7.1 Note to bootloader source changed 2014-03-14
1.2 - Notes “Conformity” and “Data Safety” inserted in Safety Instructions 2014-12-01
1.3
1. Block circuit diagram new, description of options deleted
2015-04-15
3. Description of o-ring mounting inserted
4.1 Maximum absolute power inserted
4.2 Values of EEP OM and DD 3 AM changed
4.3 Description of optional interfaces deleted,
4.12 Chapter Software Support, Chapter Serial Interfaces via P14 (Option) deleted
8. Order Information revised
1.4
2.2 Figure 2 new
2015-06-23
2.3 Figure 3 new
5.6 New chapter, description of X900 adapters
5.7 New chapter, description of X400 adapter
8. Order Information, adapters inserted
Technical details are subject to change without further notice.
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 3 of 29

Safety In truction
● When working with the XMC-CPU/2041 follow the instructions below and read the manual carefully to protect yourself
from injury and the XMC-CPU/2041 from damage.
● The device is a built-in component. It is essential to ensure that the device is mounted in a way that cannot lead to
endangering or injury of persons or damage to objects.
● The device has to be securely installed in the control cabinet before commissioning.
● Protect the XMC-CPU/2041 from dust, moisture and steam.
● Protect the XMC-CPU/2041 from shocks and vibrations.
● The XMC-CPU/2041 may become warm during normal use. Always allow adequate ventilation around the XMC-
CPU/2041 and use care when handling.
● Do not operate the XMC-CPU/2041 adjacent to heat sources and do not expose it to unnecessary thermal radiation.
Ensure an ambient temperature as specified in the technical data.
● Do not use damaged or defective cables to connect the XMC-CPU/2041.
● In case of damages to the device, which might affect safety, appropriate and immediate measures must be taken, that
exclude an endangerment of persons and domestic animals and property.
● Current circuits which are connected to the device have to be sufficiently protected against hazardous voltage (SELV
according to EN 60950-1).
● The XMC-CPU/2041 may only be driven by power supply current circuits, that are contact protected.
A power supply, that provides a safety extra-low voltage (SELV or PELV) according to EN 60950-1, complies with this
conditions.
Attention !
Electro tatic di charge may cau e damage to electronic component .
To avoid this, please perform the steps described on page 10 before you touch the XMC-
CPU/2041, in order to discharge the static electricity from your body.
Qualified Per onal
This documentation is directed exclusively towards personal qualified in control and automation engineering.
The installation and commissioning of the product may only be carried out by qualified personal, which is authorized to
put devices, systems and electric circuits into operation according to the applicable national standards of safety
engineering.
Conformity
This device is a sub-assembly intended for incorporation into an apparatus by a manufacturer and NOT by the end user.
The manufacturer of the final system must decide, whether additional EMC or EMI protection requirements are
necessary.
Data Safety
This device is equipped with an Ethernet or other interface which is suitable to establish a connection to data networks.
Depending on the software used on the device, these interfaces may allow attackers to compromise normal function, get
illegal access or cause damage.
esd does not take responsibility for any damage caused by the device if operated at any networks. It is the responsibility
of the device's user to take care that necessary safety precautions for the device's network interface are in place.
Intended U e
The intended use of the XMC-CPU/2041 is the operation as XMC/PMC Quad Core PowerPC™ CPU with FPGA.
The guarantee given by esd does not cover damages which result from improper use, usage not in accordance with
regulations or disregard of safety instructions and warnings.
● The XMC-CPU/2041 is intended for installation on a base board according to IEEE 1386.1-2001 (PMC) or Vita 42.3
(XMC).
● The operation of the XMC-CPU/2041 in hazardous areas, or areas exposed to potentially explosive materials is not
permitted.
● The operation of the XMC-CPU/2041 for medical purposes is prohibited.
Service Note
The XMC-CPU/2041 does not contain any parts that require maintenance by the user. The XMC-CPU/2041 does not
require any manual configuration of the hardware.
Di po al
Devices which have become defective in the long run have to be disposed in an appropriate way or have to be returned
to the manufacturer for proper disposal. Please, make a contribution to environmental protection.
Page 4 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041

Table of content
1. Overview...................................................................................................................................... 6
2. XMC-CPU/2041 View with Connectors and LEDs........................................................................7
2.1 PCB Top Layer View with Connectors and LEDs...................................................................7
2.2 PCB Bottom Layer View with LEDs, JTAG and Debug Interface...........................................8
2.2.1 Indication of CON Activity (LED 1222) and USB PW (LED1230) ...............................8
2.3 Front Panel View with Connectors and LEDs........................................................................9
2.3.1 LED0-4 Indication of the TriColor LEDs ........................................................................9
3. Hardware Installation..................................................................................................................10
4. Technical Data...........................................................................................................................11
4.1 General Technical Data.......................................................................................................11
4.2 CPU and Memory................................................................................................................12
4.3 Ethernet Interface................................................................................................................12
4.4 USB, USB Host Interface.....................................................................................................12
4.5 CON, USB Device Interface.................................................................................................13
4.6 PMC Interface......................................................................................................................13
4.7 XMC Interface ..................................................................................................................... 13
4.8 I²C Interface.........................................................................................................................14
4.9 eal-Time Clock ( TC)........................................................................................................14
4.10 Digital In-/Outputs..............................................................................................................14
4.11 Health................................................................................................................................15
4.12 Software Support...............................................................................................................15
5. Connector Assignments.............................................................................................................16
5.1 USB, (USB Host, X1200).....................................................................................................16
5.2 CON, (USB Device, X1220).................................................................................................16
5.3 Ethernet ETH0, ETH1..........................................................................................................17
5.4 PMC Connectors..................................................................................................................18
5.4.1 PMC P11 Connector...................................................................................................18
5.4.2 PMC P12 Connector...................................................................................................19
5.4.3 PMC P14 I/O Connector..............................................................................................20
5.5 P15 PCI Express Interface...................................................................................................22
5.6 JTAG X900.......................................................................................................................... 23
5.6.1 XMC-CPU/2041-ADAPTE -BDI..................................................................................23
5.6.2 XMC-CPU/2041-ADAPTE -NXP................................................................................24
5.7 Debug Interface X400..........................................................................................................25
5.7.1 XMC-CPU/2041-ADAPTE -FPGA .............................................................................25
6. FPGA......................................................................................................................................... 26
7. Bootloader..................................................................................................................................27
7.1 License................................................................................................................................ 27
7.2 Configuration and Console Access......................................................................................27
8. Order Information....................................................................................................................... 29
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 5 of 29

Overview
1. Overview
Figure 1: Block circuit diagram
The XMC-CPU/2041 is an XMC PowerPC Host CPU.
It is a equipped with a PMC and an XMC interface.
The powerful FreescaleTM PowerPCTM QorIQ P2041 with 1.2 GHz is built on Power Architecture®
technology, bringing high-end architectural features pioneered in the P4 platform into the mid
range quad core space.
The local memory bus is 64 bits wide plus 8 bits ECC with an overall capacity of 512 Mbyte.
16 Mbyte SPI Flash for boot loader and 32 Kbit I²C EEP OM for U-Boot environment offer non-
volatile memory spaces.
The XMC-CPU/2041 is equipped with a second 16 Mbyte “fallback” SPI Flash that is used for
system recovery, if a system crash occurs during a firmware update.
The Xilinx® FPGA Spartan® 6 is connected to the CPU by local bus for low latency data exchange.
For high bandwidth data exchange the FPGA is additionally connected via PCI Express to the
CPU. 62 LVTTL-I/Os of the FPGA are routed to the PMC-P14 connector.
The XMC interface comes with 4-lane PCIe bus and is designed according to VITA 42.3.
The PMC interface supports 32 bit / 66 MHz PCI bus according to PCI Local Bus Specification 3.0,
3.3 V voltage level (5 V tolerant) and PCI bus master capability.
The XMC-CPU/2041 is equipped with two Gigabit Ethernet interfaces accessible at the front panel,
which give an excellent base for EtherCAT® applications.
The USB host port supports USB 2.0.
Page 6 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041
Memory Bus 64 bit
+ 8 bit ECC
PEX 1x
Pericom
PCIe to PCI
Bridge
PI7C9X111SL
PCI 32 bit 66 MHz
PEX 4x
PMC P11 PMC P12
XMC P15
FPGA - ear I/O
62x LVTTL (3.3 V)
PEX 1x
16Mbyte
Serial Flash
Muxed Local Bus + DMA
1 Gbyte
NAND Flash
GB Ethernet
Phy
Transformer
J45
GMII
GB Ethernet
Phy
Transformer
J45
USB 2.0
Serial
FTDI
USB / Serial
Converter
Mini A/BMini B
Bus Power
DD 3 AM
128 Mbyte
SPI
Health
I²C
I²C
I²C
SPI-Boot Order
A/D
Converter
Main Power
1.2V
1.5V
1.0V
CPU Temp.
T4 I²C T3T2T1
Temp. Sensors
PMC P14
Xilinx
Spartan 6
XC6LXT-45T
Freescale
Power PC
P2041
1200 MHz
Digital
Isolator
Electrical Isolation
GMII
I²C
DD 3 AM
512 Mbyte
16bit
8bit

XMC-CPU/2041 View with Connector and LED
2. XMC-CPU/2041 View with Connector and LED
2.1 PCB Top Layer View with Connector and LED
Figure 2: PCB top view
See also page 16 and following for signal assignments of the connectors.
The JTAG connector and the Debug interface connector have to be connected on the PCB bottom
side of XMC-CPU/2041 (see Figure 3 for the position of the connectors and pins).
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 7 of 29

XMC-CPU/2041 View with Connector and LED
2.2 PCB Bottom Layer View with LED , JTAG and Debug Interface
Figure 3: PCB bottom view
The Debug interface and the JTAG interfaces have to be connected from the bottom side of the
XMC-CPU/2041. See also page 16 and following for signal assignments of the connectors.
esd offers special adapters as accessories, see “Order Information” on page 29.
2.2.1 Indication of CON Activity (LED 1222) and USB PWR (LED1230)
LED Colour Indication De cription (LED on)
LED name
in schematic
diagram
CON Activity green Activity Data transfer on terminal interface CON LED1222
USB PWR green Power 5 V power supply voltage of USB interface on LED1230
Table 1: LEDs CON Activity and USB PW
Page 8 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041

XMC-CPU/2041 View with Connector and LED
2.3 Front Panel View with Connector and LED
Figure 4: Front panel view
2.3.1 LED0-4 Indication of the TriColor LED
Five TriColor LEDs are equipped in the front panel.
LED Colour De cription
Signal name
in schematic
diagram
LEDX
green
User-defined via FPGA and driver
LED10XG
red LED10X
blue LED10XB
(X = 0-4)
Table 2: LEDs 0 - 4
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 9 of 29

Hardware In tallation
3. Hardware In tallation
Read the afety in truction at the beginning of thi document carefully, before
you tart with the hardware in tallation!
Danger!
Electric shock risk. Never carry out work while power supply voltage is switched on!
Attention !
Electrostatic discharges may cause damage to electronic components.
To avoid this, please discharge the static electricity from your body before you touch
the XMC-CPU/2041.
Procedure:
1. Switch off your system and all connected peripheral devices (monitor, printer, etc.).
2. Discharge your body as described above.
3. Disconnect the system from the mains.
If the system does not have a flexible mains cable, but is directly connected to mains,
disconnect the power supply via the safety fuse and make sure that the fuse cannot switch
on again unintentionally (i.e. with caution label).
Danger!
Never carry out work while power supply voltage is switched on!
4. Open the case if necessary.
5. For sufficient EMC shielding the XMC-CPU/2041 should make contact to the system's
enclosure nearly completely around its front panel. For this purpose a conductive O-ring is
contained in the product package of the XMC-CPU/2041 module. Mount the conductive O-
ring on the front panel of the XMC-CPU/2041. Additionally or instead of it use shielding
material as for example conductive shielding gasket.
6. emove the carrier board (if already installed) and plug the XMC-CPU/2041 carefully on the
carrier board. Pay attention that the XMC-CPU/2041 is correctly installed on the carrier
board.
Fix the XMC-CPU/2041 with the screws on the carrier board. Use the four M 2.5 x 6 mm
screws which are contained in the product package of the module.
7. Install the carrier board in your system.
8. Close the case again (if necessary).
9. Connect the Ethernet and the USB interfaces via the connectors in the front panel of the
XMC-CPU/2041.
10. Connect the system to mains again (mains connector or safety fuse).
11. Switch on the system and the peripheral devices.
12. End of hardware installation.
Set the interface properties in your operating system. efer to the documentation of the
operating system.
Page 10 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041

Technical Data
4. Technical Data
4.1 General Technical Data
Power supply
voltage
Nominal voltage: depending on slot used:
PMC interface:
3.3 V / I3.3V_MAX = 2.5 A, I3.3V_TYPICAL = 2.2 A,
5V / I5V_MAX = 3 A, I5V_TYPICAL = 2.5 A
XMC interface:
3.3 V / I3.3V_MAX = 2.5 A, I3.3V_TYPICAL = 2.2 A,
12V / I12V_MAX = 1.5 A, I12V_TYPICAL = 1.2 A
Absolute maximum power: P3.3V+5V_MAX = 19 W
Connectors
ETH0
ETH1
J45 socket (X1300) - Ethernet Port 0
J45 socket (X1400) - Ethernet Port 1
CON Mini USB socket type-B (X1220) - Console (USB-Device)
USB Mini USB socket type-AB (X1200) - USB-Host
PMC P11
PMC P12
PMC P14
XMC P15
64-pin PMC connector (P11) - PMC PCI part 1
64-pin PMC connector (P12) - PMC PCI part 2
64-pin PMC connector (P14) - PMC IO
XMC, Samtec ASP-105885-04 - PCI Express interface
Only for test- and programming purposes:
Debug internal connector (under the heat sink), has to be connected
from the bottom side of the XMC-CPU/2041.
Samtec CLM108-02-F-D-BE (pass-thru micro socket, X900)
- Debug interface of the CPU and the Health Controller
JTAG Samtec CLM104-02-F-D-BE (pass-thru micro socket, X400),
has to be connected from the bottom side of the XMC-
CPU/2041.
- JTAG interface additionally via XMC-P11 and P12
Temperature
range
Operating temperature: -40 °C ... + 65 °C (600 LFM)
Storage temperature: -40 °C ... +105 °C ambient
Humidity 0% ... 90%, non-condensing
Dimensions 149 mm x 74 mm
Weight 190 g
Table 3: General data of the module
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 11 of 29

Technical Data
4.2 CPU and Memory
CPU Freescale PowerPC QorIQ P2041, 1.2 GHz, e500mc core
double precision floating point unit
AM 512 Mbyte AM 64-bit wide plus 8 bits ECC DD 3 AM
Flash memory (SPI) 16 Mbyte SPI FLASH for boot loader (standard) and
16 Mbyte SPI FLASH for system recovery,
selected via Health Subsystem.
EEP OM 1x 32 Kbit I²C EEP OM for U-Boot environment,
1x 4 Kbit AM SPD,
1x 32 Kbit EEP OM for Bootstrapping
NAND Flash 1 Gbyte NAND Flash for operating system connected via FPGA
DD 3 AM on FPGA 128 Mbyte AM connected to FPGA for FPGA usage,
with 16-bit wide interface
Table 4: CPU and memory
4.3 Ethernet Interface
Number of Ethernet
interfaces 2x Gigabit Ethernet (ETH0, ETH1)
Standard IEEE 802.3, 10BASE-T, 100BASE-TX, 1000BASE-T
Bit rate 10/100/1000 Mbit/s
Connection Twisted Pair (compatible to IEEE 802.3),
Electrical isolation Via transformer,
1500Vrms / 2250 VDC
Connector 2x at J-45-socket in the front panel
Table 5: Data of the Ethernet interfaces
4.4 USB, USB Ho t Interface
Number 1x USB host
Standard USB 2.0, max. 480 Mbit/s
Topology Host Controller integrated in CPU
Max. current per
port @5V
500 mA, short-circuit-protected
Electrical isolation None
Software support - OHCI-Host controller- and device driver
- driver of the operating system
Connector Mini USB type-AB socket in the front panel (USB)
Table 6: Data of the USB Host interface USB
Page 12 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041

Technical Data
4.5 CON, USB Device Interface
Number 1x Console (serial)
Standard USB 2.0 Full-Speed, the first serial interface of the CPU is provided via
an FTDI FT232 chip as USB Device.
The FT232 chip is supplied by USB.
Electrical isolation Via digital isolator
Connector Mini USB type-B socket in the front panel (CON)
Table 7: Data of the USB Device interface CON
4.6 PMC Interface
Standard PCI bus according to PCI Local Bus Specification 3.0,
32 bit 33/66 MHz, PCI bus master capability
Voltage 3.3 V, (5 V tolerant)
Frequency 33/66 MHz
Mode Monarch / non Monarch
Connector Via PMC P11 and PMC P12
Device ID / Vendor ID Constant 0x0410 / 0x1957
Subsystem Device ID /
Subsystem Vendor ID
0x0700 / 0x12FE as endpoint
Table 8: Data of the PMC interface
4.7 XMC Interface
Standard XMC according to VITA 42.3, 4-lane PCI EXP ESS® acc. to PCIe 1.1
Lanes 4
Mode As device
Connector Via XMC P15
Device ID / Vendor ID Constant, 0x0410 / 0x1957
Subsystem Device ID /
Subsystem Vendor ID
0x0701 / 0x12FE as endpoint
Table 9: Data of the XMC interface
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 13 of 29

Technical Data
4.8 I²C Interface
Number
3x I²C interface
- 1x for external use,
- 2x for internal use only!
Control Integrated in CPU
Bit rate 100Kbit, optional 400 Kbit
Physical Interface 3.3 V only, not 5 V tolerant.
1. I2C interface Devices: CPU Setup EEP OM, DD 3 AM SPD EEP OM, TC
2. IC2 interface Devices: PCIe to PCI Bridge, Health controller, U-Boot Env EEP OM.
3. I2C interface Devices: FPGA, connector P14 pin 63 SDA pin 64 SCL.
Table 10: Data of the I²C interface
4.9 Real-Time Clock (RTC)
Type Epson X8025SA
Connection I2C Bus
Accuracy +/-5 ppm at Tamb = 25 °C (< 30 s/month)
Buffer Goldcap, C = 0,8 F
Table 11: Microprocessor and Memory
4.10 Digital In-/Output
Number 62x LVTTL-IO
I/O-configuration As input or output configurable pins of the FPGA
Input switching threshold LVTTL 3.3 V // not 5V tolerant
Output current Depending on FPGA configuration, see XILINX data sheet
Electrical isolation None
Protection circuit None, current-limiting resistors are not provided.
Connector XMC-P14
Table 12: Data of the digital in-/outputs
Page 14 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041

Technical Data
4.11 Health
System for monitoring of the board's status.
Voltages Core voltage: 0.75 V,
1.0 V,
1.2 V,
1.5 V,
2.5 V,
3.3 V,
5 V_USB,
5 V_PMC,
XMC_VPW
Temperature monitor 4x I²C temperature sensors,
1x CPU integrated temperature diode
XMC-IPMI Support Data according to „IPMI Serial EEP OM F U Information“
Boot Selection of the SPI FLASH for booting, GPIO expander for various
control functions
4.12 Software Support
The flash memory carries the standard boot program U-boot and enables the XMC-CPU/2041 to
boot various operating systems from network or on-board SPI-Flash.
BSPs are available for VxWorks® and Linux®. Example source code for the FPGA is included in the
BSPs.
For the FPGA an esdACC (esd Advanced CAN Controller) implementation is available.
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 15 of 29

Connector A ignment
5. Connector A ignment
5.1 USB, (USB Ho t, X1200)
Device connector: 5-pin mini USB socket, standard type AB
Pin Po ition: Pin A ignment:
Pin CON
(X1220)
1VBUS
2 D-
3 D+
4 UID
5 GND
Signal De cription:
VBUS... +5 V power supply voltage
D+, D-... USB signal lines Data+, Data-
UID... Signal to distinguish between a host connection and a device connection:
- host connection: signal connected to the signal ground
- device connection: not connected
GND... eference potential
5.2 CON, (USB Device, X1220)
Device connector: 5-pin mini USB socket, standard type B
Pin Po ition: Pin A ignment:
Pin CON
(X1220)
1VBUS
2 D-
3 D+
4 -
5 GND
Signal De cription:
VBUS... +5 V power supply voltage
D+, D-... USB signal lines Data+, Data-
-... not connected
GND... eference potential
Page 16 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041
21 53 4
21 53 4

Connector A ignment
5.3 Ethernet ETH0, ETH1
Device connector: J45 socket, 8-pin
Pin Po ition:
Pin A ignment:
Pin Signal
1 MDI0+ (TP0+)
2 MDI0- (TP0-)
3 MDI1+ (TP1+)
4 MDI2+ (TP2+)
5 MDI2- (TP2-)
6 MDI1- (TP1-)
7 MDI3+ (TP3+)
8 MDI3- (TP3-)
S Shield
Signal De cription:
MDIx+, MDIx- ... Ethernet data lines (x = 0 - 3)
Shield... case shield, connected with the front panel of the XMC-CPU/2041.
Note:
Cables of category CAT5e or higher have to be used to grant the function in networks
with 1000 Mbit/s.
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 17 of 29
1 2 3 4 5 6 7 8
S

Connector A ignment
5.4 PMC Connector
The XMC-CPU/2041 uses the PMC connectors P11, P12 and P14.
The assignment of the connectors P11 and P12 is in accordance with IEEE1386.
P14 is assigned module-specific.
5.4.1 PMC P11 Connector
Pin Signal Signal Pin
1 TCK -12V 2
3 GND INTA# 4
5 INTB# INTC# 6
7 GND (P ESENT#) +5V 8
9 INTD# n.c. (reserved) 10
11 GND PMCAUX 12
13 PCI-CLK_IN GND 14
15 GND GNT# 16
17 EQ# +5V 18
19 VIO AD[31] 20
21 AD[28] AD[27] 22
23 AD[25] GND 24
25 GND C/BE3# 26
27 AD[22] AD[21] 28
29 AD[19] +5V 30
31 VIO AD[17] 32
33 F AME# GND 34
35 GND I DY# 36
37 DEVSEL# +5V 38
39 GND (PCIXCAP#) PCI_LOCK# 40
41 n.c. (SDONE#) n.c. (SBO#) 42
43 PA GND 44
45 VIO AD[15] 46
47 AD[12] AD[11] 48
49 AD[09] +5V 50
51 GND C/BE0# 52
53 AD[06] AD[05] 54
55 AD[04] GND 56
57 VIO AD[03] 58
59 AD[02] AD[01] 60
61 AD[00] +5V 62
63 GND n.c. ( EQ64#) 64
Page 18 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041

Connector A ignment
5.4.2 PMC P12 Connector
Pin Signal Signal Pin
1 +12V T ST# 2
3 TMS TDO 4
5 TDI GND 6
7 GND n.c. (reserved) 8
9 n.c. (reserved) n.c. (reserved) 10
11 n.c. (MODE2#) +3.3V 12
13 PCI- ST# n.c. (MODE3#) 14
15 +3.3V n.c. (MODE4#) 16
17 PME# GND 18
19 AD[30] AD[29] 20
21 GND AD[26] 22
23 AD[24] +3.3V 24
25 IDSEL AD[23] 26
27 +3.3V AD[20] 28
29 AD[18] GND 30
31 AD[16] C/BE2# 32
33 GND n.c. (IDSELB) 34
35 T DY# +3.3V 36
37 GND STOP# 38
39 PE # GND 40
41 +3.3V SE # 42
43 C/BE1# GND 44
45 AD[14] AD[13] 46
47 M66EN AD[10] 48
49 AD[08] +3.3V 50
51 AD[07] n.c. ( EQB#) 52
53 +3.3V n.c. (GNTB#) 54
55 n.c. (reserved) GND 56
57 n.c. (reserved) E EADY 58
59 GND ESETOUT# 60
61 n.c. (ACK64#) +3.3V 62
63 GND MONA CH# 64
XMC-CPU/2041 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 Page 19 of 29

Connector A ignment
5.4.3 PMC P14 I/O Connector
Standard
Pin A ignment Optional Pin A ignment
Pin Signal Name Note Alternative Signal Name* Note * Differential Pair*
(XILINX Name) Note *
1FPGA-IO<0> 3.3V, IO SGMII- X-N-<0> LVDIFF 74-N 3xSGMII option only
2FPGA-IO<1> 3.3V, IO SGMII-TX-P-<1> LVDIFF 61-N 3xSGMII option only
3FPGA-IO<2> 3.3V, IO SGMII- X-P-<0> LVDIFF 74-P 3xSGMII option only
4FPGA-IO<3> 3.3V, IO SGMII-TX-N-<1> LVDIFF 61-P 3xSGMII option only
5FPGA-IO<4> 3.3V, IO GND (when using SGMII 0 or 1) GND 60-N 3xSGMII option only
6FPGA-IO<5> 3.3V, IO SGMII- X-P-<1> LVDIFF 53-N 3xSGMII option only
7FPGA-IO<6> 3.3V, IO GND (when using SGMII 0 or 1) GND 60-P 3xSGMII option only
8FPGA-IO<7> 3.3V, IO SGMII- X-N-<1> LVDIFF 53-P 3xSGMII option only
9FPGA-IO<8> 3.3V, IO SGMII-TX-N-<0> LVDIFF 52-N 3xSGMII option only
10 FPGA-IO<9> 3.3V, IO SGMII- X-N-<2> LVDIFF 51-N 1 and 3xSGMII option only
11 FPGA-IO<10> 3.3V, IO SGMII-TX-P-<0> LVDIFF 52-P 3xSGMII option only
12 FPGA-IO<11> 3.3V, IO SGMII- X-P-<2> LVDIFF 51-P 1 and 3xSGMII option only
13 FPGA-IO<12> 3.3V, IO SGMII-TX-P-<2> LVDIFF 50-N 1 and 3xSGMII option only
14 FPGA-IO<13> 3.3V, IO GND (when using SGMII 0,1 or 2 ) GND 49-N 1 and 3xSGMII option only
15 FPGA-IO<14> 3.3V, IO SGMII-TX-N-<2> LVDIFF 50-P 1 and 3xSGMII option only
16 FPGA-IO<15> 3.3V, IO GND (when using SGMII 0,1 or 2 ) GND 49-P 1 and 3xSGMII option only
17 FPGA-IO<16> 3.3V, IO GND (when using SGMII 0,1 or 2 ) GND 48-N 1 and 3xSGMII option only
18 FPGA-IO<17> 3.3V, IO GND (when using SGMII 0,1 or 2 ) GND 47-N 1 and 3xSGMII option only
19 FPGA-IO<18> 3.3V, IO 48-P
20 FPGA-IO<19> 3.3V, IO ETH-MDC 3.3V, IO 47-P when using one of both
SGMII options
21 FPGA-IO<20> 3.3V, IO 46-N
22 FPGA-IO<21> 3.3V, IO ETH-MDIO 3.3V, IO 45-N when using one of both
SGMII options
23 FPGA-IO<22> 3.3V, IO 46-P
24 FPGA-IO<23> 3.3V, IO ETHINT3# 3.3V, IO 45-P when using one of both
SGMII options
25 FPGA-IO<24> 3.3V, IO 44-N
26 FPGA-IO<25> 3.3V, IO 43-N CLK Input
27 FPGA-IO<26> 3.3V, IO 44-P
28 FPGA-IO<27> 3.3V, IO 43-P CLK Input
29 FPGA-IO<28> 3.3V, IO 42-N CLK Input
30 FPGA-IO<29> 3.3V, IO 41-N CLK Input
31 FPGA-IO<30> 3.3V, IO 42-P CLK Input
32 FPGA-IO<31> 3.3V, IO 41-P CLK Input
* The optional pin assignment is only available on request.
Page 20 of 29 Hardware Manual • Doc. No.: V.2029.21 / ev. 1.4 XMC-CPU/2041