Epson S2R72A21 Installation and operating instructions

Rev.1.00
S2R72A21
Application Note

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©SEIKO EPSON CORPORATION 2020, All rights reserved.

S2R72A21 Application Note Seiko Epson Corporation i
(Rev.1.00)
Table of Contents
1. Description.................................................................................................................3
2. Terms & Abbreviations..............................................................................................4
3. Operation ...................................................................................................................5
3.1 Description.............................................................................................................................5
3.2 Basic system structure..........................................................................................................5
3.3 Basic operation......................................................................................................................7
3.3.1 Operation waveform..........................................................................................................7
3.3.2 Each operation..................................................................................................................8
3.4 HS transmission current control.........................................................................................11
4. Connection example................................................................................................12
4.1 Connection ex. Host SoC (on the same board)/INT port, Portable Device/EXT port........12
4.2 Connection ex. Host SoC (on the separate board)/INT port, Portable Device/EXT port ..13
4.3 Connection ex. Host SoC (on the separate board)/EXT port, Portable Device/INT port ..13
5. Operation within each connection example ..........................................................14
5.1 Connection ex. Host SoC (on the same board)/INT port, Portable Device/EXT port........15
5.1.1 ADJ settings....................................................................................................................15
5.1.2 BC control .......................................................................................................................15
5.1.3 Role Switch control..........................................................................................................15
5.1.4 Method to detect disconnection of Portable Device..........................................................15
5.2 Connection ex. Host SoC (on the separate board)/INT port, Portable Device/EXT port ..17
5.2.1 ADJ settings....................................................................................................................17
5.2.2 BC control .......................................................................................................................17
5.2.3 Role Switch control..........................................................................................................17
5.2.4 Method to detect disconnection of Portable Device..........................................................17
5.3 Connection ex. Host SoC (on the separate board)/EXT port, Portable Device/INT port ..19
5.3.1 ADJ settings....................................................................................................................19
5.3.2 BC control .......................................................................................................................19
5.3.3 Role Switch control..........................................................................................................19
5.3.4 Method to detect disconnection of Portable Device..........................................................19
6. USB Compliance test ..............................................................................................21
6.1 S2R72A21 function aimed at USB compliance test ...........................................................21
6.2 General Test method............................................................................................................21
6.2.1 High-speed Signal Quality...............................................................................................21
6.2.2 Test J / K.........................................................................................................................22
6.3 Test method with Evaluation board ....................................................................................22
6.3.1 Test environment.............................................................................................................22
6.3.2 Test procedure.................................................................................................................23
6.4 Cautions for each test..........................................................................................................25
6.4.1 EL_22..............................................................................................................................25
6.4.2 Full-speed Signal Quality.................................................................................................25
6.5 Compliance test for Host systems with S2R72A21............................................................25
6.6 Contact window regarding Compliance test ......................................................................26

ii Seiko Epson Corporation S2R72A21 Application Note
(Rev.1.00)
7. PCB design guide....................................................................................................27
7.1 Power supply and reset.......................................................................................................27
7.2 DP/DM signal line.................................................................................................................27
7.2.1 Circuit board wiring..........................................................................................................27
7.2.2 Additional component......................................................................................................27
7.3 Oscillator circuit...................................................................................................................29
7.4 Others precautions..............................................................................................................29
Revision History.............................................................................................................31

S2R72A21 Application Note Seiko Epson Corporation 3
(Rev.1.00)
1. Description
This document is the application note of the USB2.0 Re-Synchronization IC: S2R72A21.
This document explains the USB connection description, system implementation, compliance test for products
which equip S2R72A21 as well as the remark point during PCB designing using this Re-Synchronization IC.
Please refer to the S2R72A21 data sheet for Hardware related information.

4 Seiko Epson Corporation S2R72A21 Application Note
(Rev.1.00)
2. Terms & Abbreviations
The followings are the terms and abbreviations used within this application note.
Table 2.1 terms & abbreviation
Terms & abbreviation Definition
Attach
Operation when the cable is inserted or the moment when it is
inserted
ADJ pin
The pin of S2R72A21 which setup the HS transmit current
BC
Battery Charge
BC Regulator
Regulator which correspond to BC specification
Bus Reset
Bus reset which invoke HS detection handshake
Bus Switch
Bus switch which connect between the port (analog switch)
Chip Reset
Provide the reset signal to XRESET pin (S2R72A21)
Compliance Test USB product test to license the USB logo. USB-IF adds the product which passed the test to the
Integrators List, and grants license.
Connect
Condition which Device Rpu is ON
Detach
Operation when the cable is pulled out or the moment when it is
pulled out
Device
Device which is defined within the USB specification
Disconnect Condition where the USB connection via the S2R72A21 is shut
down electrically.
EOP
End-of-Packet
EXT port
External port of S2R72A21
FS
Full-Speed
FS_J
Bus state “J” during FS (Differential"1")
FS_K
Bus state “K” during FS (Differential"0")
Host
Host which is defined within the USB specification
The host issues the SOF.
Host SoC
The SoC which is a Host during initial conditions
HS
High-Speed
HS Synchronizer
Circuit which perform the Re-Synchronization
I2C
Inter-Integrated Circuit. A kind of serial interface.
INT port
Internal port of S2R72A21
LS
Low-Speed
Portable Device (PD)
Mobile device such as Smart phone or Tablet
Re-Synchronization To Re-synchronize the received HS packet from one port and
send it out to the other port
Role Switch
Switch positions between Host and Device
*Note: Role Switch here doesn’t mean the function of OTG
device which take role of host partially)
SOF
Start-of-Frame
USB-IF
USB Implementers Forum, Inc.
USB specification
Universal Serial Bus Specification Revision 2.0

S2R72A21 Application Note Seiko Epson Corporation 5
(Rev.1.00)
3. Operation
3.1 Description
S2R72A21 prepares 2 USB paths, Bus Switch and the HS Synchronizer.
The Bus switch electrically connects INT_DP/DM and EXT_DP/DM. The LS/FS signal or BC signals are passed
by.
The HS Synchronizer is a feature which re-synchronizes the HS signal received from either INT_DP/DM or
EXT_DP/DM and send out to the other port.
The objective paths are switched automatically by the internal Bus Monitor.
3.2 Basic system structure
As the basic system structure, here shows an example where S2R72A21 is mounted on the Car Navigation or
Display Audio’s board (Host SoC board). S2R72A21 intervenes between the Host SoC’s USB port and the USB
type-A receptacle, and connects the Host SoC (as Host) and Portable device such as smart phones (as Device).
The following is the pin connection example of S2R72A21 with this structure.
Figure 3.2.1 Basic system structure of S2R72A21
Host SoC board
S2R72A21
XRESET
HVDD
ENABLE
EN_DETACH
FRC_THR
TESTEN
ADJ2
ADJ1
ADJ0
SEL_I2C
INT_DP
INT_DM
ADJ4
ADJ3
EXT_DP
EXT_DM
EP
VSS
FVDD
LVDDC
LVDDM
R1
XI
XO
STAT1
STAT0
Slave
address
setting
Portable
Device
DP
DM
VBUS
Host SoC
BC
Regulator
SCL
SDA
I2C
master
DP
DM
ENABLE
GPIO
XRESET
HVDD
Regulator
HVDD
DP
DM
HVDP
HVDM
VBUS

6 Seiko Epson Corporation S2R72A21 Application Note
(Rev.1.00)
- INT_DP/DM : Please connect the Host SoC’s USB port.
Please connect the Host SoC’s USB OTG port in case Role Switch is executed. It is possible
to connect the BC Regulator for VBUS supply between the Host SoC’s USB OTG port and
the S2R72A21’s INT port.
BC Regulator can select the VBUS supply capability by negotiation with BC capable
Portable Device. If connected with non-BC capable portable Device, the VBUS supply
capability should be set to a fixed value or set by the Host SoC.
- EXT_DP/DM : Please connect to the USB Type-A receptacle.
Please connect or disconnect the portable device using a USB cable.
- ENABLE : Please control it via the Host SoC’s GPIO.
Please set “1” when it is able to connect to the Device, and set “0” when the Device is
disconnected
- EN_DETACH: Please set and stable it either to “0” or “1” on the boards. In this chapter, the case
EN_DETACH=0 is explained as the basic setting.
- FRC_THR : Please set and stable it to “0” on the boards.
- SEL_I2C : Please set and stable it either to “0” or “1” on the boards. In this chapter, the case
SEL_I2C=1 (I2C is in use) is explained as the basic setting.
- ADJ[4:0] : Please set and stable it either to “0” or “1” on the boards.
ADJ[4:0] pins are assigned as I2C slave function pins in case SEL_I2C=1.
ADJ[2:0] : Please set up either “0” or “1” on the boards and select the slave address.
ADJ[3] : Please pull up to the HVDD and connect SCL of the I2C master
ADJ[4] :Please pull up to the HVDD and connect SDA of the I2C master
- STAT[1:0] : This is outputting the internal condition. During default, it would be open drain (0/HiZ)
outputs. Please monitor according to the needs.
Please refer to chapter 4 and 5 for detail connection as well as the operation (example).

S2R72A21 Application Note Seiko Epson Corporation 7
(Rev.1.00)
3.3 Basic operation
The basic operation of the S2R72A21 under the above basic system structure is explained based on an example
of the USB2.0+BC operation waveform.
3.3.1 Operation waveform
Figure 3.3.1.1 shows an example of the S2R72A21 operation waveform on the basic system structure of Figure
3.2.1.
a) From Reset to HS operation (1)
b) From HS operation (1) to operation end
Figure 3.3.1.1 Basic operation waveform
HS_Packet
Detect SE0
for 5us
BC
HVDD
XRESET
ENABLE
State
INT_DP/DM
EXT_DP/DM
INITIAL DISCON-
NECT
Bus Switch (INT-EXT) HS Synchronizer
FS_LS HS
▼Attach
RESET
10ms
USB signal
path
Hi-Z
Reset Reset
released
Operation
start
FS
operation
Chirp
operation
HS
opearation(1)
Detect
ENABLE=1
BC
J
J
K
KK KJ J K KJ J ・・・
K KJ J K KJ J ・・・
FS D_Chirp
H_Chirp
5us
SOF
Bus Switch
(OFF)
10ms
passed
Detect SE0
for 3ms
HVDD
XRESET
ENABLE
State
INT_DP/DM
EXT_DP/DM
DISCONNECT
Bus Switch (INT-EXT)
HS Synchronizer
FS_LSHS
▼Detach
USB signal
path
Operation
end
Suspend
operation
Resume
operation
HS
operation(1)
J
J
K
K
Suspend
3ms
SOFHS_Packet
Resume
5us
HS Synchronizer
HS
SOF
SOF SOF
Bus Switch (INT-EXT)
FS_LS
Detect SE0
for 5us
HS detach
detection
HS
operation(2)
SOF
Detect
ENABLE=0
Disconnect
operation

8 Seiko Epson Corporation S2R72A21 Application Note
(Rev.1.00)
3.3.2 Each operation
Each operation for the figure above is explained in time order.
3.3.2.1 RESET condition
S2R72A21 maintains the RESET state during XRESET=0 condition after power on.
During this period, the Bus Switch along with HS synchronizer would be stopped so the internal USB signal
path’s condition would be disconnected. Within this condition the EXT port would be Hi-Z.
3.3.2.2 RESET release
Once the reset is released (XRSET=1), the S2R72A21 would transit to INITIAL state and furthermore, it would
transit to DISCONNECT state when it passes 10ms.
During this time, the USB signal path would connect the INT port and EXT port via the Bus Switch. Both INT
port and EXT port would be VSS level due to the pull down resistor of the BC Regulator.
3.3.2.3 Operation start
When the Host SoC set up to ENABLE=1, the S2R72A21 would transit to FS_LS state.
During this period, similar to DISCONNECT state, the USB signal path would connect INT port and EXT via the
Bus Switch. So both INT port and EXT port would maintain VSS level by the pull down resistor of the BC
Regulator.
Under this condition, if you attach the Portable Device (BC capable) to the EXT port as “Device”, a negotiation
would start between Portable Device and BC Regulator based on the BC protocol (below 0.6V signal level).
3.3.2.4 FS operation
When the BC negotiation finishes, the Portable Device would indicate the FS_J to the EXT port and notify the
IDLE condition.
During this time, the Bus Switch path of the USB signal would connect the INT port and EXT port, so the Host
SoC can detect the connection of the Portable Device (IDLE condition).
After detecting the Portable Device, the Host SoC enables its HS termination and issues the Bus Reset by driving
the SE0 to the INT port.
3.3.2.5 Chirp operation
After receiving the Bus Reset from the Host SoC, the Portable Device delivers Chirp K to the EXT port to
indicate that the Portable Device is capable of HS. After receiving this, the Host SoC delivers Chirp K-J to the
INT port to indicate the Host SoC is also capable of HS. These exchanges would occur during the HS termination
of the Host SoC is enabled, so resulting USB signal amplitude would be 800mV.
After detecting “Chirp K-J-K-J-K-J”, the Portable Device would also enable its HS termination. Due to this,
Chirp K-J’s amplitude would change from 800mV to 400mV.
S2R72A21 would detect this line of Chirp operation with Bus Monitor, and wait until this Chirp sequence is
finished.

S2R72A21 Application Note Seiko Epson Corporation 9
(Rev.1.00)
3.3.2.6 HS operation (1)
After the Chirp K-J delivery to the INT port from the Host SoC is finished, the S2R72A21 would judge that the
Chirp is finished by SE0 detection and it would transit to HS state.
During this period, the USB signal path would be switched from Bus Switch to HS Synchronizer. Please wait
over 5us until the first SOF transmit start from the Chirp delivery from the Host SoC is finished.
Within this condition, the HS signal from the Host SoC received from the INT port as well as the HS signal from
the Portable Device received from the EXT port would be sent out to the other ports after it has been
re-synchronized by HS Synchronizer. During this period, there would be packet delay since the HS Synchronizer
compensates the SYNC field to 32bit. So please make the Host SoC communicate with the scheduling
considering this point. And please be careful that the timeout (explained in section 7.1.19.2 of USB specification)
is not provoked, especially in case multi-tier hubs are connected.
Furthermore, during HS operation, either the INT port or the EXT port is detected as the SOF receiving port. The
HS disconnection detector circuit is validated for the port which does not receive the SOF. In this basic operation,
SOF is received at INT port from Host SoC, so HS disconnection detector circuit of the EXT port (Portable
Device side) is validated.
3.3.2.7 Suspend operation
During HS operation, if HS signal has not been received over 3ms with both INT and EXT port side, the
S2R72A21 would judge HS operation cease and the transition to FS_LS state would occur to prepare for any
Suspend detection.
During this time, the USB signal path would switch from HS Synchronizer to Bus Switch and the INTand EXT
port would be connected. Please do not make the Host SoC and Portable Device transmit any HS signal after
2.95ms from the last HS signal delivery.
After the USB signal path switches to Bus Switch, it would detect the EXT port condition. In case it detects SE0,
it would judge that the Host SoC is indicating Bus Reset. In case it detects FS_J, it would judge that the Host SoC
is indicating Suspend. The first case is to prepare for Chirp Operation. In the latter case, it maintains the USB
signal path along with the state of Suspend active while the FS_J is continuously detected.
3.3.2.8 Resume operation
During Suspend operation active, the detection of the EXT condition would be continued. In case the S2R72A21
detects SE0, it would judge the Host SoC is indicating Bus Reset. In case it detects FS_K, it would judge the
Host SoC is indicating Resume and the Suspend operation would be finished. The first case prepares for the
Chirp operation. In the latter case, the USB signal path would be maintained along with the Resume operation
active while the FS_K is continuously detected.
3.3.2.9 HS operation (2)
When SE0 is detected after the FS_K at EXT port, the S2R72A21 would judge that the Host released the Resume
and it would transit to HS state.
During this period, the USB signal path would switch from Bus Switch to HS Synchronizer. Please keep the Host
SoC waiting over 5us from Resume end to the first SOF transmission start.
After the Resume is released, the HS operation is maintaining condition before the Suspend. So the HS
disconnection detector circuit of the EXT port (Portable Device side) is validated again.

10 Seiko Epson Corporation S2R72A21 Application Note
(Rev.1.00)
3.3.2.10 Disconnect Operation
When the Portable Device is detached during HS operation, the HS termination of the Portable Devices would be
vanished and the amplitude of the EXT port’s HS signal would change from 400mV to 800mV. The validated HS
detector circuit (EXT port) would detect the amplitude variation by the SOF’s EOP (with 40bit time length).
When the Portable Device is judged “Detach” then the S2R72A21 would transit to FS_LS state.
During this period, the USB signal path would switch from HS Synchronizer to Bus Switch and the INT port and
EXT port would be connected.Afterward the HS packet which is transmitted from the Host SoC would by pass
from INT port to EXT port via the Bus Switch. Since the HS termination of the detached Portable Device has
been vanished, the Host SoC output would have amplitude of 800mV. Due to this, the Host SoC would be able to
detect the Portable Device has been detached using the Host SoC’s own HS disconnection detector circuit.
In case EN_DETACH=1, S2R72A21 would transit to DETACH state after detection of Portable Device. During
DETACH state, EXT port would be HiZ, since both the Bus Switch and the HS Synchronizer are stopped and the
internal USB path is disconnected. Due to this, the USB cable attached to the EXT port is omitted from the USB
signal path, so the Host SoC can detect the Portable Device detach with less influence of the returning wave.
When 3ms has passed, the S2R72A21 would transit to FS_LS state.
Figure 3.3.2.10.1 shows the disconnection operation waveform in case EN_DETACH=1.
Figure 3.3.2.10.1 Disconnection operation waveform in case EN_DETACH=1
3.3.2.11 Operation end
The Host SoC can notify the Detach detection to the S2R72A21 by ENABLE=0 once the Host SoC has detected
the Detach of the Portable Device. The S2R72A21 would transit to DISCONNECTstate when ENABLE=0.
Here the connection of the INT port and the EXT port is maintained. Both the INT port and the EXT port would
be VSS level due to the pull down resistor of the Host SoC.
Afterward, the S2R72A21 would start operation by ENABLE=1 again, and then the S2R72A21 is ready to accept
re-attach of the Device.
Please note that the S2R72A21 would also transit to DISCONNECTstate by setting XRESET 0→1 and 10ms
passes by. After detecting ENABLE=1, the S2R72A21 is ready to accept re-attach.
Detect SE0
for 3ms
HVDD
XRESET
ENABLE
State
INT_DP/DM
EXT_DP/DM
DISCONNECT
Bus Switch (INT-EXT)
HS Synchronizer
FS_LSHS
▼Detach
USB signal
path
Suspend
operation
Resume
operation
HS
opearetion(1)
J
J
K
K
Suspend
3ms
SOFHS_Packet
Resume
5us
HS Synchronizer
HS
SOF
SOF SOF
DETACH
Bus Switch
(OFF) Bus Switch (INT-EXT)
FS_LS
Detect SE0
for 5us
HS detach
detection
3ms
passed
HS
opearation(2)
SOF
Detect
ENABLE=0
3ms
Operation
end
Disconnect
operation
Hi-Z

S2R72A21 Application Note Seiko Epson Corporation 11
(Rev.1.00)
3.4 HS transmission current control
HS transmission current control function (ADJ function) is a feature which controls the current used for
transmitting from either INT or EXT port during HS connection. By this feature, it enables to control the
amplitude of the USB signal. Please refer to the S2R72A21 data sheet section 6.4.1 for details.
This section explains cautions when setting ADJ function.
Figure 3.4.1 shows a USB system example including USB cable and schematic diagrams of HS signal amplitude
in the form of Eye pattern.
Figure 3.4.1 A USB system example and schematic diagrams of HS signal amplitude
HS packets transmitted from the Host are re-synchronized by S2R72A21, and reach the Device through the USB
Cable. P1 is the signal measuring point at the S2R72A21 pin, and P2 is the signal measuring point at the Device.
The HS signal transmitted from the S2R72A21 is attenuated by the USB cable, etc., thus the signal amplitude at
P1 is greater than that at P2 as shown in the figure.
The S2R72A21 detects the disconnection when the SOF amplitude level exceeds the threshold at its pin.
Therefore, please configure the ADJ settings with care not to exceed the disconnect detection threshold at P1.
Host
DP
DM
Device
S2R72A21
INT_DP
INT_DM
EXT_DP
EXT_DM
USB Cable
DP
DM
NG
OK
P1
P2
HS
Packet HS
Packet

12 Seiko Epson Corporation S2R72A21 Application Note
(Rev.1.00)
4. Connection example
Please refer to the following in regard to the 3 system connection examples using S2R72A21. Please refer to
Chapter 5 for detail operation of each connection examples.
In addition, “EP” in the drawing stands for Exposed die pad.
In case where the Portable Device executes the Role Switch and the Bus is floating after the Role Switch, we
recommend pulling down the DP and DM of the Portable Device side (ex. 1MΩ).
4.1 Connection ex. Host SoC (on the same board)/INT port, Portable Device/EXT
port
Figure 4.1.1 Connection ex. Host SoC (on the same board)/INT port, Portable Device/EXT port
The same as the basic system structure shown on Figure 3.2.1.
Host SoC board
S2R72A21
XRESET
HVDD
ENABLE
EN_DETACH
FRC_THR
TESTEN
ADJ2
ADJ1
ADJ0
SEL_I2C
INT_DP
INT_DM
ADJ4
ADJ3
EXT_DP
EXT_DM
EP
VSS
FVDD
LVDDC
LVDDM
R1
XI
XO
STAT1
STAT0
Slave
address
setting
Portable
Device
DP
DM
VBUS
Host SoC
BC
Regulator
SCL
SDA
I2C
master
DP
DM
ENABLE
GPIO
XRESET
HVDD
Regulator
HVDD
DP
DM
HVDP
HVDM
VBUS

S2R72A21 Application Note Seiko Epson Corporation 13
(Rev.1.00)
4.2 Connection ex. Host SoC (on the separate board)/INT port, Portable
Device/EXT port
Figure 4.2.1 Connection ex. Host SoC (on the separate board)/INT port, Portable Device/EXT port
4.3 Connection ex. Host SoC (on the separate board)/EXT port, Portable
Device/INT port
Figure 4.3.1 Connection ex. Host SoC (on the separate board)/EXT port, Portable Device/INT port
Host SoC board
S2R72A21 board
S2R72A21
XRESET
HVDD
ENABLE
EN_DETACH
FRC_THR
TESTEN
ADJ4
ADJ3
ADJ2
ADJ1
ADJ0
SEL_I2C
INT_DP
INT_DM
EXT_DP
EXT_DM
EP
VSS
FVDD
LVDDC
LVDDM
R1
XI
XO
STAT1
STAT0
HS
transmission
current
control
BC
Regulator
Host SoC
DP
DM
VBUS
Portable
Device
DP
DM
VBUS
HVDD
Regulator
VBUS
HVDD
POR
Host SoC board
S2R72A21 board
S2R72A21
XRESET
HVDD
ENABLE
EN_DETACH
FRC_THR
TESTEN
ADJ4
ADJ3
ADJ2
ADJ1
ADJ0
SEL_I2C
EXT_DP
EXT_DM
INT_DP
INT_DM
EP
VSS
FVDD
LVDDC
LVDDM
R1
XI
XO
STAT1
STAT0
HS
transmission
current
control
BC
Regulator
Host SoC
DP
DM
VBUS
Portable
Device
DP
DM
VBUS
HVDD
Regulator
VBUS
HVDD
POR

14 Seiko Epson Corporation S2R72A21 Application Note
(Rev.1.00)
5. Operation within each connection example
Within the 3 system connection examples indicated on Chapter 4, we would explain each of the operation such as
the ADJ setting, BC control, Role Switch control and the disconnection detection control separately within
section 5.1-5.3. Table 5.1 is the summary of the connection, function, pin setting, disconnection detection control
for each system structure.
Role Switch is a function to switch the Host & Device role as indicated on Chapter 2, and some Portable Devices
have this function. S2R72A21 is a Re-Synchronization IC which also follows the Role Switch function.
In case where the Portable Device has the Role Switch function, there would be a negotiation to switch the role of
the Host and the Device after FS to HS connection (corresponding to the USB specification). After that the
Portable Device would play as a Host and issue the Bus reset and resume the HS communication again via FS to
HS connection.
As mentioned on the S2R72A21 Data sheet (section 6.1.1), S2R72A21 would transit from HS state to FS_LS
state automatically when over 3ms of SE0 is detected and the Bus Switch connection between INT-EXT would
be valid. In other words, within the above Role switch operation sequence, S2R72A21 would detect over 3ms of
SE0, automatically validate the Bus Switch in between INT-EXT for FS communication, and transit to HS
communication connection condition after Role Switch.
Table 5.1 Summary of each system structure
Section
USB port connection
Function
Pin
Disconnection
detection
control after
Role Switch
INT
EXT
I2C IF
HS transmission
current control
ADJ
4.1
5.1
Host SoC
(BC)
PD
Usable
INT/EXT
Fine adjustment
I2C
address
ENABLE pin
control; 0 to 1
4.2
5.2
Host SoC
(BC)
PD
Unusable
EXT only
Rough tuning
HS
transmissi
on current
control
VBUS supply:
Stop to resume
4.3
5.3
PD
Host SoC
(BC)
Unusable
EXT only
Rough tuning
HS
transmissi
on current
control
VBUS supply:
Stop to resume
BC = BC Regulator
PD = Portable Device

S2R72A21 Application Note Seiko Epson Corporation 15
(Rev.1.00)
5.1 Connection ex. Host SoC (on the same board)/INT port, Portable Device/EXT
port
5.1.1 ADJ settings
S2R72A21 is mounted on the same board as the Host SoC. Each of the ADJ4 pin (SDApin) andADJ3 (SCL pin)
are connected with the SoC’s I2C master. In this case, the HS transmit current control can all be possible to set
entire 4bit for both the INT and the EXT port by setting SEL_I2C=1 setting via I2C register. Please follow the
S2R72A21 data sheet’s section 4.2 Control Pin, and set up the ADJ4-0 pins.
5.1.2 BC control
The Bus Switch of S2R72A21 makes a connection between INT and EXT port when reset is released
(XRESET=1). After Portable Device is connected to the EXT port, the Portable Device would communicate with
the BC regulator (mounted on the same board) and determine the SDP/CDP/DCP by BC protocol. After the BC
protocol, the Portable Device would issue FS_J and the connection with Host SoC would start.
5.1.3 Role Switch control
If the Portable Device is a Device which does not execute the Role Switch, the Host SoC connected to the INT
side would consistently function as a Host, and the Portable Device connected to the EXT would act as a Device.
If the Portable Device is a Device which executes the Role Switch, the Portable Device which is connected to the
EXT port would become the Host via some designated process after HS connection.At the same time, the Host
SoC which is connected to the INT side would switch as a Device (In this case, the Portable Device and the Host
SoC would change its role nevertheless it’s naming. However for the convenience, within this documents would
keep calling the name as Portable Device and Host SoC). If the Bus becomes Floating during the Role Switch
period, we recommend to pull down the Bus by 1MΩand etc.
5.1.4 Method to detect disconnection of Portable Device
When the Portable Device does not execute the Role Switch, it requires the following 3 steps to make the USB
connection disconnected via S2R72A21.
1: Detection of HS disconnection by S2R72A21
S2R72A21 would detect the HS disconnection by detecting the SOF amplitude level changes which is sent
out by its EXT port.After that, in case EN_DETACH=0, the HS Synchronizer gets “Off”, Bus Switch
would be connected in between INT-EXT port and the transition to FS_LS state is done. In case
EN_DETACH=1, the S2R72A21 transiently gets into DETACH state for 3ms where both the HS
Synchronizer and the Bus Switch would get “Off”, and then the transition to FS_LS state is done where
the Bus Switch connects INT-EXT port. In case the total cable length of INT port and EXT port is long,
the EN_DETACH pin can be set to 1.
2: Detection of HS disconnection by Host SoC
Host SoC would also monitor the SOF amplitude level and detect the Portable Device disconnection via its
built in HS disconnection detector.
3: Notification of HS disconnection from the Host SoC to S2R72A21 (Optional)
Notification from the Host SoC to S2R72A21 of the disconnection detection can be done by ENABLE=0
as appropriate.
When the Portable Device executed the Role Switch, it requires the following 3steps to make the Host SoC detect
HS disconnection of the Portable Device.

16 Seiko Epson Corporation S2R72A21 Application Note
(Rev.1.00)
1: S2R72A21 would detect the SE0 condition and transit to FS_LS state
Since the periodic SOF sent from the Portable Device (as Host) is lost, the SE0 would be detected by EXT
port’s Bus state. When the S2R72A21 detects the SE0 condition for 3ms by the Bus state, the HS
Synchronizer’s operation would stop and the FS_LS state transition is done where the Bus Switch path
between INT-EXT gets “ON”.
Here, the Host (Portable Device) is lost and the Device (Host SoC) is left on the Bus. In this situation the
bus would deviate from the USB specification and the S2R72A21 may not follow the Bus state.
Furthermore, the bus state on the EXT port may be unstable depending on the contact situation of the
connector during detach, since the Portable Device is detached while packets are exchanged. This may
provoke malfunction of the S2R72A21.
2: Host SoC would judge HS disconnection by Bus invalid condition.
From the Bus Switch path connection, the Host SoC will judge the disconnection of the Portable Device
by detecting the EXT port’s Bus invalid condition for a certain period of time.
3: Notification of HS disconnection from the Host SoC to S2R72A21
Notification from the Host SoC to S2R72A21 of the disconnection detection is done by ENABLE=0.
This initializes the state which deviated from the USB specification, and fixes the malfunction caused by
the unstable contact situation of the connector during detach.
In all cases above, re-attach of the Portable Devices are accepted after recovering to ENABLE=1 (ENABLE=1:
the Bus Switch Path would return to the initial condition where the INT port and the EXT port are connected).

S2R72A21 Application Note Seiko Epson Corporation 17
(Rev.1.00)
5.2 Connection ex. Host SoC (on the separate board)/INT port, Portable
Device/EXT port
5.2.1 ADJ settings
The S2R72A21 would be connected to the Host SoC via USB cables only, so the HS transmit current control
function via the I2C register cannot be used. In this case please set SEL_I2C=0 and follow, section 4.2 control
pin of the S2R72A21 data sheet and set up the HS transmit current control function by ADJ2-0.
In addition, EXT port would only be able to control the transmit current (Portable Device side).
5.2.2 BC control
The Bus Switch of S2R72A21 makes a connection between INT and EXT port when reset is released
(XRESET=1).After Portable Device is connected to the EXT port, the Portable Device would communicate with
the BC regulator (mounted on the separate board) and determine the SDP/CDP/DCPby BC protocol.After the
BC protocol, the Portable Device would issue FS_J and the connection with Host SoC would start.
5.2.3 Role Switch control
If the Portable Device is a Device which does not execute the Role Switch, the Host SoC connected to the INT
side would consistently function as a Host, and the Portable Device connected to the EXT would act as a Device.
If the Portable Device is a Device which executes the Role Switch, the Portable Device which is connected to the
EXT port would become the Host via some designated process after HS connection.At the same time, the Host
SoC which is connected to the INT side would switch as a Device (In this case, the Portable Device and the Host
SoC would change its role nevertheless it’s naming. However for the convenience, within this documents would
keep calling the name as Portable Device and Host SoC). If the Bus becomes Floating during the Role Switch
period, we recommend to pull down the Bus by 1MΩ and etc.
5.2.4 Method to detect disconnection of Portable Device
When the Portable Device does not execute the Role Switch, it requires the following 3 steps to make the USB
connection disconnected via S2R72A21.
1: Detection of HS disconnection by S2R72A21
S2R72A21 would detect the HS disconnection by detecting the SOF amplitude level changes which is sent
out by its EXT port.After that, in case EN_DETACH=0, the HS Synchronizer gets “Off”, Bus Switch
would be connected in between INT-EXT port and the transition to FS_LS state is done. In case
EN_DETACH=1, the S2R72A21 transiently gets into DETACH state for 3ms where both the HS
Synchronizer and the Bus Switch would get “Off”, and then the transition to FS_LS state is done where
the Bus Switch connects INT-EXT port. In case the total cable length of INT port and EXT port is long,
the EN_DETACH pin can be set to 1.
2: Detection of HS disconnection by Host SoC
Host SoC would also monitor the SOF amplitude level and detect the Portable Device disconnection via its
built in HS disconnection detector.
3: S2R72A21 is stopped by Host SoC (Optional)
Notification from the Host SoC to S2R72A21 of the disconnection detection can be done by shut-off
VBUS supply as appropriate.
When the Portable Device executed the Role Switch, it requires the following 3steps to make the Host SoC detect
HS disconnection of the Portable Device.

18 Seiko Epson Corporation S2R72A21 Application Note
(Rev.1.00)
1: S2R72A21 would detect the SE0 condition and transit to FS_LS state
Since the periodic SOF sent from the Portable Device (as Host) is lost, the SE0 would be detected by EXT
port’s Bus state. When the S2R72A21 detects the SE0 condition for 3ms by the Bus state, the HS
Synchronizer’s operation would stop and the FS_LS state transition is done where the Bus Switch path
between INT-EXT gets “ON”.
Here, the Host (Portable Device) is lost and the Device (Host SoC) is left on the Bus. In this situation the
bus would deviate from the USB specification and the S2R72A21 may not follow the Bus state.
Furthermore, the bus state on the EXT port may be unstable depending on the contact situation of the
connector during detach, since the Portable Device is detached while packets are exchanged. This may
provoke malfunction of the S2R72A21.
2: Host SoC would judge HS disconnection by Bus invalid condition.
From the Bus Switch path connection, the Host SoC will judge the disconnection of the Portable Device
by detecting the INTport’s Bus invalid condition for a certain period of time.
3: S2R72A21 is stopped by Host SoC
Notification from the Host SoC to S2R72A21 of the disconnection detection is done by shut-off VBUS
supply.
This initializes the state which deviated from the USB specification, and fixes the malfunction caused by
the unstable contact situation of the connector during detach.
In all cases above, re-attach of the Portable Devices are accepted after recovering VBUS supply (VBUS supply:
the Bus Switch Path would return to the initial condition where the INT port and the EXT port are connected).
The disconnection detection notification cannot be done via the ENABLE pin since this connection example
would be done via USB cable only (between Host SoC and S2R72A21). In this case please reset the S2R72A21
as indicated above at 3Steps (Stop the VBUS supply and then resuming it). Please refer to the AC characteristics
on the Data sheet for the timings (VBUS supply stop to resume).