Texas Instruments TAS3002 Installation and user guide

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2001 Digital Audio: Digital Speakers
Data
Manua
l
SLAS307B

1−1
1 Introduction
1.1 Description
The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital
parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides
high-quality, soft digital volume, bass, and treble control. All control parameters are uploaded from an outside MCU
through the I2C slave port or from an external EEPROM through the I2C master port.
The TAS3002 device also has an integrated 24-bit stereo codec with two I2C-selectable, single-ended inputs per
channel.
The digital parametric equalization consists of seven cascaded, independent biquad filters per channel. Each biquad
filter has five 24-bit coefficients that can be configured into many different filter functions (such as band-pass,
high-pass, and low-pass).
The internal loudness contour algorithm can be controlled and programmed with an I2C command.
Dynamic range compression/expansion (DRCE) is programmable through the I2C port. The system designer can set
the threshold, energy estimation time constant, compression ratio, and attack and decay time constants.
The TAS3002 device supports 13 serial interface formats (I2S, left justified, right justified) with data word lengths of
16, 18, 20, or 24 bits. The sampling frequency (fS) may be set to 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface
formats are listed and described in Section 2.1.
The TAS3002 device uses a system clock generated by the internal phase-locked loop (PLL). The reference clock
for the PLL is provided by an external master clock (MCLK) of 256fSor 512fS, or a 256fScrystal.
The TAS3002 device has six internally configurable general-purpose input (GPI) terminals that control volume, bass,
treble, and equalization. Each GPI terminal has a debounce algorithm that is programmed into the TAS3002 internal
microcontroller.
1.2 Features
•Programmable seven-band parametric equalization
•Programmable digital volume control
•Programmable digital bass and treble control
•Programmable dynamic range compression/expansion (DRCE)
•Programmable loudness contour/dynamic bass control
•Configurable serial port for audio data
•Two input data channels that can be mixed with digital data from the analog-to-digital converter (ADC) of
the codec (analog input). These channels are controlled by I2C commands.
•Three output data channels: Left and right data go through equalization; bass, treble, DRCE, and volume
to SDOUT1; SDOUT2 mixes left and right data. SDOUT2 operates as a center channel or subwoofer
channel. The output of the ADC is available for additional processing.
•Capability to digitally mix left and right input channels for a monaural output to facilitate subwoofer operation
•Serial I2C master/slave port that allows:
− Downloading of control data to the device externally from the EEPROM or an I2C master
− Controlling other I2C devices

1−2
•Two I2C-selectable, single-ended analog input stereo channels
•Equalization bypass mode
•Single 3.3-V power supply
•Power down without reloading the coefficients
•Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz
•Master clock frequency of 256fSor 512fS
•Can have crystal input to replace MCLK. Crystal input frequency is 256fS.
•Six GPI terminals for volume, bass, treble up/down control, mute, and selection of equalization filters
1.3 Functional Block Diagram
Figure 1−1 is a block diagram showing the major functions of the TAS3002.

1−3
Control
PWR_DN
TEST
AINRP
AINRM
AINLM
AINLP
24-Bit
Stereo
ADC
RINA
RINB
AINRM
AINRP
AINLM
AINLP
LINA
LINB
Control
CS1
SDA
SCL
Controller
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
24-Bit
Stereo DAC
CAP_PLL
MCLK
XTALO
MCLKO
CLKSEL
SDIN2 SDIN1
SDATA
Control
LRCLK/O
SCLK/O
SDOUT1
L
L+R SDOUT2
32-Bit Audio Signal
Processor
AOUTL
VCOM
AOUTR
L+R
R32-Bit Audio Signal
Processor
OSC/CLK
Select PLL
Reference
Voltage Supplies Analog Supplies Digital
IFM/S
RESET
INPA
ALLPASS
XTALI/
AVSS(REF) VRFILT AVDD AVSS VREFM DVDD DVSS VREFP
I2C
SDOUT0
Figure 1−1. TAS3002 Block Diagram

1−4
1.4 Terminal Assignments
Figure 1−2 shows the terminal locations on the package outline, along with the signal name assigned to each
terminal.
14 15
NC
AVDD
NC
GPI5
GPI4
GPI3
GPI2
GPI1
GPI0
ALLPASS
SDOUT1
SDOUT0
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
LINA
VRFILT
AVSS(REF)
AVSS
INPA
RESET
CS1
PWR_DN
TEST
CAP_PLL
CLKSEL
MCLKO
17 18 19 20
AINRM AINRP AOUTR VCOM
47 46 45 44 4348 42
LINB AINLP
V
AINLM
40 39 3841
21 22 23 24
37
13
AOUTL RINA RINB
PACKAGE
(TOP VIEW)
XTALI/MCLK
XTALO
SCL
SDA
DVDD
DVSS
LRCLK/O
SCLK/O
IFM/S
SDIN1 SDIN2
SDOUT2
REFM
VREFP
Figure 1−2. TAS3002 Terminal Assignments
1.5 Terminal Functions
Table 1−1 lists the terminals in alphanumeric order by signal name, along with the terminal number, terminal type,
and a description of the terminal function.
Table 1−1. TAS3002 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AINLM 46 I ADC left channel analog input (antialias capacitor)
AINLP 47 I ADC left channel analog input (antialias capacitor)
AINRM 43 I ADC right channel analog input (antialias capacitor)
AINRP 42 I ADC right channel analog input (antialias capacitor)
ALLPASS 27 I Logic high bypasses equalization filters
AOUTL 39 O Left channel analog output
AOUTR 37 O Right channel analog output
AVDD 35 I Analog power supply (3.3 V)
AVSS 4 I Analog voltage ground
AVSS(REF) 3 I Analog ground voltage reference

1−5
Table 1−1. TAS3002 Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
CAP_PLL 10 I Loop filter for internal phase-locked loop (PLL)
CLKSEL 11 ILogic low selects 256fS; logic high selects 512fSMCLK
CS1 7 I I2C address bit A0; low = 68h, high = 6Ah
DVDD 17 I Digital power supply (3.3 V)
DVSS 18 I Digital ground
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
28
29
30
31
32
33
ISwitch input terminals
IFM/S 21 I Digital audio I/O control (low = input; high = output)
INPA 5 O Low when analog input A is selected (will sink 4 mA)
LINA 1 I Left channel analog input 1
LINB 48 I Left channel analog input 2
LRCLK/O 19 I/O Left/right clock input/output (output when IFM/S is high)
MCLKO 12 O MCLK output for slave devices
NC 34 No connection; Can be used as a printed circuit board routing channel
NC 36 No connection; Can be used as a printed circuit board routing channel
PWR_DN 8 I Logic high places the TAS3002 device in power-down mode
RESET 6 I Logic low resets the TAS3002 device to the initial state
RINA 40 I Right channel analog input 1
RINB 41 I Right channel analog input 2
SCL 15 I/O I2C clock connection
SCLK/O 20 I/O Shift (bit) clock input (output when IFM/S is high)
SDA 16 I/O I2C data connection
SDIN1 22 I Serial data input 1
SDIN2 23 I Serial data input 2
SDOUT0 25 O Serial data output from ADC
SDOUT1 26 O Serial data output (from internal audio processing)
SDOUT2 24 O Serial data output (a monaural mix of left and right, before processing)
TEST 9 I Reserved manufacturing test terminal; connect to DVSS
VCOM 38 O Digital-to-analog converter mid-rail supply (decouple with parallel combination of 10-µF and 0.1-µF
capacitors)
VREFM 45 I ADC minus voltage reference
VREFP 44 I ADC plus voltage reference
VRFILT 2 O Voltage reference low pass filter
XTALI/MCLK 13 I Crystal or external MCLK input
XTALO 14 I Crystal input (crystal is connected between terminals 13 and 14)

1−6

2−1
2 Audio Data Formats
2.1 Serial Interface Formats
The TAS3002 device works in master or slave mode.
In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can
be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be
connected to XTALI/MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK/O) and
20 (SCLK/O) becoming outputs to drive slave devices.
In the slave mode, IFM/S is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device
requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options
for selecting the clock rates. If the 512fSMCLK rate is selected, terminal 11 (CLKSEL) is tied high and an MCLK rate
of 512fSmust be supplied. If the 256fSMCLK is selected, CLKSEL is tied low and an MCLK of 256fSmust be supplied.
In both cases, an LRCLK of 64SCLK must be supplied.
•MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.
•If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I2S, right justified,
and left justified. Table 2−1 indicates how the 13 options are selected using the I2C bus and the main control register
(MCR, I2C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64fS.
Additionally, the 16-bit mode operates at 32fS.
Table 2−1. Serial Interface Options
MODE MCR BIT (6) MCR BIT (5−4) MCR BIT (1−0) SERIAL INTERFACE
SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0
0 0 00 00 16-bit, 32fS
1 1 00 00 16-bit, left justified, 64fS
2 1 01 00 16-bit, right justified, 64fS
3 1 10 00 16-bit, I2S, 64fS
4 1 00 01 18-bit, left justified, 64fS
5 1 01 01 18-bit, right justified, 64fS
6 1 10 01 18-bit, I2S, 64fS
7 1 00 10 20-bit, left justified, 64fS
8 1 01 10 20-bit, right justified, 64fS
9 1 10 10 20-bit, I2S, 64fS
10 1 00 11 24-bit, left justified, 64fS
11 1 01 11 24-bit, right justified, 64fS
12 1 10 11 24-bit, I2S, 64fS
Figure 2−1 through Figure 2−3 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the
different interface protocols.

2−2
2.2 Digital Output Modes
The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3.
2.2.1 MSB-First, Right-Justified, Serial-Interface Format
The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−1
shows the following characteristics of this protocol:
•Left channel is transmitted when LRCLK is high.
•The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.
•The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the
next rising edge of SCLK.
•If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
SCLK
LRCLK = fS
MSB LSB
………… …… MSB LSB ……
SDIN
MSB LSB
…… …… MSB LSB ……
Left Channel Right Channel
SDOUT ……
Figure 2−1. MSB-First, Right-Justified, Serial-Interface Format

2−3
2.2.2 I2S Serial-Interface Format
The normal output mode for the I2S serial-interface format is for 16, 18, 20, or 24 bits.
Figure 2−2 shows the following characteristics of this protocol:
•Left channel is transmitted when LRCLK is low.
•SDIN is sampled with the rising edge of SCLK.
•SDOUT is transmitted on the falling edge of SCLK.
•If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
SCLK
LRCLK = fS
X LSB
SDIN
X LSB
Left Channel Right Channel
SDOUT
……
……
…
…
MSB
MSB
X LSB
X LSB
……
……
…
…
MSB
MSB
Figure 2−2. I2S Serial-Interface Format

2−4
2.2.3 MSB-Left-Justified, Serial-Interface Format
The normal output mode for the MSB-left-justified, serial-interface format is for 16, 18, 20, or 24 bits.
Figure 2−3 shows the following characteristics of this protocol:
•Left channel is transmitted when LRCLK is high.
•The SDIN data is justified to the leading edge of the LRCLK.
•The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.
SCLK
LRCLK = fS
MSB LSB …… MSB LSB
……
SDIN
MSB LSB …… MSB LSB
……
Left Channel Right Channel
SDOUT
……
……
……
……
Figure 2−3. MSB-Left-Justified, Serial-Interface Format

2−5
2.3 Switching Characteristics
PARAMETER MIN TYP MAX UNIT
tc(SCLK) SCLK cycle time 325.5 ns
td(SLR) SCLK rising to LRCLK edge 20 ns
td(SDOUT) SDOUT valid from SCLK falling edge (see Note 1) (1/256fS) + 10 ns
tsu(SDIN) SDIN setup before SCLK rising edge 20 ns
th(SDIN) SDIN hold after SCLK rising edge 100 ns
f(LRCLK) LRCLK frequency 32 44.1 48 kHz
Duty cycle 50 %
NOTE 1: Maximum of 50-pF external load on SDOUT.
SCLK
LRCLK
SDIN1
SDIN2
SDOUT1
SDOUT2
SDOUT0
tc(SCLK)
td(SDOUT)
tsu(SDIN) th(SDIN)
td(SLR)
tf(SCLK)
tr(SCLK)
td(SLR)
Figure 2−4. For Right-/Left-Justified and I2S Serial Protocols

2−6

3−1
3 Analog Input/Output
The TAS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A or
B analog input is accomplished by setting a bit in the analog control register (ACR) by an I2C command. Additionally,
the TAS3002 device has a stereo 24-bit digital-to-analog converter (DAC).
3.1 Analog Input
Figure 3−1 shows the technique and components required for analog input to the TAS3002 device. The maximum
input signal must not exceed 0.7 Vrms. Selection of the above component values gives a frequency response from
20 Hz to 20 kHz at a sampling frequency of 48 kHz without alias frequency problems.
AINRP
AINRM
AINLM
AINLP
24-Bit
Stereo
ADC
RINA
RINB
AINRM
AINRP
AINLM
AINLP
LINA
LINB
Reference
Voltage
1200 pF
1200 pF
0.47 µF
0.47 µF
1
1
0.47 µF
0.47 µF
1
1
2
2
1Analog Inputs − Use 0.47 µF for 20-Hz Cutoff
2Anti-Alias Capacitors for fS= 48 kHz
Input Select Command
From Internal Controller
3 Tie unused analog inputs to analog ground through 0.1-µF capacitors.
Figure 3−1. Analog Input to the TAS3002 Device
3.2 Analog Output
3.2.1 Direct Analog Output
The full scale analog output from the TAS3002 device is 0.707 Vrms. It is referenced to VCOM which is approximately
1.5 Vdc. VCOM must be decoupled with the network shown in Figure 3−2.

3−2
AOUTR
10 µF
24-Bit
DAC
AOUTL
VCOM
+0.1 µF
AGND
Analog Output
(Adjust Capacitors for Desired
Low Frequency Response)
Figure 3−2. VCOM Decoupling Network
3.2.2 Analog Output With Gain
Because the maximum analog output from the TAS3002 device is 0.707 Vrms, the output level can be increased by
using an external amplifier. The circuit shown in Figure 3−3 boosts the output level to 1 Vrms (when it has a gain of
1.414) and provides improved signal-to-noise ratio (SNR). Since this circuit lowers the noise floor, THD + N is
improved also.
AOUTR
10 µF
Analog Output
(Adjust Capacitors for Desired
Low Frequency Response)
24-Bit
DAC
AOUTL
VCOM
+0.1 µF
AGND
+
−
+5 Op Amp/2
+
−
+5 Op Amp/2
TLV2362
or Equilvalent
TLV2362
or Equilvalent
C1
C2
C3
C5C5
C4
C1= C2= C3
C4= C5
Figure 3−3. Analog Output With External Amplifier

3−3
3.2.3 Reference Voltage Filter
Figure 3−4 shows the TAS3002 reference voltage filter.
0.1 µF
15 µF
+
0.1 µF
1 µF
+
0.1 µF
4 23 45
44VREFP
AVSS
AVSS(REF)
VRFILT
VREFM
TAS3002
Figure 3−4. TAS3002 Reference Voltage Filter

3−4

4−1
4 Audio Control/Enhancement Functions
4.1 Soft Volume Update
The TAS3002 device implements a TI proprietary soft volume update. This feature allows a smooth and
pleasant-sounding change from one volume level to another over the entire range of volume control (18 dB to mute).
The volume is adjustable by downloading a gain coefficient through the I2C interface in 4.16 format—4 bits for the
integer and 16 bits for the fractional part. NO TAG lists the 4.16 coefficients converted into dB for the range of –70
dB to 18 dB with 0.5-dB step resolution.
Right and left channel volumes can be unganged and set to different values. This feature implements a balance
control.
Volume is changed by writing the desired value into the volume control registers. This is done by asserting the
volume-up or volume-down GPI terminal (see Section 7.6.1) for a limited range of volume control. Alternatively,
volume control settings can be sent to the TAS3002 device over the I2C bus.
4.2 Software Soft Mute
Soft mute is implemented by loading all zeros in the volume control register. This causes the volume to ramp down
over a duration of 2048fSsamples to a final output of 0 (− infinity dB).
Soft mute can be enabled by either asserting the mute GPI terminal (see Section 7.6.1) or sending a mute command
over the I2C bus. Subsequent assertions of the mute GPI terminal toggle soft mute off and on.
4.3 Input Mixer Control
The TAS3002 device is capable of mixing and multiplexing three channels (SDIN1, SDIN2, and the ADC output) of
serial audio data. The mixing is controlled through three mixer control registers. This is accomplished by loading
values into the corresponding bytes of the mixer left gain (07h) and mixer right gain (08h) control registers. See
Figure 4−1 for a functional block diagram of the input mixer.
The values loaded into these registers are in 4.20 format—4 bits for the integer and 20 bits for the fractional part.
NO TAG lists the 4.20 numbers converted into dB for the range of –70 dB to 18 dB, although any positive 4.20 number
may be used.
To mute any of the channels, 0s are loaded into the respective mixer control register.
Mixer controls are updated instantly and can cause audible artifacts for large changes in setting when updated
dynamically outside of the fast load mode; therefore, it is desirable to use fast load in conjunction with the soft-volume
mode.
SDIN1, SDIN2, and the ADC output can be mixed with a user-selectable gain for each channel. The gain control
registers are represented in 4.20 format.

4−2
SDIN2_L 7 Biquad
Filters Tone Soft
Volume
DRCE
SDIN1_L
ADC_L
SDOUT1
7 Biquad
Filters Tone Soft
Volume
DRCE
SDIN2_R
SDIN1_R
ADC_R
SDOUT2
1/2 L + R_SUM
Right Channel Mix Coefficients
I2C Register Address 07h SDIN1 ^ SDIN2 ^ ADC
= (3) 24-Bit Right Mix Coefficient
Left Channel Mix Coefficients
I2C Register Address 08h = (3) 24-Bit Left Mix Coefficient
SDIN1 ^ SDIN2 ^ ADC
1/2
L_SUM
R_SUM
Figure 4−1. TAS3002 Mixer Function
4.4 Mono Mixer Control
The TAS3002 device contains a second mixer that performs the function of mixing left and right channel digital audio
data from the input mixer in order to derive a monaural channel. This mixer has a fixed gain of −6 dB so that full scale
inputs on L_sum and R_sum do not produce clipping on the resulting L+R_sum.
The output of this mixer is present on terminal 24 (SDOUT2) and is generally used for a digitally-mixed subwoofer
or center channel application.
4.5 Treble Control
The treble gain level may be adjusted within the range of 15 dB to –15 dB with 0.5-dB step resolution. The level
changes are accomplished by downloading treble codes (shown in NO TAG) into the treble gain register.
Alternatively, a limited range of treble control is available by asserting the treble-up or treble-down GPI terminal (see
Section 7.6.1).
The treble control has a corner frequency of 6 kHz at a 48-kHz sample rate.
The gain values for treble control can be found in Section NO TAG.

4−3
4.6 Bass Control
The bass gain level can be adjusted within the range of 15 dB to −15 dB with 0.5-dB step resolution. The level changes
are accomplished by downloading bass codes (shown in NO TAG) into the bass frequency control register.
Alternatively, a limited range of bass control is available by asserting the bass-up or bass-down GPI terminal (see
Section 7.6.1).
Bass control is a shelf filter with a corner frequency of 250 Hz at a 48-kHz sample rate.
The gain values for bass control can be found in Section NO TAG.
4.7 De-Emphasis Mode (DM)
De-emphasis is implemented in the DAC and is software controlled. De-emphasis is valid at 44.1 kHz and 48 kHz.
To enable de-emphasis, values are written into the analog control register via the I2C command. See Section 4.8 for
analog control register operation.
Figure 4−2 illustrates the frequency response of the de-emphasis mode.
Response (dB)
3.18
(50 µs) 10.6
(15 µs)
Frequency (kHz)
De-Emphasis
Figure 4−2. De-Emphasis Mode Frequency Response