ETAS ES1130.3 User manual

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ES1130.3
Simulation Controller Board
User’s Guide
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ES1130.3 Simulation Controller Board2
Copyright
The data in this document may not be altered or amended without special
notification from ETAS GmbH. ETAS GmbH undertakes no further obligation in
relation to this document. The software presented herein is provided on the
basis of a general license agreement or a single license. Using and copying is
only allowed in concurrence with the specifications stipulated in the contract.
Under no circumstances may any part of this document be copied, repro-
duced, transmitted, stored in a retrieval system or translated into another lan-
guage without the express written permission of ETAS GmbH.
© Copyright 2003 ETAS GmbH, Stuttgart
The names and designations used in this document are trademarks or brands
belonging to the respective owners.
Document QH110302 R1.0.1 EN TTN F 00K 103 453
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Contents 3
Contents
1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Areas of Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Main Processor - MPC750 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.2 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.3 MPC860T Communication Processor . . . . . . . . . . . . . . . . . . . . 12
2.1.4 Ethernet Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.5 Dual-Ported RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Pin Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 "Serial" Plug Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.2 "PC" Plug Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.3 Backplane Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 PC Connection Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Contents4
2.6 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Communicating with the Host PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.1 Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.2 MPC860T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.3 MPC750. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4ETAS Contact Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Introduction 5
1Introduction
This section contains information about the basic features and areas of imple-
mentation of the ES1130.3 Simulation Controller Board. A block diagram is
also included here to show the schematic layout of the board.
1.1 Functions
The ES1130.3 Simulation Controller Board is a universal processor module for
VMEbus systems. The module is composed of two PowerPC processors: an
MPC750, the high-performance main processor, and an MPC860T which acts
as a communication processor. The two processors are linked using a Dual-
Ported RAM. Each of the two processors has its own Flash ROM as program
memory and its own RAM.
The MPC750 processor is equipped with a VMEbus interface. The VMEbus
interface is designed for both master and slave access. The board can also be
used as the system controller.
The MPC860T communication processor has an Ethernet interface. The inter-
face can either be operated with 10 or 100 MBit/s. The data rate is recognized
automatically.
The board has the following features:
• fully adapted to automotive requirements, temperature range of -40 ....
85°C
• high-performance main processor
– MPC750 PowerPC with L2 cache
– SDRAM (SO-DIMM)
– Flash memory
–EEPROM
– Dual-Ported RAM to the VME bus (slave)
note
Some components of the board may be damaged or destroyed by electrostatic
discharges. Please keep the board in its storage package until it is installed.
The board should only be taken from its package, configured and installed at a
working place that is protected against static discharge.
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Introduction6
• VMEbus interface
– master interface: A16:D16, A24:D16, A40:MD32
– slave interface: A24:D16, A40:MD32
– interrupt controller
– system controller with automatic activation
– bus timer: BTO (256)
– auto-ID configuration
• high-performance host interface via Ethernet
– PowerPC MPC860T
–SRAM
– Flash memory
– Ethernet 10/100 MBit/s, automatic recognition
– Dual-Ported RAM to the MPC750
• JTAG interface as a test interface
•extensionsocket
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Introduction 7
The following figure shows the front panel and the position of the plug con-
nector.
Fig. 1-1 Front Panel
1.2 Areas of Implementation
The ES1130.3 Simulation Controller Board can be used in VMEbus systems
wherever high performance is necessary. The Ethernet interface provides a sim-
ple link to host PCs.
Possible areas of implementation include:
• high-performance simulation processor for real-time applications.
• control of VMEbus boards for data acquisition and signal generation.
ES1130.3
PC
SERIAL
MCD
MCI
MSF
SCD
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Introduction8
1.3 Block Diagram
The following figure shows you a block diagram of the ES1130.3 Simulation
Controller Board.
Fig. 1-2 Block Diagram
In the block diagram, you can see the communication processor (MPC860T)
and the main processor, MPC750. Both processors have their own memory
areas which are composed of Flash ROM and RAM. Data is exchanged
between the processors via the shared Dual-Ported RAM.
The communication processor, MPC860T, is equipped with an Ethernet inter-
face. The Ethernet interface can be operated with 10 or 100 MBit/s.
The connection to the VMEbus takes place via an interface of the main proces-
sor, MPC750. The interface allows both master and slave access attempts to
the VMEbus.
Extension Socket
MPC 860T DPR
256 kB
VME64
Slave
Interface
VME64
MPC 750
DPR
256 kB
FLASH
8 MB
SDRAM
64 MB
Memory Controller
Interupt Controller
L2 Cache
1 MB
VME64
Master
Interface
FLASH
4 MB
SRAM
1 MB
10/100
MBit/s
PC
UARTSERIAL
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Hardware 9
2 Hardware
This section contains a detailed functional description, the pin allocation of the
connectors and the technical data of the board.
2.1 Functional Description
This section describes each feature of the ES1130.3 Simulation Controller
Board. You will find information on the following subjects:
• main processor, MPC750
• VMEbus interface
• communication processor, MPC860T
• Ethernet interface
• Dual-Ported RAM
• power supply
2.1.1 Main Processor - MPC750
The MPC750 processor is the central processing unit of the board. It works at
a clock rate of 366 MHz.
The following sections provide you with detailed information on the compo-
nents of this unit.
Memory
The MPC750 can address the following memory areas.
Memory Area Size
SDRAM 64 MBytes
VMEbus master A24 16 MBytes
VMEbus master A40 1 GByte
Dual-Ported RAM to the MPC860T 256 KBytes
Dual-Ported RAM to the VMEbus 256 KBytes
EEPROM 8 KBytes
Flash ROM 8 MBytes
Tab . 2 -1 Memory Areas of the MPC750
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Hardware10
32-Bit-Counter (Decrementer)
The MPC750 has two 32-bit counters at its disposal. The counters are loaded
with a start value by writing to register addresses. Once the relevant release
bits have been set in the status register, the counters are counted downwards
at a rate of 16.66 MHz. The overflow from 0 to -1 results in an interrupt.
Watchdog
The board’s watchdog can be programmed to the intervals 4027 ms, 1007 ms,
252 ms and 63 ms. Once the supply voltage has been switched on, the longest
interval is set and the watchdog released. The watchdog can be locked via a
bit in the status register but can only be released by a switch-on cycle. A certain
byte sequence has to be written to the watchdog service register to reset the
watchdog.
Interrupt Controller
The MPC750 can react to interrupts from different sources. The following
interrupt sources can occur:
• interrupt of the 32-bit counters
• interrupts from the VMEbus
• MPC860T communication interrupt
• VMEbus slave communication interrupt
Different interrupt levels can be assigned to the different interrupt sources
using registers. Fixed vectors and priorities are allocated to the interrupt levels.
Interrupt level 0 has the highest priority and interrupt level 15 the lowest.
Every interrupt level can be released or locked individually using an interrupt
mask register.
Board Control and Status Register (BCSR)
The board control and status register is composed of different registers with
which different features and statuses of the board can be controlled or read.
The following are some of the available registers:
• configuration register board
• status register board
• interrupt controller: configuration and mask register
• counter
• system time
• VMEbus configuration and control register
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Hardware 11
• watchdog service register
The registers are used by the board’s firmware for controlling and monitoring
the hardware functions.
2.1.2 VMEbus Interface
The VMEbus interface can act both as a master and as a slave interface.
The board is linked as a VMEbus slave using shared memory areas which are in
the address space of the VMEbus and MPC750.
Master Interface
The master interface can execute A16, A24 and A40 accesses. Please consult
the following table for the size of the allocated memory areas and the relevant
address modifiers.
It is allowed for the MPC750 as VMEbus master to access the card-specific
configuration ROM / control and status register area (CR/CSR) in A24 mode.
The MPC750 is not, however, allowed to access the card-specific Dual-Ported
RAM as VMEbus master. This memory area can be read and written directly.
Before there is a master access to the VMEbus, the requester level and mode
have to be set via the board control and status register. The ES1130.3 Simula-
tion Controller Board supports a single-level arbiter.
The requester mode is oriented to the particular implementation. The setting
"release on request" is the most sensible for single-master systems.
Memory Area Modifier Size
A24 supervisory BLT 3F 16 MBytes
A24 supervisory program 3E 16 MBytes
A24 supervisory data 3D 16 MBytes
A24 non-privileged BLT 3B 16 MBytes
A24 non-privileged program 3A 16 MBytes
A24 non-privileged data 39 16 MBytes
CR/CSR 2F 16 MBytes
A16 non-privileged access 29 64 KBytes
A16 supervisory access 2D 64 KBytes
Vector fetch -14 bytes
A40 34 1 GByte
Tab . 2 -2 Access Variants of the VMEbus Master Interface
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Hardware12
In A40 mode, the MPC750 can address the entire A40 address space of the
VMEbus. The larger A40 address space is mapped to the smaller MPC750
address space via a segment register. The VMEbus A40 address is composed of
the bottom 30 bits of the MPC750 access address and 10 bits from the seg-
ment register.
Slave Interface
The VMEbus slave interface allows the VMEbus to access the Dual-Ported RAM
shared by the MPC750 and VMEbus.
The slave interface supports both A24 and A40 access attempts. The basic
address via which the Dual-Ported RAM can be accessed by the VMEbus, is
determined via a register in the CR/CSR area.
The Dual-Ported RAM is not allowed to be accessed via the proprietary VME-
bus master interface.
Configuration ROM / Control and Status Register (CR/CSR) Slave
The CR/CSR slave makes various configuration and status registers available for
the configuration of the board in concurrence with the VME64 norm.
The address position of the CR/CSR area is determined by the auto-ID cycle
after the supply voltage has been switched on.
The CR/CSR registers can be divided into the following areas:
• configuration ROM in concurrence with the VME64 norm
• card-specific configuration ROM
• card-specific control and status register
• control and status register in concurrence with the VME64 norm
VMEbus Slot1 Controller
The ES1130.3 Simulation Controller Board can independently recognize
whether it should act as a system controller or not. The ES1130.3 assumes this
function if it is in Slot1.
2.1.3 MPC860T Communication Processor
The MPC860T communication processor controls data transfer via the Ether-
net interface. It has its own Flash ROM and SRAM, as well as an internal inter-
rupt logic.
Data is exchanged between the MPC860T communication processor and the
main processor, MPC750, via the shared Dual-Ported RAM.
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Hardware 13
The MPC860T makes several other functions available:
•boardreset
• reset of the MPC750
• reset of the Ethernet interface driver
• /SYSRES of the VMEbus
• switching of the boot memory for the MPC750 from Flash or Dual-Ported
RAM
• switching of the boot memory from Flash or Dual-Ported RAM
• programming interface for firmware, EPLD and FPGA
• BDM interface
2.1.4 Ethernet Interface
The board is equipped with an Ethernet interface in concurrence with the 10/
100BaseT standard. To be able to come up to the requirements of operation in
automotive vehicles, a plug connector is used that does not actually conform
to this standard.
The Ethernet interface is responsible for the connection of the ES1130.3 Sim-
ulation Controller Board to a host processor. The interface can be operated
either with 10 or 100 MBit/s, half or full-duplex. Switching takes place auto-
matically.
Every ES1130.3 Simulation Controller Board is equipped with an individual Eth-
ernet address (MAC address) and a standard IP address. The standard settings
of the board when it is delivered to the customer can be found in the section
"Ethernet, IP Address and Subnet Mask" on page 19.
2.1.5 Dual-Ported RAM
The Dual-Ported RAM is used for the data exchange between the main proces-
sor, MPC750, and the communication processor, MPC860T. The access of the
two processors to the shared memory area is controlled by a semaphore regis-
ter.
The MPC860T can determine whether the MPC750 loads its boot program
from the Flash memory or from the Dual-Ported RAM after a reset via an out-
put. This mechanism makes it possible to load programs for the MPC750 via
the Ethernet interface of the MPC860T.
note
The PC connection cable CBE100-3 which is part of the delivery scope of the
ES1130.3 Simulation Controller Board is only suitable for the direct connection to
a host system.
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Hardware14
2.1.6 Power Supply
The board has its own +3.3 V voltage regulator. This means it can be operated
in card cages which only make +5 V supply voltage available. If the card cage
makes +3.3 V available, the card automatically switches to the external supply
with +3.3 V.
2.2 Hardware Configuration
The board has no jumpers or solder straps which have to be configured.
2.3 Displays
The meaning of the LEDs on the front panel is given in the following tables.
Tab . 2 -3 Meaning of the front panel LEDs
LED Status Meaning
MCD MPC750: Master CPU Display
Off Normal operation
On Reset on MPC750 (independent from the source)
Blinking - receiving L1-Message while active L1-Loader
- Failure: exeption, dependent on vector
MCI MPC750: Master CPU Interrupt
On Interrupt on MPC750
MSF VMEBus: Module/Sysfail
Off Normal operation
On Failure: SysFail on VMEbus generated;
(no failure while boot up or reset)
SCD MPC860: Slave CPU Display
Off Normal operation
On Error status firmware
Blinking Activity of Ethernet-Link: LED-Status (in msec)
on off on off
- no Link: 100 100 100 100
- 10 MBit-Link Half Duplex: 100 500 100 500
- 100 MBit-Link Half Duplex: 500 500 500 500
- 100 MBit-Link Full Duplex: 500 100 500 500
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Hardware 15
2.4 Pin Allocation
This section contains the pin allocation of the front-facing connector and the
backplane connector of the ES1130.3 Simulation Controller Board.
2.4.1 "Serial" Plug Connector
The "Serial" plug connector has three lines for the serial interface of the
MPC750 main processor.
Fig. 2-1 "Serial" Plug Connector
Pin Function Pin Function
1 reserved 2 RxD
3TxD 4reserved
5GND 6open
7reserved 8reserved
9 open
Tab . 2 -4 "Serial" Pin Allocation
5
9
2
8
7
4
3
61
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Hardware16
2.4.2 "PC" Plug Connector
The "PC" plug connector contains the lines for the Ethernet interface. The
plug connector is designed as a eight-pin Lemo socket of size 1B.
Fig. 2-2 "PC" Plug Connector
2.4.3 Backplane Connector
The following table shows the allocation of the 160-pin backplane connector.
The signals marked "/" are low-active.
Pin Function Pin Function
1 n.c. 5 TX-
2 n.c. 6 RX-
3n.c. 7n.c.
4RX+ 8 TX+
Tab . 2 -5 "PC" Pin Allocation
Pin Row z Row a Row b Row c Row d
1 open D00 /BBSY D08 open
2GND D01 /BCLR D09 open
3 open D02 /ACFAIL D10 open
4GND D03 /BG0IN D11 open
5 open D04 /BG0OUT D12 open
6GND D05 /BG1IN D13 open
7 open D06 /BG1OUT D14 open
8GND D07 /BG2IN D15 open
9 open GND /BG2OUT GND /GAP
10 GND SYSCLK /BG3IN /SYSFAIL open
Tab . 2 -6 VME 64 Pin Allocation
7
1
2
3
4
5
68
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Hardware 17
2.5 PC Connection Cable
A special cable is needed to connect the ES1130.3 Simulation Controller Board
to the PC: the cable is perfectly adapted to the requirements (resulting from
the high transfer rates).
Fig. 2-3 PC Connection Cable CBE100-X
11 open GND /BG3OUT /BERR open
12 GND /DS1 /BR0 /SysReset open
13 open /DS0 /BR1 /LWORD open
14 GND /WRITE /BR2 AM5 open
15 open GND /BR3 A23 open
16 GND /DTACK AM0 A22 open
17 open GND AM1 A21 open
18 GND /AS AM2 A20 open
19 open GND AM3 A19 open
20 GND /IACK GND A18 open
21 open /IACKIN res. A17 open
22 GND /IACKOUT res. A16 open
23 open AM4 GND A15 open
24 GND A07 /IRQ7 A14 open
25 open A06 /IRQ6 A13 open
26 GND A05 /IRQ5 A12 open
27 open A04 /IRQ4 A11 open
28 GND A03 /IRQ3 A10 open
29 open A02 /IRQ2 A09 open
30 GND A01 /IRQ1 A08 open
31 open -12 V +5 V Stby +12 V open
32 GND +5 V +5 V +5 V open
Pin Row z Row a Row b Row c Row d
Tab . 2 -6 VME 64 Pin Allocation
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Hardware18
The following table provides you with more information on other available
types of cable and their order numbers.
2.6 Technical Data
This section contains the technical data on the ES1130.3 Simulation Controller
Board in tabular form.
MPC750 Main Processor
MPC860T Communication Processor
Order Designation Abbreviation Order Number
PC connection cable, 3 m CBE100-3 F 00K 102 559
PC connection cable, 8 m CBE100-8 F 00K 102 571
PC connection cable, 20 m CBE100-20 F 00K 102 570
Microprocessor MPC750 PowerPC, 366 MHz, 64-bit
1 MByte L2 cache, bus rate 66 MHz
Memory 64-MByte SDRAM (SO-DIMM, 64 bit/burst)
8-MByte Flash (64-bit)
8-KByte parallel EEPROM
256-KByte Dual-Ported RAM to the VMEbus
256-KByte Dual-Ported RAM to the
MPC860T
Function modules 2 counters, 32-bit, programmable
Watchdog, programmable
Interrupt controller, programmable
Microprocessor MPC860T PowerPC, bus rate 50 MHz
Memory 1-MByte SRAM
4-MByte Flash
256-KByte Dual-Ported RAM to the MPC750
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Hardware 19
Ethernet, IP Address and Subnet Mask
VMEbus
Power Supply
Type 10/100BaseT, automatic configuration
Ethernet address (MAC) Individual for each board
IP address 192.168.40.11
Subnet mask 255.255.255.0
Type Master interface and slave interface
Access types: master interface A16:D16; A24:D16; A40:MD32
Access types: slave interface A24:D16; A40:MD32
Interrupter 2 interrupters; levels 1 to 7,
programmable
Interrupt handler 2 interrupt handlers; levels 1 to 7,
programmable
System controller Automatic Slot1 detection
Bus timer BTO (256)
Configuration Auto-ID procedure
With exclusive powering
with +5 V
+5 (-0.125, +0.25) V DC, max. 2400 mA
With powering with
+3.3 V and +5 V
+3.3 V DC, ±5%, max. 3600 mA
+5 (-0.125, +0.25) V DC, max. 500 mA
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