Exar XRT73L04B User manual

Exar Corporation 48720 Kato Road, Fremont CA, 94538 •[phone] •FAX [phone] •www.exar.com
XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
OCTOBER 2003 REV. 1.0.1
GENERAL DESCRIPTION
The XRT73L04B, 4-Channel, DS3/E3/STS-1 Line In-
terface Unit is a low power CMOS version of the
XRT73L04A and consists of four independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73L04B can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73L04B performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
•Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L04A
•Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
•Contains a 4-Wire Microprocessor Serial Interface
•Full Loop-Back Capability
•Transmit and Receive Power Down Modes
•Full Redundancy Support
•Uses Minimum External components
•Single +3.3V Power Supply
•Low Power CMOS design
•5V tolerant I/O
•-40°C to +85°C Operating Temperature Range
•Available in a Thermally Enhanced 144 pin LQFP
package
APPLICATIONS
•Digital Cross Connect Systems
•CSU/DSU Equipment
•Routers
•Fiber Optic Terminals
•Multiplexers
•ATM Switches
FIGURE 1. XRT73L04B BLOCK DIAGRAM
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF
Channel 2
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO
SClk
CS/(SR/DR)
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
Channel 0
Channel 1
Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
Device
Monitor
MTIP_(n)
MRing_(n)
DMO_(n)
Transmit
Logic Duty Cycle Adjust
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3_(n) STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) RxOFF RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)/
(LCV_(n))
Channel 3
Tx
Control

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
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TYPICAL APPLICATIONS
TRANSMIT INTERFACE CHARACTERISTICS:
•Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
from the line
•Integrated Pulse Shaping Circuit
•Built-in B3ZS/HDB3 Encoder (which can be dis-
abled)
•Contains Transmit Clock Duty Cycle Correction
Circuit on-chip
•Generates pulses that comply with the ITU-T G.703
pulse template (E3 applications)
•Generates pulses that comply with the DSX-3 pulse
template as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993
•Generates pulses that comply with the STSX-1
pulse template as specified in Bellcore GR-253-
CORE
•Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS:
•Integrated Adaptive Receive Equalization (optional)
and Timing Recovery
•Declares and Clears the LOS defect per ITU-T
G.775 requirements (E3 and DS3 applications)
•Meets Jitter Tolerance Requirements as specified
in ITU-T G.823_1993 (E3 Applications)
•Meets Jitter Tolerance Requirements as specified
in Bellcore GR-499-CORE (DS3 Applications)
•Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
•Built-in B3ZS/HDB3 Decoder (which can be dis-
abled)
•Recovered Data can be muted while the LOS Con-
dition is declared
•Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
•Receiver can be powered down in order to con-
serve power in redundancy designs
FIGURE 2. MULTICHANNEL ATM APPLICATION
ATM
Switch/
SAR XRT74L74
RPOS
RNEG
RxLineClk
XRT71D04 XRT73L04B
RRPOS
RRNEG
RRClk
RPOS
RNEG
RxClk
RPOS
RNEG
RxClk
RTIP
RRing
TTIP
TRing
TPOS
TNEG
TxLineClk
MClk TPOS
TNEG
TxClk
4 Channel E3/DS3 ATM
UNI 4 Channel E3/DS3 J/A 4 Channel E3/DS3 LIU
FIGURE 3. MULTISERVICE - FRAME RELAY APPLICATION
Frame
Relay XRT72L58
RPOS
RNEG
RxLineClk
XRT71D04 XRT73L04B
RRPOS
RRNEG
RRClk
RPOS
RNEG
RxClk
RPOS
RNEG
RxClk
RTIP
RRing
TTIP
TRing
TPOS
TNEG
TxLineClk
MClk
TPOS
TNEG
TxClk
8 Channel E3/DS3 Framer 2 x 4 Channel E3/DS3 J/A 2 x 4 Channel E3/DS3 LIU

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
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ORDERING INFORMATION
FIGURE 4. PIN OUT OF THE XRT73L04B IN THE 144 PIN TQFP PACKAGE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
XRT73L04B
MRing_2
MTIP_2
TTIP_2
TxAVDD_2
TRing_2
TxAGND_2
TxClk_3
TPData_3
TNData_3
TxAVDD_3
DMO_3
TTIP_3
TxAVDD_3
TRing_3
TxAGND_3
MTIP_3
MRing_3
TxAGND_3 TxAGND_1
MRing_1
MTIP_1
TxAGND_1
TRing_1
TxAVDD_1
TTIP_1
DMO_1
TxAVDD_1
TNData_1
TPData_1
TxClk_1
TxAGND_0
TRing_0
TxAVDD_0
TTIP_0
MTIP_0
MRing_0
E3_2 E3_3 STS1/DS3_2 LLB_2 RLB_2 RxAVDD_2 RRing_2 RTIP_2 RxAGND_2 REQEN_2 STS1/DS3_3 LLB_3 RLB_3 RxAVDD_3 RRing_3 RTIP_3 RxAGND_3 REQEN_3 REQEN_1 RxAGND_1 RTIP_1 RRing_1 RxAVDD_1 RLB_1 LLB_1 STS1/DS3_1 REQEN_0 RxAGND_0 RTIP_0 RRing_0 RxAVDD_0 RLB_0 LLB_0 LOSTHR ICT STS1/DS3_0
AGND_2
REGR/(RxClkINV)
LOSMUTEN
AGND_3
RLOL_3
RLOS_3
EXClk_2
RLOL_2
RLOS_2
RxDGND_2
RPOS_2
RNEG_2/LCV_2
RxClk_2
RxDVDD_2
EXClk_3
RxDGND_3
RPOS_3
RNEG3/LCV_3
RxClk_3
RxDVDD_3
EXDGNDA
EXDVDDA
TxOFF
TxAGND_2
DMO_2
TxAVDD_2
TAOS_2
TAOS_3
TxLEV_2
TxLEV_3
TxClk_2
TPData_2
TNData_2
NC
NC
NC
SDO/E3_0
SDI/E3_1
SClk/(RxOFF)
CS/(SR/DR)
RLOL_1
RLOS_1
EXClk_0
RLOL_0
RLOS_0
AGND_1
RxDGND_0
RPOS_0
RNEG_0/LCV_0
RxClk_0
RxDVDD_0
EXClk_1
RxDGND_1
RPOS_1
RNEG_1/LCV_1
RxClk_1
Host/(HW)
RxDVDD_1
AGND_0
TxAGND_0
DMO_0
TxAVDD_0
TAOS_0
TAOS_1
TxLEV_0
TxLEV_1
TxClk_0
TPData_0
TNData_0
NC
NC
NC
PART #PACKAGE OPERATING TEMPERATURE RANGE
XRT73L04BIV 144 Pin LQFP 20 X 20 X 1.4 mm -40oC to +85oC

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ......................................................................................................... 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... 1
Figure 1.XRT73L04B Block Diagram ................................................................................................................ 1
TYPICAL APPLICATIONS ................................................................................................................................. 2
Figure 2.MultiChannel ATM Application ............................................................................................................ 2
Figure 3.MultiService - Frame Relay Application .............................................................................................. 2
TRANSMIT INTERFACE CHARACTERISTICS: ..................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS: ....................................................................................................... 2
Figure 4.Pin out of the XRT73L04B in the 144 Pin TQFP package .................................................................. 3
ORDERING INFORMATION ....................................................................................................... 3
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTIONS (BY FUNCTION) ......................................................................................... 4
TRANSMIT INTERFACE ................................................................................................................................... 4
RECEIVE INTERFACE ..................................................................................................................................... 6
CLOCK INTERFACE ........................................................................................................................................ 7
OPERATING MODE SELECT ........................................................................................................................... 8
CONTROL AND ALARM INTERFACE ................................................................................................................. 9
MICROPROCESSOR INTERFACE .................................................................................................................... 11
POWER AND GROUND PINS ......................................................................................................................... 13
NOCONNECTION PINS ................................................................................................................................ 14
ELECTRICAL CHARACTERISTICS ........................................................................................... 15
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15
DC Electrical Characteristics .......................................................................................................... 15
AC Electrical Characteristics (See Figure 5) ........................................................................................................ 16
Terminal Side Timing Parameters (See Figure 6 and Figure 7) -- {(n) = 0, 1, 2 or 3 } ......................................... 16
Figure 5.Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel) .................. 17
Figure 6.Timing Diagram of the Transmit Terminal Input Interface ................................................................. 17
Figure 7.Timing Diagram of the Receive Terminal Output Interface ............................................................... 17
Line Side Parameters E3 Application ................................................................................................................... 18
Transmit Characteristics (see Figure 5) ............................................................................................................... 18
Line Side Parameters Sonet STS-1 Application ................................................................................................... 19
Transmit Characteristics (See Figure 5) ............................................................................................................... 19
Line Side Parameters DS3 Application ................................................................................................................ 20
Transmit Characteristics (see Figure 5) ............................................................................................................... 20
Figure 8.ITU-T G.703 Transmit Output Pulse Template for E3 Applications .................................................. 21
Figure 9.Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications ............................. 21
Figure 10.Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ........... 22
Figure 11.Microprocessor Serial Interface Data Structure .............................................................................. 22
Microprocessor Serial Interface Timing (See Figure 12) ...................................................................................... 23
Figure 12.Timing Diagram for the Microprocessor Serial Interface ................................................................. 23
SYSTEM DESCRIPTION .................................................................................................. 24
THE TRANSMIT SECTION - CHANNELS 0, 1, 2, AND 3 .................................................................................... 24
THE RECEIVE SECTION - CHANNELS 0, 1, 2 AND 3 ....................................................................................... 24
THE MICROPROCESSOR SERIAL INTERFACE ................................................................................................. 24
Table 1:Role of Microprocessor Serial Interface pins when the XRT73L04B is operating in the Hardware Mode
24
Figure 13.Functional Block Diagram of the XRT73L04B ................................................................................ 25

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
II
1.0 SELECTING THE DATA RATE ............................................................................................................... 25
1.1 CONFIGURING CHANNEL(N) ............................................................................................................ 25
Table 2:Hexadecimal Addresses and Bit Formats of XRT73L04B Command Registers ............................... 26
Table 3:Selecting the Data Rate for Channel(n) via the E3_(n) and STS-1/DS3_(n) input pins (Hardware Mode)
27
COMMAND REGISTER, CR4-(N) ........................................................................................................... 27
Table 4:Selecting the Data Rate for Channel(n) via the STS-1/DS3_(n) and the E3_(n) bit-fields within the Ap-
propriate Command Register (HOST Mode) ..................................................................................... 27
2.0 THE TRANSMIT SECTION ...................................................................................................................... 28
2.1 THE TRANSMIT LOGIC BLOCK ......................................................................................................... 28
Accepting Dual-Rail Data from the Terminal Equipment ................................................................... 28
Figure 14. The typical interface for the Transmission of Data in a Dual-Rail Format from the Transmitting Ter-
minal Equipment to the Transmit Section of a channel .................................................................... 28
Figure 15.The XRT73L04B Samples the data on the TPData and TNData input pins ................................... 28
Accepting Single-Rail Data from the Terminal Equipment ................................................................ 29
COMMAND REGISTER CR3-(N) ............................................................................................................ 29
Figure 16.The Behavior of the TPData and TxClk Input Sgnals, while the Transmit Logic Block is Accepting Sin-
gle-Rail Data from the Terminal Equipment ..................................................................................... 29
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................. 29
2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................... 29
B3ZS Encoding .................................................................................................................................. 29
Figure 17.An Example of B3ZS Encoding ...................................................................................................... 30
HDB3 Encoding ................................................................................................................................. 30
Figure 18.An Example of HDB3 Encoding ..................................................................................................... 30
Disabling the HDB3/B3ZS Encoder ................................................................................................... 30
COMMAND REGISTER CR3-(N) ............................................................................................................ 31
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY .................................................................................... 31
Figure 19.The Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications .................... 31
Figure 20.The Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ... 32
Enabling the Transmit Line Build-Out Circuit ..................................................................................... 32
COMMAND REGISTER, CR1-(N) ........................................................................................................... 32
Disabling the Transmit Line Build-Out Circuit .................................................................................... 32
COMMAND REGISTER, CR1-(N) ........................................................................................................... 33
Design Guideline for Setting the Transmit Line Build-Out Circuit ...................................................... 33
The Transmit Line Build-Out Circuit and E3 Applications .................................................................. 33
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L04B TO THE LINE ...................................... 33
Figure 21.Recommended Schematic for Interfacing the Transmit Section of the XRT73L04B to the Line .... 33
TRANSFORMER RECOMMENDATIONS .................................................................................................... 34
3.0 THE RECEIVE SECTION ......................................................................................................................... 35
3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L04B TO THE LINE ........................................ 35
Figure 22.Recommended Schematic for Interfacing the Receive Section of the XRT73L04B to the Line (Trans-
former-Coupling) .............................................................................................................................. 35
3.2 THE RECEIVE EQUALIZER BLOCK ................................................................................................... 36
Figure 23.The Typical Application for the System Installer ............................................................................ 36
Guidelines for Setting the Receive Equalizer ................................................................................... 36

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
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COMMAND REGISTER CR-2(N) ............................................................................................................ 37
3.3 CLOCK RECOVERY PLL .................................................................................................................. 38
The Training Mode ............................................................................................................................. 38
The Data/Clock Recovery Mode ........................................................................................................ 38
3.4 THE HDB3/B3ZS DECODER .......................................................................................................... 38
B3ZS Decoding (DS3/STS-1 Applications) ........................................................................................ 38
Figure 24.An Example of B3ZS Decoding ...................................................................................................... 38
HDB3 Decoding (E3 Applications) ..................................................................................................... 38
Figure 25.An Example of HDB3 Decoding ...................................................................................................... 39
Configuring the HDB3/B3ZS Decoder ................................................................................................ 39
COMMAND REGISTER CR3-(N) ............................................................................................................ 39
3.5 LOS DECLARATION/CLEARANCE ..................................................................................................... 39
The LOS Declaration/Clearance Criteria for E3 Applications ............................................................. 39
Figure 26.The Signal Levels that the XRT73L04B declares and clears LOS ................................................. 40
Figure 27.The Behavior of the LOS Output Indicator in response to the Loss of Signal and the Restoration of
Signal ................................................................................................................................................ 41
The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications ........................................ 41
Table 5:The ALOS (Analog LOS) Declare and Clear Thresholds for a given setting of LOSTHR and REQEN
(DS3 and STS-1 Applications) ........................................................................................................... 41
COMMAND REGISTER CR0-(N) ............................................................................................................ 42
COMMAND REGISTER CR2-(N) ............................................................................................................ 42
COMMAND REGISTER CR0-(N) ............................................................................................................ 42
COMMAND REGISTER CR2-(N) ............................................................................................................ 42
Muting the Recovered Data while the LOS is being Declared ........................................................... 42
COMMAND REGISTER CR3-(N) ............................................................................................................ 43
3.6 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT .
43
Routing Dual-Rail Format Data to the Receiving Terminal Equipment .............................................. 43
Figure 28.The typical interface for the Transmission of Data in a Dual-Rail Format, from the Receive Section of
the XRT73L04B to the Receiving Terminal Equipment .................................................................... 43
Figure 29.How the XRT73L04B outputs data on the RPOS and RNEG output pins ...................................... 44
Figure 30.The Behavior of the RPOS, RNEG, and RxClk signals when RxClk is inverted ............................. 44
COMMAND REGISTER CR3-(N) ............................................................................................................ 45
Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment ............ 45
COMMAND REGISTER CR3-(N) ............................................................................................................ 45
Figure 31.The typical interface for the Transmission of Data in a Single-Rail Format from the Receive Section
of the XRT73L04B to the Receiving Terminal Equipment ................................................................ 45
Figure 32.The behavior of the RPOS and RxClk output signals while the XRT73L04B is transmitting Single-Rail
data to the Receiving Terminal Equipment ....................................................................................... 46
3.7 SHUTTING OFF THE RECEIVE SECTION ........................................................................................... 46
COMMAND REGISTER CR3-(N) ............................................................................................................ 46
4.0 DIAGNOSTIC FEATURES OF THE XRT73L04B .................................................................................... 47
4.1 THE ANALOG LOCAL LOOP-BACK MODE ......................................................................................... 47
Figure 33. A channel operating in the Analog Local Loop-Back Mode ........................................................... 47
4.2 THE DIGITAL LOCAL LOOP-BACK MODE. ......................................................................................... 48

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
IV
COMMAND REGISTER CR4-(N) ............................................................................................................ 48
Figure 34.The Digital Local Loop-Back path within a given channel .............................................................. 48
COMMAND REGISTER CR4-(N) ............................................................................................................ 48
4.3 THE REMOTE LOOP-BACK MODE ................................................................................................... 49
Figure 35.The Remote Loop-Back path, within a given channel .................................................................... 49
COMMAND REGISTER CR4-(n) ............................................................................................................ 49
4.4 TXOFF FEATURES ......................................................................................................................... 50
COMMAND REGISTER CR1-(N) ............................................................................................................ 50
Table 6:The Relationship Between the TxOFF Input Pin, the TxOFF Bit Field and the State of the Transmitter
50
4.5 THE TRANSMIT DRIVE MONITOR FEATURES .................................................................................... 50
Figure 36.The XRT73L04B employing the Transmit Drive Monitor Features ................................................. 51
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE ................................................................................. 51
5.0 THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 51
5.1 DESCRIPTION OF THE COMMAND REGISTERS .................................................................................. 51
COMMAND REGISTER CR1-(N) ............................................................................................................ 51
Table 7:Hexadecimal Addresses and Bit Formats of XRT73L04B Command Registers ............................... 52
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ......................................................... 53
Command Register - CR0-(n) ............................................................................................................ 53
COMMAND REGISTER CR0-(N) ............................................................................................................. 53
COMMAND REGISTER CR1-(N) ............................................................................................................ 54
Command Register CR2-(n) .............................................................................................................. 54
COMMAND REGISTER CR2-(N) ............................................................................................................ 54
COMMAND REGISTER CR3-(N) ............................................................................................................ 55
COMMAND REGISTER CR4-(N) ............................................................................................................ 56
Table 8:Contents of LLB_(n) and RLB_(n) and the Corresponding Loop-Back Mode for Channel(n) ........... 56
5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................. 56
Figure 37.Microprocessor Serial Interface Data Structure ............................................................................. 57
Figure 38.Timing Diagram for the Microprocessor Serial Interface ................................................................ 58
ORDERING INFORMATION ..................................................................................................... 59
PACKAGE DIMENSIONS ........................................................................................................ 59
REVISION HISTORY ..................................................................................................................................... 60

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
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PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
PIN #NAME TYPE DESCRIPTION
34
25
3
12
TTIP_0
TTIP_1
TTIP_2
TTIP_3
OTransmit TTIP Output - Channel (n):
The XRT73L04B uses this pin along with TRing_(n) to transmit a bipolar
line signal via a 1:1 transformer.
32
23
5
14
TRing_0
TRing_1
TRing_2
TRing_3
OTransmit Ring Output - Channel (n):
The XRT73L04B uses this pin along with TTIP_(n) to transmit a bipolar
line signal via a 1:1 transformer.
42
30
139
7
TxClk_0
TxClk_1
TxClk_2
TxClk_3
ITransmit Clock Input for TPData and TNData - Channel (n):
This input pin must be driven at 34.368 MHz (for E3 applications),
44.736 MHz (for DS3 applications), or 51.84 MHz (for SONET STS-1
applications). The XRT73L04B uses this signal to sample the
TPData_(n) and TNData_(n) input pins. By default, the XRT73L04B is
configured to sample these two pins on the falling edge of this signal.
N OTE : If the XRT73L04B is operating in the HOST Mode, then the
device can be configured to sample the TPData_(n) and TNData_(n)
input pins on either the rising or falling edge of TxClk_(n).
41
29
140
8
TPData_0
TPData_1
TPData_2
TPData_3
ITransmit Positive Data Input - Channel (n):
The XRT73L04B samples this pin on the falling edge of TxClk_(n). If the
device samples a "1", then it generates and transmits a positive polarity
pulse to the line.
The data should be applied to this input pin if the Transmit Section is
configured to accept Single-Rail data from the Terminal Equipment.
N OTE : If the XRT73L04B is operating in the HOST Mode, then the
XRT73L04B can be configured to sample the TPData_(n) pin on either
the rising or falling edge of TxClk_(n).
40
28
141
9
TNData_0
TNData_1
TNData_2
TNData_3
ITransmit Negative Data Input - Channel (n):
The XRT73L04B samples this pin on the falling edge of TxClk_(n). If the
device samples a "1", then it generates and transmits a negative polarity
pulse to the line.
In Single-Rail Mode, this pin must be tied to GND to enable the HDB3/
B3ZS Encoder and Decoder, (internally pulled-down).
In Dual-Rail Mode this input is the N-Rail Data input.
N OTE : If the XRT73L04B is operating in the HOST Mode, then the
XRT73L04B can be configured to sample the TNData_(n) pin on either
the rising or falling edge of TxClk_(n).

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
5
44
43
137
138
TxLEV_0
TxLEV_1
TxLEV_2
TxLEV_3
ITransmit Line Build-Out Enable/Disable Select - Channel (n):
This input pin permits the Transmit Line Build-Out circuit, within Channel
(n), to be enabled or disabled. In E3 mode, this pin has no effect on the
transmit pulse shape.
Setting this pin to "High" disables the Line Build-Out circuit. In this
mode, Channel (n) outputs partially-shaped pulses onto the line via the
TTIP_(n) and TRing_(n) output pins.
Setting this pin to "Low" enables the Line Build-Out circuit within Chan-
nel (n). In this mode, Channel (n) outputs shaped pulses onto the line
via the TTIP_(n) and TRing_(n) output pins.
To comply with the Isolated DSX-3/STSX-1 Pulse Template Require-
ments per Bellcore GR-499-CORE or Bellcore GR-253-CORE:
1. Set thisinput pin to "1" if the cable length between the Cross-Connect
and the transmit output of Channel (n) is greater than 225 feet.
2. Set thisinput pin to "0" if the cable length between the Cross-Connect
and the transmit output of Channel (n) is less than 225 feet.
This pin is active only if the following two conditions are true:
a. The XRT73L04B is configured to operate in either the DS3 or SONET
STS-1 Modes.
b. The XRT73L04B is configured to operate in the Hardware Mode.
N OTE : This pin to should be tied to GND if the XRT73L04B is going to be
operating in the HOST Mode, (internally pulled-down).
131 TxOFF I Transmitter OFF Input:
Setting this input pin "High" turns off all of the Transmitter Sections. In
this mode the TTIP and TRing outputs are tri-stated.
N OTES :
1. This input pin controls the TTIP and TRing outputs even when
the XRT73L04B is operating in the HOST Mode.
2. For HOST Mode Operation, this pin is tied to GND if the Trans-
mitter is intended to be turned off via the Microprocessor Serial
Interface.
TRANSMIT INTERFACE
PIN #NAME TYPE DESCRIPTION

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
6
RECEIVE INTERFACE
PIN #NAME TYPE DESCRIPTION
59
53
121
127
RxClk_0
RxClk_1
RxClk_2
RxClk_3
OReceive Clock Output - Channel (n):
This output pin is the Recovered Clock signal from the incoming line sig-
nal for Channel (n). The Receive Section of Channel (n) outputs data via
the RPOS_(n) and RNEG_(n) output pins on the rising edge of this clock
signal.
Configure the Receive Section of Channel (n) to update the data on the
RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n)
by doing one of the following:
a. Operating in the Hardware Mode
Pull the RxClkINV pin to "High".
b. Operating in the HOST Mode
Write a "1" into the RxClkINV bit-field within the Command Register.
60
54
120
126
RNEG_0/LCV_0
RNEG_1/LCV_1
RNEG_2/LCV_2
RNEG_3/LCV_3
OReceive Negative Data Output - Channel (n):
The function of this pin is dependent on whether the 73L04A is in the
Hardware or HOST Mode (HOST/HW) and the condition of CS/(SR/DR).
a. Operating in the Hardware Mode
Receive Negative Data:
Setting the CS/(SR/DR) pin ”Low”, (Dual-Rail operation) this output pin
pulses "High" whenever Channel (n) has received a Negative Polarity
pulse in the incoming line signal at the RTIP_(n) and RRing_(n) inputs.
Line Code Violation:
When CS/(SR/DR) is set “High”, (Single-Rail operation), the B3ZS/HDB3
Encoder/Decoder is activated and the Line Code Violation signal is out-
put on this pin.
b. Operating in the HOST Mode
Receive Negative Data:
Writing a “0” to the (SR/DR)_(n) bit in the command register configures
channel(n) in the Dual-Rail Mode and activates RNEG_(n).
Writing a “1” to (SR/DR)_(n) bit of the Command Register configures the
Single-Rail Mode and activates LCV_(n).
If the B3ZS/HDB3 Decoder is enabled then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V")
is not reflected at this output.
61
55
119
125
RPOS_0
RPOS_1
RPOS_2
RPOS_3
OReceive Positive Data Output - Channel (n):
The function of this pin is dependent on the setting of the CS/(SR/DR)
pin.
Receive Positive Data
If CS/(SR/DR) is set “Low” (Dual-Rail Mode), this output pin pulses
"High" whenever Channel (n) has received a Positive Polarity pulse in
the incoming line signal at the RTIP_(n)/RRing_(n) inputs.
Data Output
If CS/(SR/DR) is set “High” (Single-Rail Mode), data is output on this pin.
If the B3ZS/HDB3 Decoder is enabled then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V")
is not reflected at this output.
79
87
102
94
RRing_0
RRing_1
RRing_2
RRing_3
IReceive Ring Input - Channel (n):
This input pin along with RTIP_(n) is used to receive the bipolar line sig-
nal from the Remote DS3/E3/STS-1 Terminal.

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
7
80
88
101
93
RTIP_0
RTIP_1
RTIP_2
RTIP_3
IReceive TIP Input - Channel (n):
This input pin along with RRing_(n) is used to receive the bipolar line sig-
nal from the Remote DS3/E3/STS-1 Terminal.
82
90
99
91
REQEN_0
REQEN_1
REQEN_2
REQEN_3
IReceive Equalization Enable Input - Channel (n):
Setting this input pin "High" enables the Internal Receive Equalizer
within Channel (n). Setting this pin "Low" disables the Internal Receive
Equalizer. The guidelines for enabling and disabling the Receive Equal-
izer are described in Section 3.2.
N OTE : This pin is ignored and should be tied to GND if the XRT73L04B
is going to be operating in the HOST Mode, (internally pulled-down).
110 RxClkINV I Invert RxClk_(n) Output - Select:
The function of this pin depends upon the mode of operation.
Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Section of all Chan-
nels to invert their RxClk_(n) clock output signals.
Setting this pin "Low" configures Channel(n) to output the recovered
data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of
RxClk_(n).
Setting this input pin "High" configures Channel (n) to output the recov-
ered data via the RPOS_(n) and RNEG_(n) output pins on the falling
edge of RxClk_(n).
N OTE : This pin is internally pulled “High”.
RECEIVE INTERFACE
PIN #NAME TYPE DESCRIPTION
CLOCK INTERFACE
PIN #NAME TYPE DESCRIPTION
66
57
115
123
EXClk_0
EXClk_1
EXClk_2
EXClk_3
IExternal Reference Clock Input - Channel (n):
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz
clock signal for DS3 applications or a 51.84 MHz clock signal for SONET
STS-1 applications.
The Channel (n) Clock Recovery PLL uses this signal as a Reference
Signal for Declaring and Clearing the Receive Loss of Lock Alarm. The
Clock recovery PLL also generates the exact clock for the LIU.
It is permissible to use the same clock that drives the TxClk_(n) input
pin.
It is permissible to operate the four Channels at different data rates.

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
8
OPERATING MODE SELECT
PIN #NAME TYPE DESCRIPTION
69 SR/DR/CS I Microprocessor Serial Interface - Chip Select Input/Encoder-
Decoder Disable Input:
The function of this pin depends upon whether the XRT73L04B is oper-
ating in the HOST Mode or in the Hardware Mode.
N OTE : This pin is internally pulled "High".
Hardware Mode - Receive Output Single-Rail/Dual-Rail Select:
In Hardware Mode, setting this pin “High” configures each of the four
channels to operate in the Single-Rail Mode. When each of the four
channels are configured to operate in the Single-Rail Mode, then the
Receive Section of each channel will output data via the RPOS_(n) out-
put pin.
N OTE : Tie the TNData_(n) input to GND to enable HDB3/B3ZS Encod-
ing and Decoding.
Setting this pin “Low” configures each of the four channels to operate in
the Dual-Rail Mode. When each of the four channels are configured to
operate in the Dual-Rail Mode, then the Receive Section of each chan-
nel will output data via both the RPOS_(n) and RNEG_(n) output pins.
N OTE : This input pin functions as the CS input pin, if the XRT73L04B
device has been configured to operate in the HOST Mode.
72
71
108
107
E3_0/SDO
E3_1/SDI
E3_2
E3_3
I/O
I
I
I
E3_Mode Select - Channel 0:
This pin has a dual function. In HOST mode, this pin functions as SDO.
E3_Mode Select - Channel 1
This pin has a dual function. In HOST mode,this pin functions as SDI.
E3_Mode Select - Channel 2
E3_Mode Select - Channel 3
Hardware Mode Operation - E3 Mode Select - Channel (n):
This input pin is used to configure Channel (n) of the XRT73L04B to
operate in the E3 or STS-1/DS3 Modes. Setting this input pin to "High"
configures Channel (n) to operate in the E3 Mode. Setting it "Low" con-
figures Channel (n) to operate in either the DS3 or STS-1 Modes,
depending upon the state of the STS-1/DS3_(n) input pin.
N OTE : This pin is internally pulled “Low” when XRT73L04B is in the
Hardware Mode.
73
83
106
98
STS1/DS3_0
STS1/DS3_1
STS1/DS3_2
STS1/DS3_3
ISTS-1/DS3 Select Input - Channel (n):
“High” for STS-1 and “Low” for DS3 Operation.
The XRT73L04B ignores this pin if the E3_(n) pin is set to "1".
This input pin is ignored if the XRT73L04B is operating in the HOST
Mode.
N OTE : This pin should be tied to GND if the XRT73L04B is going to be
operating in the HOST Mode, (internally pulled-down).

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
9
52 HOST/(HW)IHOST-Hardware Mode Select:
This input pin is used to enable or disable the Microprocessor Serial
Interface (e.g., consisting of the SDI, SDO, SClk, and CSpins).
Setting this input pin "High" enables the Microprocessor Serial Interface
(e.g. configures the XRT73L04B to operate in the HOST Mode). In this
mode,configuretheXRT73L04B viatheMicroprocessorSerialInterface.
When the XRT73L04B is operating in the HOST Mode, then it ignores
the states of many of the discrete input pins. Setting this input pin "Low"
disables the Microprocessor Serial Interface (e.g., configures the
XRT73L04B to operate in the Hardware Mode). In this mode, many of
the external input control pins are functional. (Internally Pulled-up)
OPERATING MODE SELECT
PIN #NAME TYPE DESCRIPTION
CONTROL AND ALARM INTERFACE
PIN #NAME TYPE DESCRIPTION
36
20
1
17
MRing_0
MRing_1
MRing_2
MRing_3
IMonitor Ring Input - Channel (n):
The bipolar line output signal from TRing_(n) can be connected to this
pin via a 270-ohm resistor in order to check for line driver failure. This
pin is internally pulled "High".
35
21
2
16
MTIP_0
MTIP_1
MTIP_2
MTIP_3
IMonitor Tip Input - Channel (n):
The bipolar line output signal from TTIP_(n) can be connected to this pin
via a 270-ohm resistor in order to check for line driver failure. This pin is
internally pulled "High".
48
26
133
11
DMO_0
DMO_1
DMO_2
DMO_3
ODrive Monitor Output - Channel (n):
If no transmitted AMI signal is present on MTIP_(n) and MRing_(n) input
pins for 128±32 TxClk periods, then DMO_(n) toggles and remains
"High" until the next AMI signal is detected.
46
45
135
136
TAOS_0
TAOS_1
TAOS_2
TAOS_3
ITransmit All Ones Select - Channel (n):
A "High" on this pin causes the Transmit Section, within Channel (n), to
generate and transmit a continuous AMI all “1’s" pattern onto the line.
The frequency of this "1’s" pattern is determined by TxClk_(n).
This input pin is ignored if the XRT73L04B is operating in the HOST
Mode.
N OTE : This pin should be tied to GND if the XRT73L04B is going to be
operating in the HOST Mode, (internally pulled-down).
64
67
117
114
RLOS_0
RLOS_1
RLOS_2
RLOS_3
OReceive Loss of Signal Output Indicator - Channel (n):
This output pin toggles "High" if Channel (n) has detected a Loss of Sig-
nal Condition in the incoming line signal.
The criteria that the XRT73L04B uses to declare an LOS Condition
depends upon whether the device is operating in the E3 or STS-1/DS3
Mode.
65
68
116
113
RLOL_0
RLOL_1
RLOL_2
RLOL_3
OReceive Loss of Lock Output Indicator - Channel (n):
This output pin toggles "High" if Channel (n) has detected a Loss of Lock
Condition. Channel (n) declares an LOL (Loss of Lock) condition if the
recovered clock frequency deviates from the Reference Clock frequency
(available at the EXClk_(n) input pin) by more than 0.5%.

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
10
60
54
120
126
RNEG_0/(LCV_0)
RNEG_1/(LCV_1)
RNEG_2/(LCV_2)
RNEG_3/(LCV_3)
OLine Code Violation - Channel (n):
The function of this pin is dependent on whether the XRT73L04B is in
the Hardware or HOST Mode (HOST/HW) and if CS/(SR/DR) is set
“High”.
Hardware Mode
Line Code Violation:
When CS/(SR/DR) is set “High”, (Single-Rail operation), the B3ZS/HDB3
Encoder/Decoder is activated and the Line Code Violation signal is out-
put on this pin.
HOST Mode
Receive Negative Data:
Writing a “1” to (SR/DR)_(n) bit of the Command Register configures the
Single-Rail Mode and activates LCV_(n).
If the B3ZS/HDB3 Decoder is enabled then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V")
is not reflected at this output.
74 ICT IIn-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a
high-impedance state to allow for in-circuit testing. This pin should be
set to "High" for normal operation.
This pin is internally pulled "High".
75 LOSTHR I Loss of Signal Threshold Control:
Forcing the LOSTHR pin to GND or VDD provides two settings. This pin
must be set to a “High” or “Low” level upon power up and should not be
changed during operation.
This pin is only applicable during DS3 or STS-1 operations.
76
84
105
97
LLB_0
LLB_1
LLB_2
LLB_3
ILocal Loop-back - Channel (n):
This input pin along with RLB_(n) dictates which Loop-Back mode Chan-
nel (n) is operating in.
A "High" on this pin with RLB_(n) set to "Low" configures Channel (n) to
operate in the Analog Local Loop-Back Mode.
A "High" on this pin with RLB_(n) also being set to "High" configures
Channel (n) to operate in the Digital Local Loop-Back Mode.
N OTE : This pin is ignored and should be tied to GND if the XRT73L04B
is going to be operating in the HOST Mode.
77
85
104
96
RLB_0
RLB_1
RLB_2
RLB_3
IRemote Loop-Back - Channel (n):
This input pin in conjunction with LLB_(n) dictates which Loop-Back
mode Channel (n) is operating in.
A "High" on this pin with LLB_(n) being set to "Low" configures Channel
(n) to operate in the Remote Loop-Back Mode.
A "High" on this pin with LLB_(n) also being set to "High" configures
Channel (n) to operate in the Digital Local Loop-Back Mode.
N OTE : This pin is ignored and should be tied to GND if the XRT73L04B
is going to be operating in the HOST Mode.
CONTROL AND ALARM INTERFACE
PIN #NAME TYPE DESCRIPTION

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
11
111 LOSMUTEN I MUTE-upon-LOS Enable Input (Hardware Mode):
This input pin is use to configure the XRT73L04B, while it is operating in
the Hardware Mode, to MUTE the recovered data via the RPOS_(n),
RNEG_(n) output pins whenever one of the Channels declares an LOS
conditions.
Setting this input pin “High" configures all Channels to automatically pull
the RPOS_(n) and RNEG_(n) output pins “Low” whenever it is declaring
an LOS condition, thereby MUTing the data being output to the Terminal
Equipment.
Setting this input pin "Low" configuresall Channelsto NOT automatically
MUTE the recovered data whenever an LOS condition is declared.
N OTES :
1. This pin is ignored and should be tied to GND if the XRT73L04B
is going to be operating in the HOST Mode.
2. This pin is internally pulled "Low".
CONTROL AND ALARM INTERFACE
PIN #NAME TYPE DESCRIPTION
MICROPROCESSOR INTERFACE
PIN # NAME TYPE DESCRIPTION
69 CS/
SR/DR IMicroprocessor Serial Interface - Chip Select Input/Encoder-
Decoder Disable Input:
The function of this pin depends upon whether the XRT73L04B is oper-
ating in the HOST Mode or in the Hardware Mode.
HOST Mode Operation - Chip Select Input:
The Local Microprocessor must assert this pin to "0" in order to enable
communication with the XRT73L04B via the Microprocessor Serial Inter-
face.
N OTE : This pin is internally pulled "High".
70 SClk/(RxOFF) I Microprocessor Serial Interface Clock Signal/Receiver Shut OFF
Input:
The function of this pin depends upon:
HOST Mode - Microprocessor Serial Interface Clock Signal:
This signal is used to sample the data on the SDI pin on the rising edge
of this signal. During Read operations the Microprocessor Serial Inter-
face updates the SDO output on the falling edge of this signal.
Hardware Mode - Receiver Shut OFF input:
Setting this input pin "High" shuts off all of the Receiver Sections. Set-
ting this input pin "Low" enables all of the Receive Sections for full oper-
ation.
71 SDI/E3_1 I Serial Data Input for the Microprocessor Serial Interface
This pin has a dual function.
HOST Mode:
To read or write data into the Command Registers over the Microproces-
sor Serial Interface, apply the Read/Write bit, the Address Values of the
Command Registers and Data Value to be written during Write Opera-
tions to this pin.
This input is sampled on the rising edge of the SClk pin.

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
12
72 SDO/E3_0 O Serial Data Output from the Microprocessor Serial Interface
The function of this pin depends upon the mode of operation.
HOST Mode Operation:
This pin serially outputs the contents of the specified Command Register
during Read Operations. The data on this pin is updated on the falling
edge of the SClk input signal. This pin is tri-stated upon completion of
data transfer.
110 REGR/
RxClkINV IRegister Reset Input (Invert RxClk_(n) Output - Select):
The function of this pin depends upon the mode of operation.In Hard-
ware mode, this pin functions as RxClkINV.
HOST Mode - Register Reset Input:
Setting this input pin "Low" causes the XRT73L04B to reset the contents
of the Command Registers to their default settings and to its default
operating configuration.
N OTE : This pin is internally pulled “High”.
MICROPROCESSOR INTERFACE
PIN # NAME TYPE DESCRIPTION

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
13
POWER AND GROUND PINS
PIN # NAME TYPE DESCRIPTION
4 TxAVDD_2 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)
6 TxAGND_2 **** Transmitter Analog Ground - Channel(n)
10 TxAVDD_3 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)
13 TxAVDD_3 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)
15 TxAGND_3 **** Transmitter Analog Ground - Channel(n)
18 TxAGND_3 **** Transmitter Analog Ground - Channel(n)
19 TxAGND_1 **** Transmitter Analog Ground - Channel(n)
22 TxAGND_1 **** Transmitter Analog Ground - Channel(n)
24 TxAVDD_1 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)
27 TxAVDD_1 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)
31 TxAGND_0 **** Transmitter Analog Ground - Channel(n)
33 TxAVDD_0 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)
47 TxAVDD_0 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)
49 TxAGND_0 **** Transmitter Analog Ground - Channel (n)
50 AGND_0 **** Analog Ground Pin - Channel (n)
51 RxDVDD_1 **** Receiver Digital Supply 3.3V + 5% Channel (n)
56 RxDGND_1 **** Receiver Digital Ground - Channel(n)
58 RxDVDD_0 **** Receiver Digital Supply 3.3V + 5% Channel (n)
62 RxDGND_0 **** Receiver Digital Ground - Channel(n)
63 AGND_1 **** Analog Ground Pin - Channel(n)
78 RxAVDD_0 **** Receiver Analog Supply 3.3V + 5% - Channel (n)
81 RxAGND_0 **** Receiver Analog Ground - Channel (n)
86 RxAVDD_1 **** Receiver Analog Supply 3.3V + 5% - Channel (n)
89 RxAGND_1 **** Receiver Analog Ground - Channel (n)
92 RxAGND_3 **** Receiver Analog Ground - Channel (n)
95 RxAVDD_3 **** Receiver Analog Supply 3.3V + 5% - Channel (n)
100 RxAGND_2 **** Receiver Analog Ground - Channel (n)
103 RxAVDD_2 **** Receiver Analog Supply 3.3V + 5% - Channel (n)
109 AGND_2 **** Analog Ground Pin - Channel (n)
112 AGND_3 **** Analog Ground Pin - Channel (n)
118 RxDGND_2 **** Receiver Digital Ground - Channel(n)
122 RxDVDD_2 **** Receiver Digital Supply 3.3V + 5% - Channel (n)

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
14
124 RxDGND_3 **** Receiver Digital Ground - Channel(n)
128 RxDVDD_3 **** Receiver Digital Supply 3.3V + 5% - Channel (n)
129 EXDGNDA **** External Clock Digital Ground
130 EXDVDDA **** External Clock Digital Supply
132 TxAGND_2 **** Transmitter Analog Ground - Channel (n)
134 TxAVDD_2 **** Transmitter Analog Supply 3.3V + 5% - Channel(n)
POWER AND GROUND PINS
PIN # NAME TYPE DESCRIPTION
NO CONNECTION PINS
PIN # NAME TYPE DESCRIPTION
37 NC No connection
38 NC No connection
39 NC No connection
142 NC No connection
143 NC No connection
144 NC No connection

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
15
ELECTRICAL CHARACTERISTICS
N OTE : The XRT73L04B is assembled in a thermally
enhanced package with an integral Copper Heat Slug. The
Heat Slug is solder plated and is exposed on the bottom of
the package and is electrically connected to the internal
Ground connections of the device. This Heat Slug can be
soldered to the mounting board if desired, but must be elec-
trically isolated from any V
DD
connections.
N
OTE : * Not applicable to pins with pull-up or pull-down
resistors.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature - 65°C to + 150°C
Operating Temperature - 40°C to + 85°C
Supply Voltage Range -0.5V to +3.465V
Theta-JA 24° C/W
Theta-JC 5.5° C/W
ELECTRICAL CHARACTERISTICS (TA= 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL PARAMETER MIN.TYP.MAX.UNITS
DC Electrical Characteristics
DVDD Digital DC Supply Voltage 3.135 3.3 3.465 V
AVDD Analog DC Supply Voltage 3.135 3.3 3.465 V
ICC Supply Current (Measured while Transmitting and Receiving all "1’s") 500 mA
VIL Input Low Voltage * 0.8 V
VIH Input High Voltage * 2.0 5.0 V
VOL Output Low Voltage, IOUT = -4.0mA * 0.4 V
VOH Output High Voltage, IOUT = 4.0mA * 2.8 V
ILInput Leakage Current * ±10 µA

XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
16
N OTES :
1. All XRT73L04B digital inputs are designed to be
TTL 5V compliant.
2. All XRT73L04B digital outputs are also TTL 5V
compliant. However, these outputs will not drive to
5V nor will they accept external 5V pull-ups.
ELECTRICAL CHARACTERISTICS (CONTINUED) (TA= 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
AC ELECTRICAL CHARACTERISTICS (SEE FIGURE 5)
TERMINAL SIDE TIMING PARAMETERS (SEE FIGURE 6 AND FIGURE 7) -- {(n) = 0, 1, 2 OR 3 }
SYMBOL PARAMETER MIN.TYP.MAX.UNITS
TxClk_(n) Clock Duty Cycle (STS-1/DS3) 30 50 70 %
TxClk_(n) Clock Duty Cycle (E3) 30 50 70 %
TxClk_(n) Frequency (SONET STS-1) 51.84 MHz
TxClk_(n) Frequency (DS3) 44.736 MHz
TxClk_(n) Frequency (E3) 34.368 MHz
tRTX TxClk_(n) Clock Rise Time (10% to 90%) 3 5 ns
tFTX TxClk_(n) Clock Fall Time (90% to 10%) 3 5 ns
tTSU TPData_(n)/TNData_(n) to TxClk_(n) Falling Set up time 3 1.5 ns
tTHO TPData_(n)/TNData_(n) to TxClk_(n) Falling Hold time 3 1.5 ns
tLCVO RxClk_(n) to rising edge of LCV_(n) output delay 2.5 ns
tTDY TTIP_(n)/TRing_(n) to TxClk_(n) Rising Propagation Delay time 8 ns
RxClk_(n) Clock Duty Cycle 50 %
RxClk_(n) Frequency (SONET STS-1) 51.84 MHz
RxClk_(n) Frequency (DS3) 44.736 MHz
RxClk_(n) Frequency (E3) 34.368 MHz
tCO RxClk_(n) to RPOS_(n)/RNEG_(n) Delay Time 0 2.5 ns
tRRX RxClk_(n) Clock Rise Time (10% to 90%) 1.5 ns
tFRX RxClk_(n) Clock Fall Time (10% to 90%) 1.5 ns
CIInput Capacitance 10 pF
CLLoad Capacitance 10 pF