EXOSTIV LABS EP Series User manual

https://www.exostivlabs.com 1
Interfacing EXOSTIV Probe EP Series
User Guide
Rev. 2.0.5 - February 10, 2023

Rev. 2.0.5 - February 10, 2023 2
Table of Contents
Interfacing EP Series ................................................................................................................................................................................3
Introduction.........................................................................................................................................................................................3
SFP/SFP+ Cages....................................................................................................................................................................................4
Other connectivity...............................................................................................................................................................................6
HDMI Connector (! Legacy !) ...............................................................................................................................................................7
References
[1] SFF committee, INF-8074i specification for SFP (Small Formfactor Pluggable) Transceiver (May 12, 2001)
Revision History
Revision
Modifications
1.0.26
•Original revision
1.0.47
•Notes added below Table 4
•HDMI I²C minimum reference level changed to +2.5V. Table updated accordingly
•Notes added below Table 1
•Different minimum VREF value for GPIO lines 0-3 (Error! Reference source not found.)
and 4-5 (+1.65V)
•Pin mapping correction for GPIO connector (Error! Reference source not found. and
Error! Reference source not found.)
•DC characteristics for GPIO lines split in Error! Reference source not found. and Error!
Reference source not found.
1.0.53
•Pin mapping for HDMI type-C added (Table 4)
1.0.115
•Extended document to cover all EP devices
2.0.0
•General review with EXOSTIV Dashboard for Intel release
2.0.1
•Corrected some typos
2.0.2
•Removed description of optical SFP cables.
2.0.3
•Update of legal and brand names.
•Removed obligation to use copper cables.
2.0.4
•Corrected information about optical cables.
•Removed reference to EP3000 probes.
2.0.5
•Updated the status of the ‘HDMI’connector to not recommended for new designs –
legacy.

Rev. 2.0.5 - February 10, 2023 3
Interfacing EP Series
Introduction
EXOSTIV Probe (‘EP Series’) device requires a bi-directional link to connect to the target system. This bi-directional
link is composed of:
•a potentially lower data rate downstream link from the EP device to the target system. It is used to
configure and control the IP embedded in the FPGA.
•a high speed upstream link from the target FPGA to the EP device to collect the captured data.
The EP series devices use transceivers (or ‘multi-gigabit transceivers’, or ‘MGT’or SERDES) to implement the
upstream link.
In the current revision of the EP Probe devices, 2 connection options are available on the probe’s front panel:
-Option 1: 4 SFP/SFP+ cages able to receive passive SFP copper cables or SFP/SFP+ optical transceiver modules
-Option 2: A HDMI form factor connector type-A with up to 4 simplex multi-gigabit links.
Important : it is not recommended to use Option 2 above for new designs. Option 2 above (HDMI form factor
connector with a custom pinout) is described in this document for legacy support purposes. Future versions of the
EP series probe will see this type of connectivity phased out.
The low data rate downstream link is implemented using either MGT or a low speed serial link similar to I²C.
The purpose of this document is to provide the necessary information to correctly connect the EP series devices to
the user's target system. Pin assignments, mechanical and electrical specifications of the connectors are provided
to help designers implement interfaces compatible with Exostiv Labs devices.
The following models of EXOSTIV Probes EP series are available:
EXOSTIV Probes
EP6000
EP12000
Max. speed per channel
6.6 Gbps
12.5 Gbps
Number of channels (Transceivers)
1,2 or 4
Supported devices
Xilinx FPGA : please click here.
Intel FPGA : please click here.
EXOSTIV Probe user’s guide can be found on Exostiv Labs’ general documentation page.
Notes : 1. Please contact us for other devices and manufacturers support, availability and roadmaps.
2. FPGA devices that will be supported in the future with the EP6000 and EP12000 probes will use the pinout
described in this document.
3. Other probe number encoding such as EP6000-X, EP12000-X, EP6000-I or EP12000-I with ‘X’ or ‘I’ suffix are
now covered by the generic numberings, ‘EP6000’ and ‘EP12000’.
4. EP6000 is a legacy product that is now discontinued.

Rev. 2.0.5 - February 10, 2023 4
SFP/SFP+ Cages
EP series can be connected to up to 4 simplex or full-duplex multi-gigabit links through SFP/SPF+ physical interface.
The SFP/SFP+ cages can receive passive cables or optical cables. The connector pin assignment is compatible with
the standard proposed by the MSA group [1].
Using the SFP/SFP+ interface enables the implementation of a full-duplex link. Upstream data flow (TX) refers to
data transmitted from the target system to the EP device. Downstream data flow (RX) refers to data received by
the target system from the EP device.
A downstream link is mandatory to let the EP device control the IP embedded in the FPGA. A single downstream link
is required, even if multiple SFP/SFP+ links are used for the upstream link.
This downstream link does not need to be implemented using a multi-gigabit link since only a very low data rate is
required in this direction.
When the downstream link does not use the multi-gigabit transceiver, it must be implemented with a I²C bus. Two
user IO pins of the FPGA must be reserved to connect the SCL and SDA lines of the I²C interface. Refer to ‘HDMI
Connector’ section for more details on how to implement the I²C interface.
Figure 1: SFP+ receptacle pin mapping

Rev. 2.0.5 - February 10, 2023 5
Table 1: SFP/SFP+ connector pin assignment
Pin #
Signal
Description
Usage
1
VeeT
Transmitter ground
Mandatory
2
TX Fault
Transmitter fault indication. Open collector/drain output. 4.7K to
10K pull-up required.
Optional
3
TX Disable
Active high transmitter disable.
Optional
4
MOD-DEF2
SDA line for I²C interface. Pull-up resistor required.
Optional
5
MOD_DEF1
SCL line for I²C interface. Pull-up resistor required.
Optional
6
MOD-DEF0
Active low module presence detection. Pull-up resistor required.
Optional
7
RS0
Receiver rate select.
Optional
8
LOS
Loss of receiver signal. Open collector/drain output. 4.7K to 10K
pull-up required.
Optional
9
RS1
Transmitter rate select.
Optional
10
VeeR
Receiver ground
Mandatory
11
VeeR
Receiver ground
Mandatory
12
RD-
Inverted received data out. Connect to MGTPRXN, MGTXRXN or
MGTHRXN pin of the FPGA.
Optional1
13
RD+
Received data out. Connect to MGTPRXP, MGTXRXP or MGTHRXP
pin of the FPGA.
Optional1
14
VeeR
Receiver ground.
Mandatory
15
VccR
Receiver power.
Optional2
16
VccT
Transmitter power.
Mandatory3
17
VeeT
Transmitter ground.
Mandatory
18
TD+
Transmit data in. Connect to MGTPTXP, MGTXTXP or MGTHTXP pin
of the FPGA.
Mandatory
19
TD-
Inverted transmit data in. Connect to MGTPTXN, MGTXTXN or
MGTHTXN pin of the FPGA.
Mandatory
20
VeeT
Transmitter ground
Mandatory
1 Optional if downstream link is implemented using I²C bus
2 Not required if RD+/RD- are not used. Optional if only passive cables are used for RD+/RD-
3 Optional if only passive cables are used for TD+/TD-
4 Transceiver + and –signals can be swapped within a differential pair if it is required to improve the layout. The
EP can dynamically invert the polarity of the received signals.
When passive cables are used, it is not mandatory to provide power on these pins and they can be connected to
GND. Please note that the internal identification EEPROM cannot be accessed if no power is provided to the SFP
cable. In this case, the cable will operate correctly but the diagnostic features won't be available.
TD+/TD- are mandatory and are used for the upstream link to the EP device. This differential pair must be
connected to the dedicated transmitter pins of the FPGA (MGTPTX, MGTXTX or MGTHTX). It is recommended to
place AC coupling capacitors on the target system as close as possible to the FPGA pins.
RD+/RD- are not mandatory. They can be used for the downstream link from the EP device.
If multiple SFP/SFP+ links are used, a single downstream link is required. If no SFP/SFP+ link is used for downstream
link, an I²C bus interface must be foreseen. Refer to “HDMI Connector” section for more details. The RD+/RD-
differential pair must be connected to the dedicated receiver pins of the FPGA (MGTPRX, MGTXRX or MGTHRX). AC
coupling capacitors are placed in the EP devices for the downstream links and hence no AC coupling capacitor is
required for the receiver lines on the target system.
The control and status signals of the SPF/SFP+ connector are not mandatory. Connecting these pins to an FPGA
bank compatible with +3.3V IO signalling allows using the diagnostic features of the IP embedded in the target
FPGA. These pins are not required for the IP operation. Table 2 describes how to connect these pins if the

Rev. 2.0.5 - February 10, 2023 6
diagnostic feature is not used. The IP diagnostic feature gives the possibility to automatically detect the module or
cable presence, to read the module or the cable identification, and so on.
If multiple SFP/SFP+ links are used, it is possible to spare FPGA pins by connecting the corresponding control and
status lines of modules together.
Note: The I²C bus of multiple SFP/SFP+ links cannot be connected together to form a single bus. All modules have
the same I²C slave address. Placing several modules on the same bus will create conflicts. One I²C (SDA/SCL)
pair must be used per SFP/SFP+ links. An I²C bus switch component can be added on board to reduce the
number of used FPGA user IO.
Table 2: Handling unused SFP/SFP+ control and status signals.
Pin #
Signal
Description
2
TX Fault
Keep unconnected when not used.
3
TX Disable
Must be connected to GND to enable the module by default.
4
MOD-DEF2
Pull-up to +3.3V.
5
MOD_DEF1
Pull-up to +3.3V.
6
MOD-DEF0
Keep unconnected when not used
7
RS0
This pin has no effect for passive cables. Pull-up resistor of
maximum 10K is recommended (check optical module
manufacturer documents for more details).
8
LOS
Keep unconnected if not used.
9
RS1
This pin has no effect for passive cables. Pull-up resistor of
maximum 10K is recommended (check optical module
manufacturer documents for more details).
Other connectivity
Should SFP/SFP+ or QSFP/QSFP+ not be suitable for your needs, please contact Exostiv Labs to select a more suitable
or compact connectivity. Exostiv Labs constantly works at selecting the best connectors and our technical team is
able to select the best available solution for your needs, with a readily available connector adapter or advanced
cable assemblies.

Rev. 2.0.5 - February 10, 2023 7
HDMI Connector (! Legacy !)
Important : it is not recommended to use this option as custom connector for new designs.
The description that follows is provided for legacy support purposes. Future versions of the
EP series probe will see this type of connectivity phased out.
The HDMI port is implemented using a 19-pin type-A HDMI compatible connector. Industry standard HDMI cables
can be used to connect the EP devices to the user's target system. Table 3 provides some examples of compatible
connectors that can be placed onto the target system board.
Even if the EP devices use a type-A HDMI connector, the target system can be equipped with space saving type-C
(mini-HDMI) or type-D HDMI (micro-HDMI) connectors. In this case, a connector adapter or a cable with a different
connector on each end must be used to connect the EP device to the target system. Using type-B induces the
presence of via on the transceiver lines. With type-A connector, straight routing without via is possible.
Table 3: Examples of compatible HDMI connectors
Manufacturer
Part Number
Connector Type
Molex
047151-1001
Type-A
FCI
10029449-001RLF
Type-A
TE Connectivity
1747981-1
Type-A
CNC Tech
2000-1-2-30-00-BK
Type-A
Molex
046765-0001
Type-D
CNC Tech
2002-1-2-40-30-BK
Type-D
This list is not exhaustive.
Table 4 provides the pin assignments for type-A, type-C and type-D HDMI connectors. The HDMI interface uses up
to 4 simplex multi-gigabit links from the target system to the EP device (upstream data flow direction). The
differential GTX data lines must be connected to the dedicated transmitter pins of the FPGA (MGTPTX, MGTXTX or
MGTHTX). It is recommended to place AC coupling capacitors on the target system as close as possible to the FPGA
pins.

Rev. 2.0.5 - February 10, 2023 8
Table 4: HDMI Type-A and Type-D connector pin assignments
Type-A(1)
Type-C(4)
Type-D(2)
Signal
Description
1
2
3
T2Y_Data3+
Positive data line of the 4th GTX1differential pair from
target system to EP device. Connect to MGTPTXP,
MGTXTXP or MGTHTXP pin of the FPGA.
2
1
4
D3_Shield
Shield for 4th GTX differential pair
3
3
5
T2Y_Data3-
Negative data line of the 4th GTX differential pair from
target system to EP device. Connect to MGTPTXN,
MGTXTXN or MGTHTXN pin of the FPGA.
4
5
6
T2Y_Data2+
Positive data line of the 3rd GTX differential pair from target
system to EP device. Connect to MGTPTXP, MGTXTXP or
MGTHTXP pin of the FPGA.
5
4
7
D2_Shield
Shield for 3rd GTX differential pair
6
6
8
T2Y_Data2-
Negative data line of the 3rd GTX differential pair from
target system to EP device. Connect to MGTPTXN,
MGTXTXN or MGTHTXN pin of the FPGA.
7
8
9
T2Y_Data1+
Positive data line of the 2nd GTX differential pair from target
system to EP device. Connect to MGTPTXP, MGTXTXP or
MGTHTXP pin of the FPGA.
8
7
10
D1_Shield
Shield for 2nd GTX differential pair
9
9
11
T2Y_Data1-
Negative data line of the 2nd GTX differential pair from
target system to EP device. Connect to MGTPTXN,
MGTXTXN or MGTHTXN pin of the FPGA.
10
11
12
T2Y_Data0+
Positive data line of the 1st GTX differential pair from target
system to EP device. Connect to MGTPTXP, MGTXTXP or
MGTHTXP pin of the FPGA.
11
10
13
D0_Shield
Shield for 1st GTX differential pair
12
12
14
T2Y_Data0-
Negative data line of the 1st GTX differential pair from
target system to EP device. Connect to MGTPTXN,
MGTXTXN or MGTHTXN pin of the FPGA.
13
13
15
DNC
Do not connect. Keep this pin floating.
14
14
2
DNC
Do not connect. Keep this pin floating.
15
15
17
Y2T_SCL
I²C serial clock from EP to target system. EP device is the
I²C bus master. Add 2KΩ pull-up resistor on target system.
Connect this pin to an FPGA user IO.
16
16
18
Y2T_SDA
I²C serial bi-directional data line. Add 2KΩ pull-up resistor
on target system. Connect this pin to an FPGA user IO.
17
17
16
GND
Reference signal ground
18
18
19
DNC
Do not connect. Keep this pin floating.
19
19
1
Presence Detect
Target presence detection. Connect this pin to signal
ground.
1Tested with 10 m cable up to 6.6 Gbps per link and with 2 m cable up to 10.0 Gbps.
2 Tested with 2 m cable up to 10.0 Gbps per link. Higher bit rates tests underway Please contact us for details.
3 Transceiver + and –signals can be swapped within a differential pair if it is required to improve the layout. The
EP can dynamically invert the polarity of the received signals.
4Not tested yet –provided ‘as is’.
When using the HDMI connector, the downstream communication (from the EP device to the target system) is
implemented with the dedicated I²C serial bus of the HDMI connector. This link is used to control the IP that is
embedded in the FPGA fabric. The EP device operates as the bus master and the target system as the slave. SCL
and SDA lines must be connected to user IO pins of the FPGA; in addition, external pull-up resistors connecting SCL
and SDA to a voltage reference from +2.5V to +3.3V must be added. If this voltage level range is not compatible
1
GTX = ‘Gigabit transceiver’ or ‘transceiver’. The abbreviation can change according to the FPGA vendor and FPGA family. In this document ‘GTX’ is
used as a generic term.

Rev. 2.0.5 - February 10, 2023 9
with the selected FPGA bank, an I²C bus level converter must be inserted between the HDMI connector and the
FPGA.
Table 5: I²C bus specifications through HDMI connector
Parameter
Min
Typ
Max
Unit
Voltage reference
VREF
2.5V
-
3.3V
V
SCL/SDA pull-up resistor
-
-
2
-
kΩ
SCL/SDA voltage level (input to EP)
Low-level
VIL
-0.5
-
0.85
V
High-level
VIH
2.31
-
6
V
Low-level output current
IOL
3
9
-
mA
Note: Even if an industry standard HDMI connector is used on EP series, do not connect any HDMI-compatible
device. The multi-gigabit transceiver port is not pin and functionality-compatible with the HDMI video
standard.

Rev. 2.0.5 - February 10, 2023 10
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