Fraser Innovation FII-PRA006 Operating and maintenance manual

V1.2
FRASER INNOVATION INC
FII-PRA006/010 Hardware Reference Guide

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Version Control
Version
Date
Description
V1.0
06/25/2019
Initial Release
V1.1
07/15/2019
Add Description About PCF8591
V1.2
07/19/2019
Add Description About Oscillator and IIC

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Copyright Notice:
© 2019 Fraser Innovation Inc ALL RIGHTS RESERVED
Without written permission of Fraser Innovation Inc, no unit or individual may
extract or modify part of or all the contents of this manual. Offenders will be held
liable for their legal responsibility.
Thank you for purchasing the FPGA development board. Please read the manual
carefully before using the product and make sure that you know how to use the
product correctly. Improper operation may damage the development board. This
manual is constantly updated, and it is recommended that you download the
latest version when using.
Official Shopping Website:
https://fpgamarketing.com/FII-PRA040-Altera-risc-v-Cyclone10-FPGA-Boards-FII-
PRA040.htm

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Contents
1. Introduction..................................................................................................................................... 5
2. Basic Features................................................................................................................................. 9
1）FPGA................................................................................................................................................. 9
2）USB Interface................................................................................................................................ 9
3）Oscillator ......................................................................................................................................12
4) Segment LED Display...........................................................................................................13
5）VGA Interface............................................................................................................................. 16
6）EEPROM AT24C02................................................................................................................... 20
7）Gigabit Ethernet Interface...................................................................................................22
8）Push Button ................................................................................................................................25
9）AD/DA Thermistor, Photoresistor and Potentiometer........................................26
10）DIP Switch.................................................................................................................................28
11）LED................................................................................................................................................ 30
12）FLASH Configuration Chip...............................................................................................32
13）GPIO Expansion Bus ............................................................................................................32
14）JTAG Interface.........................................................................................................................35
3. References .........................................................................................................................37

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Fraser Innovation Inc develops FII-PRA006/010 based on Intel Cyclone10
development board. It was initial released in 2019. The model is PRA006/010.
Although it is designed for FPGA beginners, this development board has been
spent a lot on the schematics design, PCB design, and function creation. It can be
described as “simple but powerful”.
PRA006/010 Full View Picture

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1. Introduction
This development board uses Intel's Cyclone10 series chip, model
10CL006YE144C8G or 10CL010YE144C8G.
The Cyclone10 series is Intel's latest generation of FPGAs for the data torrent
of the future and the rapidly growing IoT application market. This series provides
fast, power-saving processing and is suitable for automotive, industrial
automation, professional audio and visual systems and a variety of applications.
Compared to previous generations of Cyclone FPGAs, the 10 Series saves more
power while delivering twice the performance.
PRA006/010 system block diagram：
FPGA
Cyclone10
VGA
Gigabit
Ethernet
JTAG
6 Digit 7-segment Decoders
4 Push Buttons
Reset
Potentiometer
Photoresistor
FLASH
128Mbit
8 DIP Switches
8 LEDs
EEPROM
AT24C02
50M Oscillator
Thermistor
GPIO
Interface
USB to
Serial Chip
AD/DA
(Back)
USB Power
Supply and
Download
Interface
GPIO
Interface
External I2C Interface
External A/D
Interface
Figure 1.1 PRA006/100 System Block Diagram
Ethernet
Chip
RTL8211E

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Chip resource：
Figure 1.2 Chip Resource
Other parameters：
Working temperature：0~85℃
Core voltage：1.15~1.25V（Recommended voltage 1.2V）
Hardware resources:
•The USB interface provides power interface, program download, and can
be used as a USB to serial port. Achieved the function of one wire to
complete the power supply, download functions, and serial
communication;
•A 50 MHz oscillator, a 32.768 kHz oscillator, provides a stable clock source
for the development board;
•6-digit common anode 7-segment LED display, through dynamic scanning
10CL006 10CL010
6,272 10,320
Block 30 46
Capacity(Kb) 270 414
15 23
2 2
20 20
176 176
65 65
Clock
Maximum I/O
Maximum LVDS
Resource
Logic Elements (LE)
M9K
Memory
18 x 18 Multiplier
PLL

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to achieve data display;
•1-channel VGA interface to display colorful pictures or camera video;
•1 EEPROM chip with I2C interface, model AT24C02;
•1 adaptive 10M/100M/Gigabit Ethernet interface;
•5 push buttons, 4 for programmable buttons, 1 for reset button;
•1 photoresistor, through which it can simulate light control; 1 thermistor,
which can collect temperature or analog temperature alarm function; 1
potentiometer, which can simulate voltage change etc;
•1 PCF8591 AD/DA conversion chip;
•On-board 50MHz oscillator, through which provides a stable clock signal to
the development board;
•8-digit DIP switch;
•8-bit LED;
•1-piece 128Mbit Flash chip;
•2 GPIO external signal expansion interfaces;
•One JTAG interface, which makes PRA006/010 a full-featured JTAG adapter,
which can download programs for FPGAs from Intel, Xilinx and other
vendors;

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Before using the development board, it is necessary to check whether the
power supply and jtag mode jumpers are correct. J9 is the selection jumper for
either internal or external program download (when this development board is
used as the downloader). For the internal download program, connect "INT".
When using it as a downloader, connect "EXT". J6 is used to select FPGA BANK
power supply, generally 3.3V and 5V . And J8 will be used to select bank IO
voltage. Its jumper description is silk screen printed on the development board, as
shown below.
Figure 1.3 Power Selection Jumper

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2. Basic Features
1）FPGA
As mentioned above, this development board FPGA model is
10CL006YE144C8G (PRA010 uses 10CL010YE144C8G), which is Intel's latest
generation of low-power high-performance FPGA.
Figure 2.1 FPGA Physical Picture
2）USB Interface
It is a micro USB interface onboard that integrates power supply, program
download and serial communication functions.
Figure 2.2 USB Interface Physical Picture
By the way to mention the power supply circuit of the development board and

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the power supply of the FPGA. When the USB cable (sold with the board as a set)
is connected to the development board and the computer's USB port, the
development board will work through the 5V power supply provided by the
computer's USB interface, but instead of directly using the 5V level, the 5V voltage
will be converted by the conversion chip to the required voltages such as 1.2V,
2.5V, 3.3V. See Figure 2.3 for the schematics of the USB interface and power
conversion chip.
Figure 2.3 Schematics of Micro USB
The external input power PC_USB5V is connected to the 5V level network of
the development board, and then converted from the 5V level network to 1.2V
(FPGA core voltage) required by the FPGA, 2.5V or 3.3V. Both 2.5V and 3.3V are
FPGA BANK voltages. The two voltages are provided to accommodate various
external signal level standards. The conversion circuit is shown below.

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Figure 2.4 Schematics of 3.3V Power Supply
Figure 2.5 Schematics of 2.5V Power Supply
Figure 2.6 Schematics of 1.2V Power Supply
If we look at the power supply of the FPGA, we can see these kinds of voltages:

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Figure 2.7 Pins of FPGA Power Supply
In Figure 2.7, VCCD_PLL1_37, VCCD_PLL2_109 are the power supply pins of the
FPGA phase-locked loop(PLL), and the following numbers 37, 109 are their pin
numbers on the FPGA. VCCINT is the core voltage of the FPGA (the other power
supply parts of the FPGA are not listed, please refer to the attached schematics for
details).
As a communication serial port, its D_N and D_P pins are connected to the
FT2232HL chip (this is a chip specially used as a USB to UART), which is processed
by the FT2232HL and then connected to the FPGA and JTAG ports.
Signal Name
FPGA Pin
JTAG_RXD
143
JTAG_TXD
144
3）Oscillator

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One on-board oscillators for 50MHz. The clock input is connected to the pin
91 of the FPGA. The schematic is as follows:
Figure 3.1 Schematics of Oscillators
Figure 3.2 Oscillators Physical Picture
Pin Assignment
Signal Name
FPGA Pin
CLK_50M
91
4) Segment LED Display
Figure 4.1 Segment Display

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One type of digital tube is a semiconductor light-emitting device. The
segment decoder can be divided into a seven-segment decoder and an eight-
segment decoder. The difference is that the eight-segment decoder has one more
unit for displaying the decimal point, the basic unit is a light-emitting diode. The
segment structure of the decoder is shown below:
Figure 4.2 Segment Decoder Structure
Common anode decoders are used here. That is, the anodes of the LEDs are
connected.
Figure 4.3 Schematics of Common Anode LED
To illuminate a segment of an 8-segment decoder, the level of the
corresponding pin needs to be pulled low; when the pin is set high, the
corresponding field will not light. This development board uses a 6-in-one eight-
segment decoder. The schematics is shown below:

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Figure 4.4 Schematic of Segment Decoders
The six-in-one decoder is a dynamic display. Due to the persistence of human
vision and the afterglow effect of the LED, although the decoders are not lit at the
same time, if the scanning speed is fast enough, the impression of human eyes is a
group of stable display data, no flickering can be noticed. The same segments of
the six-in-one decoders are connected, a total of eight pins, and with six control
signal pins, a total of 14 pins, as shown in Figure 4.4. Among them SEG_PA,
SEG_PB, SEG_PC, SEG_PD, SEG_PE, SEG_PF, SEG_PG, SEG_DP correspond to the A,
B, C, D, E, F, G, DP of decoder; SEG_3V3_D [0..5] are six control pins of the
decoders, which are also active low. When the control pin is low, the
corresponding decoder is powered, so that the LED can be lit.
Pin assignments of display decoders

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Signal Name
FPGA Pin
Description
SEG PA
132
Segment A
SEG PB
137
Segment B
SEG PC
133
Segment C
SEG PD
125
Segment D
SEG PE
126
Segment E
SEG PF
138
Segment F
SEG PG
135
Segment G
SEG DP
128
Segment DP
SEG_3V3_D0
136
Decoder 1(from right)
SEG_3V3_D1
142
Decoder 2(from right)
SEG_3V3_D2
141
Decoder 3(from right)
SEG_3V3_D3
129
Decoder 4(from right)
SEG_3V3_D4
127
Decoder 5(from right)
SEG_3V3_D5
124
Decoder 6(from right)
5）VGA Interface
The VGA (Video Graphics Array) interface is a common interface for computer
monitors. It has been used since the earliest CRT monitors and has been in use ever
since. The VGA connector is a D-type connector with a total of 15 pinholes divided
into 3 rows of 5 per row. More important are three RGB color component signal
pins and two scan sync signals (HSYNC and VSYNC) pins.
Pins 1, 2, and 3 are the red, green, and blue primary color analog voltages,

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which are 0~0.714V peak-peak, 0V is colorless, and 0.714V is full color. Some non-
standard displays use a full color level of 1Vpp.
Figure 5.1 Schematics of VGA
The three primary color source and terminal matching resistors are both 75
ohms. See Figure 5.1.
Figure 5.2 VGA Signal Transmission Diagram
HSYNC and VSYNC are line data synchronization and frame data
synchronization, respectively, which are TTL levels. The FPGA can only output
digital signals, and the R, G, and B required by VGA are analog signals, so we need
to perform analog-to-digital conversion or DAC function. To implement a video
DAC, we can use a dedicated chip or a weight resistor network. Here we use the
latter as a DAC.
Source
Terminal

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The development board selects the 4:4:4 mode, that is, 4 bits for red, 4 bits for
green, and 4 bits for blue. The following takes red 4 bits to illustrate the selection
of the resistor.
Since the DAC is a linear model, when the red 4 bits output is high, we need
to get a voltage of 0.714V. The topology is shown in Figure 5.3.
Figure 5.3 Schematics of the Weight Resistance Mode Topology
The output voltage of the FPGA is 3.3V, and Rx is a parallel connection of 4 bits
resistor networks, so the following equation can be obtained:
（Rx + 75）/ 3.3 = 75 / 0.714
Let the reference resistance be Ra, then:
Ra // 2Ra // 4Ra // 8Ra = Rx
According to the above two equations, the solution is obtained, Rx = 271.6, and
Ra = 509.2. 500, 1k, 2k, 4k are selected for the network resistor. As shown below：
0.714V Voltage Output

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Figure 5.4 VGA Weight Resistance Network
Figure 5.5 VGA Interface Physical Picture
VGA Pin Assignment
Signal Name
FPGA Pin
Description
VGA HS
98
Horizontal Synchronous
Signal
VGA VS
99
Vertical Synchronous Signal
VGA R0
100
Red[0]
VGA R1
101
Red[1]