Freescale Semiconductor 56F8300 Series User manual

56F8300
16-bit Hybrid Controllers
freescale.com
56F8357
Evaluation Module User Manual
MC56F357EVMUM
Rev. 1
08/2004

TABLE OF CONTENTS
TOC
Freescale Semiconductor i
Preliminary
Preface vii
Chapter 1
Introduction
1.1 56F8357EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 56F8357EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 56F8357EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Technical Summary
2.1 56F8357. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 Program and Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.2 SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.4 Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.5 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.5.1 EXTBOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.5.2 EMI_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.5.3 CLKMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.6 Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.7 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.7.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.7.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.8 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.11 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.11.1 Peripheral Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.11.2 Memory Daughter Card Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.12 Motor Control PWM Signals and LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.13 CAN Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.14 Software Feature Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

56F8357EVM User Manual, Rev. 1
ii Freescale Semiconductor
Preliminary
2.15 Peripheral Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.15.1 Address Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.15.2 Data Bus Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.15.3 External Memory Control Signal Expansion Connector. . . . . . . . . . . . . . . . . . . . . 2-26
2.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector. . . . . . . . . . . . . . . . . . 2-26
2.15.5 Encoder #1 / SPI #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.15.6 Timer Channel C Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.15.7 Timer Channel D Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.15.8 A/D Port A Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.15.9 A/D Port B Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.15.10 Serial Communications Port #0 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-30
2.15.11 Serial Communications Port #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-30
2.15.12 Serial Peripheral Interface #0 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.15.13 FlexCAN Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.15.14 PWM Port A Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.15.15 PWM Port B Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.16 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Appendix A
56F8357EVM Schematics
Appendix B
56F8357EVM Bill of Material

LIST OF FIGURES
LOF
Freescale Semiconductor iii
Preliminary
1-1 Block Diagram of the 56F8357EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 56F8357EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 Connecting the 56F8357EVM Cables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1 Schematic Diagram of the External CS0 Memory Interface. . . . . . . . . . . . . . . . . . . 2-4
2-2 Schematic Diagram of the External CS1/CS4 Memory Interface. . . . . . . . . . . . . . . 2-5
2-3 Schematic Diagram of the RS-232 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-4 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-5 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-6 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-7 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-8 Schematic Diagram of the RESET Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-9 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-10 PWM Group A Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2-11 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2-12 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2-13 Typical Analog Input RC Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

56F8357EVM User Manual, Rev. 1
iv Freescale Semiconductor
Preliminary

LIST OF TABLES
Freescale Semiconductor v
Preliminary
1-1 56F8357EVM Default Jumper Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1 SCI0 Jumper Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-2 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-3 EXTBOOT Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-4 EMI Operating Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5 EMI Operating Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-6 LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-7 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-8 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-11
2-9 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-10 Parallel JTAG Interface Voltage Jumper Selection. . . . . . . . . . . . . . . . . . . . . . 2-13
2-11 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-12 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2-13 CAN Header Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2-14 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-24
2-15 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-25
2-16 External Memory Control Signal Connector Description . . . . . . . . . . . . . . . . . 2-26
2-17 Timer A Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2-18 SPI #1 Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2-19 Timer Channel C Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2-20 Timer Channel D Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2-21 A/D Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2-22 A/D Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2-23 SCI #0 Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2-24 SCI #1 Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2-25 SPI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

56F8357EVM User Manual, Rev. 1
vi Freescale Semiconductor
Preliminary
2-26 CAN Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2-27 PWM Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2-28 PWM Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

Preface
Freescale Semiconductor vii
Preliminary
Preface
This reference manual describes in detail the hardware on the 56F8357 Evaluation
Module.
Audience
This document is intended for application developers who are creating software for
devices using the Freescale 56F8357 part or a member of the 56F8300 family that is
compatible with this part. Examples would include the 56F8347 and the 56F8356.
Organization
This manual is organized into two chapters and two appendixes.
•Chapter 1,Introduction provides an overview of the EVM and its features.
•Chapter 2,Technical Summary describes in detail the 56F8357 hardware.
•Appendix A,"56F8357EVM Schematics"contains the schematics of the
56F8357EVM.
•Appendix B,"56F8357EVM Bill of Material" provides a list of the materials used on the
56F8357EVM board.
Suggested Reading
More documentation on the 56F8357 and the 56F8357EVM kit may be found at URL:
freescale.com

56F8357EVM User Manual, Rev. 1
viii Freescale Semiconductor
Preliminary
Notation Conventions
This manual uses the following notational conventions:
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined
below for reference.
Term or Value Symbol Examples Exceptions
Active High
Signals
(Logic One)
No special symbol
attached to the
signal name
A0
CLKO
Active Low
Signals
(Logic Zero)
Noted with an
overbar in text and
in most figures
WE
OE In schematic drawings,
Active Low Signals may be
noted by a backslash: /WE
Hexadecimal
Values Begin with a “$” symbol $0FF0 $80
Decimal Values No special symbol
attached to the
number
10
34
Binary Values Begin with the letter
“b” attached to the
number
b1010
b0011
Numbers Considered positive
unless specifically
noted as a negative
value
5
-10 Voltage is often shown as positive: +3.3V
Blue Text Linkable on-line ...refer to Chapter 7, License
Bold Reference sources,
paths, emphasis ...see:
http://www.freescale.com/
A/D Analog-to-Digital; a method of converting Analog signals to Digital
values
ADC Analog-to-Digital Converter; a peripheral on the 56F8357 part
CAN Controller Area Network; serial communications peripheral and method
CiA CAN in Automation; an international CAN user’s group that coordinates
standards for CAN communications protocols
D/A Digital-to-Analog; a method of converting Digital values to an Analog
form
DSP Digital Signal Processor or Digital Signal Processing

Preface
Freescale Semiconductor ix
Preliminary
56F8357 Hybrid controller with motor control peripherals
EOnCE Enhanced On-Chip Emulation; a debug bus and port was created to
enable a designer to create a low-cost hardware interface for a
professional-quality debug environment
EVM Evaluation Module; a hardware platform which allows a customer to
evaluate the silicon and develop his application
FlexCAN Flexable CAN Interface Module; a peripheral on the 56F8357 part
GPIO General Purpose Input and Output port on Freescale’s family of hybrid
controllers; does not share pin functionality with any other peripheral on
the chip and can only be set as an input, output or level-sensitive
interrupt input
IC Integrated Circuit
JTAG Joint Test Action Group; a bus protocol/interface used for test and debug
LED Light Emitting Diode
LQFP Low-profile Quad Flat Package
MPIO Multi-Purpose Input and Output port on Freescale’s family of hybrid
controllers; shares package pins with other peripherals on the chip and
can function as a GPIO
OnCETM On-Chip Emulation, a debug bus and port created to allow a means for
low-cost hardware to provide a professional-quality debug environment
PCB Printed Circuit Board
PLL Phase Locked Loop
PWM Pulse Width Modulation
QuadDec Quadrature Decoder; a peripheral on the 56F8357 part
RAM Random Access Memory
R/C Resistor/Capacitor Network
ROM Read-Only Memory
SCI Serial Communications Interface; a peripherial on Freescale’s family of
hybrid controllers
SPI Serial Peripheral Interface; a peripheral on Freescale’s family of hybrid
controllers
SRAM Static Random Access Memory
UART Universal Asynchronous Receiver/Transmitter
WS Wait State

56F8357EVM User Manual, Rev. 1
xFreescale Semiconductor
Preliminary
References
The following sources were referenced to produce this manual:
[1] DSP56800E Reference Manual, DSP56800ERM, Freescale Semiconductor
[2] 56F8300 Peripheral User Manual, MC56F8300UM, Freescale Semiconductor
[3] 56F8357 Technical Data, MC56F8357, Freescale Semiconductor
[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,
Version 1.0, CAN in Automation
[5] CAN Specification 2.0B, BOSCH or CAN in Automation

Introduction, Rev. 1
Freescale Semiconductor 1-1
Preliminary
Chapter 1
Introduction
The 56F8357EVM is used to demonstrate the abilities of the 56F8357 hybrid controller and to
provide a hardware tool allowing the development of applications.
The 56F8357EVM is an evaluation module board that includes a 56F8357 part, peripheral
expansion connectors, a CAN interface, 512KB of external memory and a pair of daughter card
connectors. The daughter card connectors are for signal monitoring and user feature
expandability.
The 56F8357EVM is designed for the following purposes:
• Allowing new users to become familiar with the features of the 56800E architecture. The
tools and examples provided with the 56F8357EVM facilitate evaluation of the feature set
and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run
it, and debug it using a debugger via the JTAG/Enhanced OnCE (EOnCE) port. The
breakpoint features of the EOnCE port enable the user to easily specify complex break
conditions and to execute user-developed software at full speed until the break conditions
are satisfied. The ability to examine and modify all user-accessible registers, memory and
peripherals through the EOnCE port greatly facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the Processor's peripherals.
The EOnCE port's unobtrusive design means that all memory on the board and on the
Processor is available to the user.

56F8357EVM User Manual, Rev. 1
1-2 FreescaleSemiconductor
Preliminary
1.1 56F8357EVM Architecture
The 56F8357EVM facilitates the evaluation of various features present in the 56F8357 part. The
56F8357EVM can be used to develop real-time software and hardware products. The
56F8357EVM provides the features necessary for a user to write and debug software,
demonstrate the functionality of that software and interface with the user's application-specific
device(s). The 56F8357EVM is flexible enough to allow a user to fully exploit the 56F8357's
features to optimize the performance of his product, as shown in Figure 1-1.
Figure 1-1. Block Diagram of the 56F8357EVM
1.2 56F8357EVM Configuration Jumpers
Ninteen jumper groups, (JG1-JG19), shown in Figure 1-2, are used to configure various features
on the 56F8357EVM board. Table 1-1 describes the default jumper group settings.
56F8357
RESET
MODE/IRQ
Address,
Data &
Control
JTAG/EOnCE
XTAL/
EXTAL
SPI #0
SCI #0
Timer C
PWMA
+3.3V & GND
+3.3VA & AGND
+3.0VREF
Peripheral
Expansion
Connectors
Mode/IRQ Logic
Program Memory
128Kx16-bit
SRAM
Memory
Expansion
Connector
JTAG
Connector
Parallel
JTAG
Interface
8.00MHz
Crystal
DSub
25-Pin
Data Memory
128Kx16-bit
SRAM DSub
9-Pin
PWM LEDs
RS-232
Interface
Power Supply
+3.3V, +3.3VA, +5V &
+3.0VA
SCI #1
Reset Logic
Memory
Daughter Card
Connector
CAN Interface
Debug LEDs
CAN Bus
Header
CAN Bus
DaisyChain
Peripheral
Daughter Card
Connector
Timer D
ADCA
QuadDec #0
PWMB
ADCB
QuadDec #1
FlexCAN

56F8357EVM Configuration Jumpers
Introduction, Rev. 1
Freescale Semiconductor 1-3
Preliminary
Figure 1-2. 56F8357EVM Jumper Reference
Table 1-1. 56F8357EVM Default Jumper Options
Jumper
Group Comment Jumpers Connections
JG1 Use on-board EXTAL crystal input for oscillator 1–2
JG2 Use on-board XTAL crystal input for oscillator 1–2
JG3 Enable on-board Parallel JTAG Host/Target Interface NC
JG4 Enable Internal Boot Mode 1–2
JG5 Enable A0 - A23 for external memory accesses NC
JG6 Enable Crystal Mode 1–2
JG7 Enable SRAM Memory Bank 0 (use CS0) 1–2
JG8 Enable SRAM Memory Bank 1 (use CS1 & CS4) 1–2 & 3–4
JG9 Pass RXD0 & TXD0 to RS-232 level converter 1–2 & 3–4
JG10 Enable RS-232 output NC
JG11 Pass RS-232 RST to CTS 1–2
JG12 Pass Temperature Diode to ANA7 1–2
JG13 CAN termination selected 1–2
JG14 Isolate CAN2 (Unpopulated option) NC
JG15 High selected on User Jumper #0 1–2
JG16 High selected on User Jumper #1 1–2
MC56F8357EVM
U4
J3
JTAG
P2
S/N
LED3
P1
Y1
U1
U2
S2 S1
S3 P3
PC0
JG2
JG6
U8
RESET IRQB IRQA
1
2
JG9
JG18
JG3
JG1
JG15
JG10
JG9
1
JG15
3
JG10
PC1
PC2
PC3
PD6
PD7
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
U3
U9
JG19
JG13
JG8
J20
J21
JG16
J10
J9
J2
J1
J7 J8 J6 J12 J14
J16
J11 J13 J15 J19 J14
1
JG19 3
1
JG16
3
3
4
1
JG1
3
JG2 JG3
JG18
1
2
JG14
3
4
JG5 JG7
JG11
JG12
JG6 JG4
1
2
JG8
3
4
JG17
JG13
J22
J23
J18
J17
JG12
JG11
J5
JG4 JG5 J24 JG7
J4
JG17

56F8357EVM User Manual, Rev. 1
1-4 FreescaleSemiconductor
Preliminary
1.3 56F8357EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply to the 56F8357EVM board.
Figure 1-3. Connecting the 56F8357EVM Cables
Perform the following steps to connect the 56F8357EVM cables:
1. Connect the parallel extension cable to the Parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the
56F8357EVM board. This provides the connection which allows the host computer to
control the board.
3. Make sure that the external +12V DC, 1.2A power supply is not plugged into a +120V AC
power source.
4. Connect the 2.1mm output power plug from the external power supply into P3, shown in
Figure 1-3, on the 56F8357EVM board.
5. Apply power to the external power supply. The green Power-ON LED, LED13, will
illuminate when power is correctly applied.
JG17 CAN2 not terminated (Unpopulated option) NC
JG18 Analog Ground to Digital Ground not reconnected NC
JG19 Use +3.3V for Printer Interface to on-board Parallel JTAG Host/Target 1-2
Table 1-1. 56F8357EVM Default Jumper Options (Continued)
Jumper
Group Comment Jumpers
Connections
PC-compatible
Cable
Computer
Parallel Extension
56F8357EVM
External
+12V
Power
P1
P3
Connect cable
to Parallel/Printer port
with 2.1mm,
receptacle
connector

Technical Summary, Rev. 1
Freescale Semiconductor 2-1
Preliminary
Chapter 2
Technical Summary
The 56F8357EVM is designed as a versatile development card using the 56F8357 processor,
allowing the creation of real-time software and hardware products to support a new generation of
applications in servo and motor control, digital and wireless messaging, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit 56F8357
processor, combined with the on-board 128K ×16-bit external Program/Data Static RAM
(SRAM), 128K ×16-bit external Data/Program SRAM, RS-232 interface, CAN interface,
Daughter Card interface, Peripheral Expansion connectors and parallel JTAG interface, makes
the 56F8357EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F8357 processor.
The main features of the 56F8357EVM, with board and schematic reference designators include:
• 56F8357PY60, a 16-bit +3.3V/+2.5V hybrid controller operating at 60MHz [U1]
• External Fast Static RAM (FSRAM) memory, configured as:
— 128K × 16-bit of memory [U2] with 0 Wait State at 60MHz via CS0
— 128K × 16-bit of memory [U3] with 0 Wait State at 60MHz via CS1/CS2
• 8.00MHz crystal oscillator, for base processor frequency generation [Y1]
• Optional external oscillator frequency input connectors [JG1 and JG2]
• Joint Test Action Group (JTAG) port interface connector, for an external debug Host
Target Interface [J3]
• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port
cable [P1], including a disable jumper [JG3] and a printer port voltage selection jumper
[JG19]
• RS-232 interface, for easy connection to a host processor [U4 and P2], including a disable
jumper [JG10]
• RTS and CTS RS-232 control signal access [JG11]
• CAN interface, for high speed, 1.0Mbps, FlexCAN communications [U10 and J20]
• CAN bypass and bus termination [J21 and JG13]

56F8357EVM User Manual, Rev. 1
2-2 FreescaleSemiconductor
Preliminary
• Peripheral Daughter Card connector, to allow the user to connect his own SCI, SPI or
GPIO-compatible peripheral to the hybrid controller[J1]
• Memory Daughter Card connector, to allow the user to connect his own memory or
memory device to the device [J2]
• SCI #0 expansion connector, to allow the user to connect his own SCI #0 /
MPIO-compatible peripheral [J13]
• SCI #1 expansion connector, to allow the user to connect his own SCI #1 /
MPIO-compatible peripheral [J14]
• SPI #0 expansion connector, to allow the user to connect his own SPI #0 /
MPIO-compatible peripheral [J11]
• SPI #1 expansion connector, to allow the user to connect his own SPI #1 /
MPIO-compatible peripheral [J12]
• PWMA expansion connector, to allow the user to connect his own PWMA-compatible
peripheral [J7]
• PWMB expansion connector, to allow the user to connect his own PWMB-compatible
peripheral [J8]
• CAN expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J18]
• Timer A expansion connector, to allow the user to connect his own Timer A / Encoder
#0-compatible peripheral [J15]
• Timer C expansion connector, to allow the user to connect his own Timer C-compatible
peripheral [J16]
• Timer D expansion connector, to allow the user to connect his own Timer D-compatible
peripheral [J17]
• ADC A expansion connector, to allow the user to attach his own A/D port A-compatible
peripheral [J9]
• ADC B expansion connector, to allow the user to attach his own A/D port B-compatible
peripheral [J10]
• Address Bus expansion connector, to allow the user to monitor the external address bus
[J4]
• Data Bus expansion connector, to allow the user to monitor the external data bus [J5]
• External memory bus control signal connector, to allow the user to monitor the external
memory bus [J6]
• On-board power regulation provided from an external +12V DC-supplied power input
[P3]

56F8357
Technical Summary, Rev. 1
Freescale Semiconductor 2-3
Preliminary
• Light Emitting Diode (LED) power indicator [LED13]
• Six on-board real-time user debugging LEDs [LED1-6]
• Six on-board Port A PWM monitoring LEDs [LED7-12]
• Internal/External (EXTBOOT) Boot MODE selector [JG4]
• Address Range (EMI_MODE) Boot MODE selector [JG5]
• Clock MODE (CLKMODE) Boot selector [JG6]
• Temperature Sense Diode to ANA7 selector [JG12]
• Manual RESET push-button [S1]
• Manual interrupt push-button for IRQA [S2]
• Manual interrupt push-button for IRQB [S3]
• General-purpose jumper on GPIO PE4 [JG15]
• General-purpose jumper on GPIO PE7 [JG16]
2.1 56F8357
The 56F8357EVM uses a Freescale MC56F8357PY60 part, designated as U1 on the board and in
the schematics. This part will operate at a maximum external bus speed of 60MHz. A full
description of the 56F8357, including functionality and user information, is provided in these
documents:
• 56F8357 Technical Data Sheet,(56F8357):Electrical and timing specifications, pin
descriptions, device specific peripheral information and package descriptions (this
document)
•56F8300 Peripheral User Manual,(MC56F8300UM): Detailed description of peripherals
of the 56F8300 family of devices
•DSP56800E Reference Manual,(DSP56800ERM): Detailed description of the 56800E
family architecture, 16-bit core processor, and the instruction set
Refer to these documents for detailed information about chip functionality and operation. They
can be found on this URL:
www.freescale.com

56F8357EVM User Manual, Rev. 1
2-4 FreescaleSemiconductor
Preliminary
2.2 Program and Data Memory
The 56F8357EVM contains two 128K x 16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS4. This provides a total of
256K x 16 bits of external memory.
2.2.1 SRAM Bank 0
SRAM bank 0, which is controlled by CS0, uses a 128K×16-bit Fast Static RAM (GSI GS72116,
labeled U2) for external memory expansion; see the FSRAM schematic diagram in Figure 2-1.
CS0 can be configured to use this memory bank as 16 bits of Program memory, Data memory, or
both. Additionally, CS0 can be configured to assign this memory’s size and starting address to
any modulo address space.
This memory bank will operate with zero Wait State access while the MC56F8357 is running at
60MHz and can be disabled by removing the jumper at JG7.
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K × 16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-2. Using CS1 and CS4, this memory bank can be configured as byte (8-bit) or word
(16-bit) accessable Program memory, Data memory, or both. Additionally, CS1 and CS4 can be
configured to assign this memory’s size and starting address to any modulo address space.
56F8357 GS72116
A0-A16
D0-D15
RD
WR
A0-A16
DQ0-DQ15
OE
WE
CE
1 2
JG7
+3.3V
Jumper Pin 1-2:
Enable SRAM
PS/CS0
Jumper Removed:
Disable SRAM