Freescale Semiconductor ColdFire MCF5275 User manual

MCF5275EVB User’s Manual
Devices Supported:
MCF5275
MCF5275L
MCF5274
MCF5274L
MCF5275EVBUM
Rev. 1.1
11/2008

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© Freescale Semiconductor, Inc. 2004
MCF5275EVBUM
Rev. 1.0
10/2004

EMC Information on M5275EVB
1. This product as shipped from the factory with associated power supplies and cables, has been
tested and meets with requirements of EN5022 and EN 50082-1: 1998 as a CLASS A product.
2. This product is designed and intended for use as a development platform for hardware or software
in an educational or professional laboratory.
3. In a domestic environment this product may cause radio interference in which case the user may
be required to take adequate measures.
4. Anti-static precautions must be adhered to when using this product.
5. Attaching additional cables or wiring to this product or modifying the products operation from the
factory default as shipped may effect its performance and also cause interference with other appa-
ratus in the immediate vicinity. If such interference is detected, suitable mitigating measures
should be taken.

WARNI N G
This board generates, uses, and can radiate radio frequency energy and, if not installed properly, may cause
interference to radio communications. As temporarily permitted by regulation, it has not been tested for
compliance with the limits for class a computing devices pursuant to Subpart J of Part 15 of FCC rules,
which are designed to provide reasonable protection against such interference. Operation of this product
in a residential area is likely to cause interference, in which case the user, at his/her own expense, will be
required to correct the interference.

CONTENTS
Paragraph
Number Title Page Number
Freescale Contents 1
Chapter 1
M5275EVB Introduction
1.1 MCF5275 Microprocessor.................................................................................. 1-3
1.2 System Memory.................................................................................................. 1-6
1.2.1 External Flash ................................................................................................. 1-6
1.2.2 SDRAM .......................................................................................................... 1-7
1.2.3 ASRAM .......................................................................................................... 1-7
1.2.4 Internal SRAM................................................................................................ 1-7
1.2.5 M5275EVB Memory Map.............................................................................. 1-7
1.2.5.1 Reset Vector Mapping ................................................................................ 1-8
1.3 Support Logic ..................................................................................................... 1-9
1.3.1 Reset Logic ..................................................................................................... 1-9
1.3.2 Clock Circuitry ............................................................................................. 1-11
1.3.3 Watchdog Timer ........................................................................................... 1-11
1.3.4 Exception Sources......................................................................................... 1-11
1.3.5 TA Generation .............................................................................................. 1-12
1.3.6 User’s Program ............................................................................................. 1-13
1.4 Communication Ports ....................................................................................... 1-13
1.4.1 UART0, UART1, UART2 Ports................................................................... 1-13
1.4.2 10/100T Ethernet Ports ................................................................................. 1-13
1.4.3 BDM/JTAG Port........................................................................................... 1-14
1.4.4 I2C ................................................................................................................ 1-15
1.4.5 QSPI.............................................................................................................. 1-16
1.5 Connectors and User Components.................................................................... 1-16
1.5.1 Daughter Card Expansion Connectors.......................................................... 1-16
1.5.2 Reset Switch (SW5)...................................................................................... 1-20
1.5.3 User LEDs..................................................................................................... 1-21
1.5.4 Other LEDs................................................................................................... 1-21
Chapter 2
Initialization and Setup
2.1 System Configuration ......................................................................................... 2-1
2.2 Installation and Setup.......................................................................................... 2-2

2M5275EVB User’s Manual Freescale
CONTENTS
Paragraph
Number Title Page Number
2.2.1 Unpacking....................................................................................................... 2-3
2.2.2 Preparing the Board for Use ........................................................................... 2-3
2.2.3 Providing Power to the Board......................................................................... 2-3
2.2.4 Power Switch (SW3) ...................................................................................... 2-4
2.2.5 Power Status LEDs and Fuse.......................................................................... 2-4
2.2.6 Selecting Terminal Baud Rate ........................................................................ 2-5
2.2.7 The Terminal Character Format ..................................................................... 2-5
2.2.8 Connecting the Terminal ................................................................................ 2-5
2.2.9 Using a Personal Computer as a Terminal...................................................... 2-5
2.3 System Power-up and Initial Operation.............................................................. 2-8
2.4 Using The BDM Port.......................................................................................... 2-8
Chapter 3
Using the Monitor/Debug Firmware
3.1 What Is dBUG?................................................................................................... 3-1
3.2 Operational Procedure ........................................................................................ 3-3
3.2.1 System Power-up ............................................................................................ 3-3
3.2.2 System Initialization ....................................................................................... 3-4
3.2.2.1 External RESET Button.............................................................................. 3-4
3.2.2.2 ABORT Button........................................................................................... 3-4
3.2.2.3 Software Reset Command .......................................................................... 3-4
3.3 Command Line Usage ........................................................................................ 3-5
3.4 Commands .......................................................................................................... 3-5
3.5 TRAP #15 Functions ........................................................................................ 3-40
3.5.1 OUT_CHAR ................................................................................................. 3-40
3.5.2 IN_CHAR ..................................................................................................... 3-41
3.5.3 CHAR_PRESENT ........................................................................................ 3-41
3.5.4 EXIT_TO_dBUG.......................................................................................... 3-42
Appendix A
Configuring dBUG for Network Downloads
A.1 Required Network Parameters ........................................................................... A-1
A.2 Configuring dBUG Network Parameters........................................................... A-2
A.3 Troubleshooting Network Problems.................................................................. A-3
Appendix B
Schematics
B.1 M5275EVB Schematics...................................................................................... B-1

CONTENTS
Paragraph
Number Title Page Number
Freescale Contents 3
Appendix C
M5275EVB BOM
C.1 M5275EVB BOM............................................................................................... C-1

4M5275EVB User’s Manual Freescale
CONTENTS
Paragraph
Number Title Page Number

Chapter 1. M5275EVB Introduction 1-1
Chapter 1
M5275EVB Introduction
This document details the setup and configuration of the ColdFire M5275EVB evaluation
board (hereafter referred to as the EVB). The EVB is intended to provide a mechanism for
easy customer evaluation of the MCF5274, MCF574L, MCF5275, and MCF5275L
ColdFire microprocessors and to facilitate hardware and software development. The EVB
can be used by software and hardware developers to test programs, tools, or circuits without
having to develop a complete microprocessor system themselves. All special features of the
MCF5274(L) and MCF5275(L) are supported.
The heart of the evaluation board is the MCF5275. The MCF5275L and MCF5274(L) have
a subset of the MCF5275 specification and can therefore be fully emulated using the
MCF5275 device. Table 1-1., “MCF5274/75 Product Family”. below details the two
devices.
All of the devices in the same package are pin compatible.
The EVB provides for low cost software testing with the use of a ROM resident debug
monitor, dBUG, programmed into the external Flash device. Operation allows the user to
load code in the on-board RAM, execute applications, set breakpoints, and display or
modify registers or memory. No additional hardware or software is required for basic
operation.
Specifications
Table 1-1. MCF5274/75 Product Family
Part Number Package FEC CRYPTO Max Core/Bus
speed
MCF5274LVM133 196 MAPBGA x1 No 133 / 66 MHz
MCF5274LVM166 196 MAPBGA x1 No 166 / 83 MHz
MCF5274VM133 256 MAPBGA x2 No 133 / 66 MHz
MCF5274VM166 256 MAPBGA x2 No 166 / 83 MHz
MCF5275LCVM133 196 MAPBGA x1 Yes 133 / 66 MHz
MCF5275LCVM166 196 MAPBGA x1 Yes 166 / 83 MHz
MCF5275CVM133 256 MAPBGA x2 Ye s 133 / 66 MHz
MCF5275CVM166 256 MAPBGA x2 Ye s 166 / 83 MHz

1-2 M5275EVB User’s Manual
• Motorola MCF5275 Microprocessor (166 MHz max core frequency)
• External Clock source: 25MHz
• Operating temperature: 0°C to +70°C
• Power requirement: 6 – 14V DC @ 1A Typical
• Power output: 5V, 3.3V, 2.5V and 1.5V regulated supplies
• Board Size: 10.00 x 5.40 inches, 8 layers
Memory Devices:
• 16-Mbyte DDR SDRAM
• 2-Mbyte (512K x 16) Page Mode Flash or 4-Mbyte (512K x 32) Page mode Flash
• 1-Mbyte ASRAM (footprint only)
• 64-Kbyte SRAM internal to MCF5275 device
Peripherals:
• FEC0 Ethernet port 10/100Mb/s (Dual-Speed Fast Ethernet Transceiver, with MII)
• FEC1 Ethernet port 10/100Mb/s (Dual-Speed Fast Ethernet Transceiver, with MII)
• USB 2.0 Full Speed (Device)
• UART0 (RS-232 serial port for dBUG firmware)
• UART1 (auxiliary RS-232 serial port)
• UART2 (auxiliary RS-232 serial port)
•I
2C interface
• QSPI interface
• BDM/JTAG interface
User Interface:
• Reset logic switch (debounced)
• Boot logic selectable (dip switch)
• Abort/IRQ7 logic switch (debounced)
• PLL Clocking options - Oscillator, Crystal or SMA for external clocking signals
• LEDs for power-up indication, general purpose I/O, and timer output signals
• Expansion connectors for daughter card
Software:
• Resident firmware package that provides a self-contained programming and
operating environment (dBUG)

Chapter 1. M5275EVB Introduction 1-3
MCF5275 Microprocessor
Figure 1-1. M5275EVB block diagram
1.1 MCF5275 Microprocessor
The microprocessor used on the EVB is the highly integrated Motorola MCF5275 32-bit
ColdFire variable-length RISC processor. The MCF5275 implements a ColdFire Version 2
core with a maximum core frequency of 166MHz and external bus speed of 83MHz.
Features of the MCF5275 include:
• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 159
Dhrystone 2.1MIPS @ 166MHz
• 64 KBytes of internal SRAM
• External bus speed of one half the CPU operating frequency (83MHz bus @
166MHz core)
• Two 10/100 BaseT Fast Ethernet Controllers (FECs)
• 16 Kbytes of configurable instruction/data cache
ColdFire MCF5275
(4) 60 pin Daughter Card
Expansion Connectors
Peripheral Signals
Data [31:0]
Address [23:0]
Control Signals
DDR SDRAM
16 MBytes
Flash
2-4 MBytes
ASRAM
1 MByte
26-pin Debug Header
RS-232
Transceivers (3)
DB-9
Connectors (3)
2x Ethernet
Transceiver
2x RJ-45
Connector
25 MHz
Osc.
USB
Connector
USB PHY

1-4 M5275EVB User’s Manual
MCF5275 Microprocessor
• Three universal asynchronous receiver/transmitters (UARTs) with DMA support
• Inter-integrated circuit (I2C) bus controller
• Queued serial peripheral interface (QSPI) module
• Hardware cryptography accelerator (optional)
— Random number generator
— DES/3DES/AES block cipher engine
— MD5/SHA-1/HMAC accelerator
• Four channel 32-bit direct memory access (DMA) controller
• Four channel 32-bit input capture/output compare timers with optional DMA
support
• Four channel 16-bit periodic interrupt timers (PITs)
• Programmable software watchdog timer
• Interrupt controller capable of handling up to 126 interrupt sources
• Clock module with Phase Locked Loop (PLL)
• External bus interface module including a DDR SDRAM controller
• 32-bit non-multiplexed bus with up to 8 chip select signals that support page-mode
Flash memories
The MCF5275 communicates with external devices over a 16-bit wide data bus, D[31:16].
The MCF5275 can address a 32 bit address range. However, only 24 bits are available on
the external bus A[23:0]. There are internally generated chip selects to allow the full 32 bit
address range to be selected. There are regions that can be decoded to allow supervisor,
user, instruction, and data each to have the 32-bit address range.
All the processor's signals are available via daughter card expansion connectors. Refer to
the schematic (Appendix B) for their pin assignments.
The MCF5275 processor has the capability to support both BDM and JTAG. These ports
are multiplexed and together. In BDM mode it can be used with third party tools to allow
the user to download code to the board. In JTAG mode it can be used for boundary scan
operations. The board is configured to boot up in the normal/BDM mode of operation. The
BDM signals are available at the port labeled BDM.
Figure 1-2 shows the MCF5275 processor block diagram.

Chapter 1. M5275EVB Introduction 1-5
MCF5275 Microprocessor
Figure 1-2. MCF5275 Block Diagram
64 Kbytes
SRAM
(8Kx16)x4
EIM
V2 ColdFire CPU
INTC0
Watchdog
PIT0
JTAG
TAP
CACHE
(1Kx32)x4
PIT1 PIT2 PIT3
4 CH DMA
UART
0
UART
1I2CQSPI
DTIM
0
DTIM
1
DTIM
2
DTIM
3
Timer
PLL
CLKGEN
UART
2
16 Kbytes
Edge
Port
SDRAMC
CHIP
EBI
SELECTS
(To/From PADI)
(To/From
PORTS
CIM
(GPIO)
DIV EMAC
DREQ[1:0]
INTC1
Arbiter
(To/From SRAM backdoor)
(To/From Arbiter backdoor)
SKHA
RNGA
MDHA
Cryptography
Modules
DACK[3:0]
BDM
(To/From INTC)
MUX
PADI)
JTAG_EN
PADI – Pin Muxing
BS[3:2]
PWMn
USB
FEC0
DTnIN
DTnOUT
Un RXD
Un TXD
I2C_SDA
I2C_SCL
DDR
QSPI
UnRTS
UnCTS
D[31:16]
A[23:0]
R/ W
CS[3:0]
TA
TSIZ[1:0]
TEA
FEC1
JTAG_EN
TRST
TCLK
TMS
TDI
TDO
(To/From
PADI)
(To/From PADI) FAST ETHERNET
CONTROLLER
(FEC1)
FAST ETHERNET
CONTROLLER
(FEC0)
4 CH PWM
(To/From PADI)
USB 2.0
Full Speed
(To/From PADI)

1-6 M5275EVB User’s Manual
System Memory
1.2 System Memory
The following diagram shows the external memory implementation on the M5275EVB.
Figure 1-3. External Memory Scheme
NOTE
The external bus interface signals to the external ASRAM and
Flash are buffered. This is in order to separate the 2.5V bus to
the DDR from the 3.3V bus to the Flash and ASRAM.
The external bus signals to the expansion connectors are
buffered to 3.3V to provide a 3.3V interface to the user.
1.2.1 External Flash
The EVB is fitted with a single 1M x 16 page-mode Flash memory (U11) giving a total
memory space of 2 MBytes. Alternatively a footprint is available for the EVB user to
upgrade this device to a 2M x 16 page-mode Flash memory (U12), doubling the memory
size to 4 MBytes. Either U11 OR U12 should be fitted on the board - both devices cannot
be populated at the same time. Refer to the specific device data sheet and sample software
provided for information on configuring the Flash memory.
Users should note that the debug monitor firmware is installed on this flash device.
Development tools or user application programs may erase or corrupt the debug monitor. If
the debug monitor becomes corrupted and it’s operation is desired, the firmware must be
reprogrammed into the flash by using a development tool through the BDM port. Users
Expansion
Connectors
DDR SDRAM
(16MBytes)
ASRAM
(1MByte)
Flash
(1M x 16)
or
(2M x 16)
Buffers
Data
Address
Control
MCF5275

Chapter 1. M5275EVB Introduction 1-7
System Memory
should use caution to avoid this situation. The M5275EVB dBUG debugger/monitor
firmware is programmed into the lower sectors of Flash (0xFFE0_0000 to 0xFFE3_FFFF
for 2 MBytes of Flash or 0xFFC0_0000 to 0xFFC3_FFFF for 4 MBytes of Flash).
When U11 is fitted on the EVB, jumper 3 (JP3) provides an alternative hardware
mechanism for write protection. This feature is not available when U10 is populated.
1.2.2 SDRAM
The EVB is populated with 16 MBytes of SDRAM. This is done with a single device
(Micron MT46V16M16TG) with a 16 bit data bus. The device (U7) is organized as 2Meg
x 16 x 4 banks with a 16 bit data bus.
1.2.3 ASRAM
The EVB has a footprint for one 256K x 16 Asynchronous SRAM devices (Cypress
Semiconductor - CY7C1041CV3310ZC). These memory devices (U1) may be populated
by the user for benchmarking purposes.
1.2.4 Internal SRAM
The MCF5275 processor has 64 KBytes of internal SRAM memory which may be used as
data or instruction memory. This memory is mapped to 0x2000_0000 by the dBUG
monitor, but is not used by the dBUG monitor except during system initialization. After
system initialization is complete, the internal memory is available to the user. The memory
is relocatable to any 64 KByte boundary within the processor’s four gigabyte address space.
1.2.5 M5275EVB Memory Map
Signals to support the interface to external memory and peripheral devices are generated by
the memory controller. The MCF5275 supports 8 external chip selects, CS[1:0] and
SD_CS0 are used with external memories on the EVB. CS0 also functions as the global
(boot) chip-select for booting out of external flash. All chip selects (CS[7:0] and
SD_CS[1:0]) are easily accessible to users via the daughter card expansion connectors.
Since the MCF5275 chip selects are fully programmable, the memory banks may be located
at any 64-KByte boundary within the processor’s four gigabyte address space.
Table 1-2 shows the default memory map for this board as configured by the dBUG monitor
located in the external Flash bank. The internal memory space of the MCF5275 is detailed
further in the MCF5275 Reference Manual. Chip Selects 0 and 1 can be changed by user
software to map the external memory in different locations but the chip select configuration
such as wait states and transfer acknowledge for each memory type should be maintained.

1-8 M5275EVB User’s Manual
System Memory
Table 1-2 shows the M5275EVB memory map.
1.2.5.1 Reset Vector Mapping
Asserting the reset input signal to the processor causes a reset exception. The reset
exception has the highest priority of any exception; it provides for system initialization and
recovery from catastrophic failure. Reset also aborts any processing in progress when the
reset input is recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the S-bit and
disables tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets
the processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the
VBR is initialized to zero (0x0000_0000). The control registers specifying the operation of
any memories (e.g., cache and/or RAM modules) connected directly to the processor are
disabled.
Once the processor is granted the bus, it then performs two longword read bus cycles. The
first longword at address 0 is loaded into the stack pointer and the second longword at
address 4 is loaded into the program counter. After the initial instruction is fetched from
memory, program execution begins at the address in the PC. If an access error or address
error occurs before the first instruction is executed, the processor enters the fault-on-fault
halted state.
The port size of the memory that the MCF5275 accesses at address 0x0000_0000 is
determined at reset by sampling D[20:19].
Table 1-2. The M5275EVB Default Memory Map
Address Range Chip Select Signal and Device
0x0000_0000 - 0x00FF_FFFF SD_CS0 16 MByte SDRAM (U7)
0x2000_0000 - 0x2000_FFFF —64 KBytes Internal SRAM
0x3000_0000 - 0x300F_FFFF CS1 512 KByte External ASRAM (not fitted) (U1)
0xFFE0_0000 - 0xFFFF_FFFF
or
0xFFC0_0000 - 0xFFFF_FFFF
CS0 2 MBytes External Flash (U11)
or
4 MBytes External Flash (U12)
Table 1-3. D[20:19] External Boot Chip Select Configuration
D[20:19] Boot Device/Data Port Size
00 Reserved
01 External (16-bit)
10 External (8-bit)
11 Reserved

Chapter 1. M5275EVB Introduction 1-9
Support Logic
1.3 Support Logic
1.3.1 Reset Logic
Reset occurs during power-on or via assertion of the signal RESET which causes the
MCF5275 to reset. RESET is triggered by the reset switch (SW5) which resets the entire
processor/system.
The dBUG Firmware configures the MCF5275 microprocessor internal resources during
initialization. The contents of the exception vector table are copied to address 0x0000_0000
in the SDRAM. The Software Watchdog Timer is disabled, the Bus Monitor is enabled, and
the internal timers are placed in a stop condition. A memory map for the entire board can
be seen in Table 1-2.
If the external RCON pin is asserted (SW6-1 ON) during reset, then various chip functions,
including the reset configuration pin functions after reset, are configured according to the
levels driven onto the external data pins. See tables below on settings for reset
configurations.
If the RCON pin is negated (SW6-1 OFF) during reset, the chip configuration and the reset
configuration pin functions after reset are determined by the RCON register or fixed
defaults, regardless of the states of the external data pins.
Table 1-4. SW6-1 RCON
SW6-1 Reset Configuration
OFF RCON not asserted, Default Chip configuration or RCON register settings
ON RCON is asserted, Chip functions, including the reset configuration after reset,
are configured according to the levels driven onto the external data pins.
Table 1-5. SW6-2 JTAG_EN
SW6-2 JTAG Enable
OFF JTAG interface enabled
ON BDM interface enabled
Table 1-6. SW6-[4:3] Encoded Clock Mode
SW6-3 SW6-4 Clock Mode
ON ON Normal PLL mode with external clock reference
ON OFF Normal PLL mode with external clock reference
OFF ON External clock mode- (PLL disabled)
OFF OFF 1:1 PLL mode

1-10 M5275EVB User’s Manual
Support Logic
Table 1-7. SW6-[7:5] Chip Mode
SW6-5 SW6-6 SW6-7 RCON
(SW6-1) Mode
ON ON ON ON Master mode
ON ON OFF ON Reserved
ON OFF ON ON Reserved
ON OFF OFF ON Reserved
OFF X X ON Reserved
XXXOFF Master mode
Table 1-8. SW6-[9:8] Boot Device
SW6-8 SW6-9 RCON
(SW6-1) Boot Device
ON ON ON External (16-bit)
ON OFF ON Reserved
OFF ON ON Reserved
OFF OFF ON External (8-bit)
X X OFF External (16-bit)
Table 1-9. SW6-10 Bus Drive Strength
SW6-10 RCON
(SW6-1) Drive Strength
ON ON Full Bus Drive
OFF ON Partial Bus Drive
XOFF Full Bus Drive
Table 1-10. SW6-[12:11] Address/Chip Select Mode
SW6-11 SW6-12 RCON
(SW6-1) Mode
ON ON ON PADDR[7:5] = A[23:21]
ON OFF ON PADDR7 = CS6; PADDR[6:5] = A[22:21]
OFF ON ON PADDR[7:6] = CS[6:5]; PADDR5 = A21
OFF OFF ON PADDR[7:5] = CS[6:4]
X X OFF PADDR[7:5] = A[23:21]

Chapter 1. M5275EVB Introduction 1-11
Support Logic
1.3.2 Clock Circuitry
The are three options to provide the clock to the CPU. Table 1-11 shows how these options
can be configured by setting JP9 and JP10.
The 25MHz oscillator (U19) also feeds the Ethernet transceiver chips (U8 and U9).
1.3.3 Watchdog Timer
The dBUG Firmware does NOT enable the watchdog timer on the MCF5275.
1.3.4 Exception Sources
The ColdFire® family of processors can receive seven levels of interrupt priorities. When
the processor receives an interrupt which has a higher priority than the current interrupt
mask (in the status register), it will perform an interrupt acknowledge cycle at the end of
the current instruction cycle. The MCF5275’s interrupt controller will respond to the
interrupt acknowledge cycle with the vector number for the interrupt (refer to the MCF5275
Reference Manual for more information on the interrupt controller function).
The vector number is used as an index into the exception vector table that contains the
interrupt service routine locations. This table is stored in the board’s Flash memory. The
address of the table location is stored in the VBR. The dBUG ROM monitor writes a copy
of the exception table into the RAM starting at 0x0000_0000. To set an exception vector,
the user places the address of the exception handler in the appropriate vector in the vector
table located at 0x0000_0000 and then points the VBR to 0x0000_0000.
The MCF5275 microprocessor has seven external interrupt request lines IRQ[7:1]. Each
external interrupt can be configured individually as a level-sensitive interrupt pin or an
edge-detecting interrupt pin (rising edge, falling edge, or both).
Two on-chip interrupt controllers are capable of providing unique vectors for all of the
on-chip and external interrupt sources. Interrupt controller 0 (INTC0) handles the following
interrupt sources:
• External interrupt signals IRQ[7:1] (EPORT)
• Software watchdog timer module
• Four DMA channels
• UART modules (UART0–UART2)
Table 1-11. M5275EVB Clock Source Selection
JP9 JP10 Clock Selection
1-2 1-2 25MHz Oscillator (default setting)
2-3 1-2 25MHz External Clock
X2-3 25MHz Crystal

1-12 M5275EVB User’s Manual
Support Logic
•I
2C module
• QSPI module
• Timer modules
• Fast Ethernet Controller (FEC0)
• Periodic Interrupt Timers (PIT0–PIT3)
• Random Number Generator (RNG)
• Symmetric Key Hardware Accelerator (SKHA)
• Message Digest Hardware Accelerator (MDHA)
• USB module
Interrupt controller 1 (INTC1) handles these interrupt sources:
• Fast Ethernet Controller (FEC1)
No interrupt sources should have the same level and priority as another interrupt within the
same interrupt controller. Programming two interrupt sources with the same level and
priority can result in undefined operation.
The M5275EVB hardware uses IRQ7 to support the ABORT function using the ABORT
switch (SW4). This switch is used to force an interrupt (level 7, mid-point priority) if the
user's program execution should be aborted without issuing a RESET (refer to Chapter 2
for more information on ABORT).
Refer to MCF5275 Reference Manual for more information about the interrupt controller.
1.3.5 TA Generation
The processor starts a bus cycle by asserting CSnwith the other control signals. The
processor then waits for a transfer acknowledgment (TA) either internally (using the chip
select’s auto acknowledge - AA mode) or externally before it can complete the bus cycle.
TA is used to indicate the completion of the bus cycle. It also allows devices with different
access times to communicate with the processor properly asynchronously. The MCF5275
processor, as part of the chip-select logic, has a built-in mechanism to generate TA for all
external devices which do not have the capability to generate this signal. For example, the
Flash cannot generate a TA signal. The chip-select logic is programmed by the dBUG ROM
Monitor to generate TA internally after a pre-programmed number of wait states.
In order to support future expansion of the M5275EVB, the TA input of the processor is
also connected to the expansion connectors (U9). This allows any expansion boards to
assert this line to provide a TA signal to the processor. On the expansion boards this signal
should be generated through an open collector buffer with no pull-up resistor; a pull-up
resistor is included on this board. All TA signals from expansion boards should be
connected to this line.