Freescale Semiconductor T4240 User manual

Freescale Semiconductor
Quick Start
© 2015 Freescale Semiconductor, Inc. All rights reserved.
The QorIQ T4240 development system (T4240QDS-PB) is
a flexible system that supports the 24 threads. The
T4240QDS main board is mounted in a 4U rack-mounted
chassis and the main PCB is a custom form factor.
An additional layer of flexibility for system clocking, power
distribution, and I/O multiplexing is built into the
T4240QDS board. Eight expansion slots are provided for
adding standard PCIe cards or Freescale specialized SerDes
riser cards (XFI or XAUI networking). The T4240QDS
board comes with a Linux® board support package (BSP)
that provides a comprehensive starting point for Linux
development efforts.
The T4240QDS board is available in two form factors:
• T4240QDS board installed in a chassis
• T4240QDS board as a stand-alone system
When you finish reading this document, you should be
familiar with:
• T4240QDS hardware kit contents
• Board configuration settings
• How to get started and boot the board
Document Number:T4240QDSQSG
Rev.1, 10/2015
Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Hardware kit contents . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. T4240QDS board diagram . . . . . . . . . . . . . . . . . . . . . 3
4. Connections and switch settings . . . . . . . . . . . . . . . . . 4
5. Starting up and booting system . . . . . . . . . . . . . . . . . 13
6. Pre-loaded RCW and boot flash information . . . . . . 18
7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
QorIQ T4240 Development System
Quick Start

1 Introduction
This T4240QDS quick start explains the T4240QDS board settings and physical connections needed to
boot the board. The document provides steps for configuring switches, connectors, jumpers, push buttons,
LEDs, and connecting peripheral devices.
The T4240QDS board works with an integrated development environment (IDE), such as Freescale
CodeWarrior. However, instructions for working with the IDE are beyond the scope of this document.
1.1 Acronyms and abbreviations
Table 1 lists commonly used acronyms and abbreviations.
1.2 Related documentation
The following table lists the documents that you can refer to for more information about the T4240QDS
board operations.
Table 1. Acronyms and abbreviations
IDE Integrated Development Environment PLL Phase Lock Loop
QDS QorIQ Development System SerDes Serializer/Deserializer
RCW Reset Configuration Word USB Universal Serial Bus
PHY Physical Layer Interface Device
Table 1-2. Related documentation
Document name Description
T4240 QorIQ Integrated Multicore
Communications Processor Family
Reference Manual (document
T4240RM)
Provides details about the features and functionalities of the T4240 QorIQ
Integrated Multicore Communications Processor Family.
Link:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=T4240&fpsp
=1&tab=Documentation_Tab
QorIQ T4240 Development System -
Fact Sheet (document T4240QDSFS)
Provides details about the features of the 4240 Development System Board.
Link:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=T4240QDS
&fpsp=1&tab=Documentation_Tab
T4240 QorIQ
Integrated Multicore Communications
Processor (document T4240)
Provides specific data regarding DC characteristics, power sequencing, input
clocks, interfaces, as well as other design considerations.
Link:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=T4240&fpsp
=1&tab=Documentation_Tab
QorIQ T4240 Development System
Reference Manual (document
T4240QDSRM)
Provides details about the features and functionalities of the T4240 Development
System Board.
Link:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=T4240QDS
&fpsp=1&tab=Documentation_Tab

QorIQ T4240 Development System Quick Start, Rev.1
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Hardware kit contents
2 Hardware kit contents
Refer to the pack-out list for the list of items included in the kit.
3 T4240QDS board diagram
Figure 1 and Figure 2 shows the T4240QDS board.
Figure 1. T4240QDS board - Components
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Figure 2. T4240QDS board and case
4 Connections and switch settings
This section explains the T4240QDS connections and switch settings.
4.1 Connection settings
In order to operate the T4240QDS and U-Boot, you need to connect different cables to the board. Some of
the cable connections are required, however, some of the connections are optional.
1. Fan cable (Required): Ensure the 3-wire cable from the pre-installed fan is connected to the 3-pin
Prod Fan header at J15.
This fan cable should already be installed in the received shipment, however ensure that this
connection is always made before powering on the system.

QorIQ T4240 Development System Quick Start, Rev.1
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Connections and switch settings
Figure 3. Main fan cable connection
2. DDR DIMMs (Required): Ensure that at least three DDR DIMMs are installed, one for each of
the three DDR controllers, as shown in Figure 4. Otherwise, U-Boot will not boot. DIMMs should
be in the following slots:
— J23 - D2_DIMM #1, pre-installed DDR3 2GB uDIMM 72 bit (with ECC) Single Rank
— J22 - D1_DIMM #1, pre-installed DDR3 2GB uDIMM 72 bit (with ECC) Single Rank
— J200 - D3_DIMM #1, pre-installed DDR3 2GB uDIMM 72 bit (with ECC) Single Rank
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Figure 4. Default DDR DIMM assembly
3. Power supply (Required): If your power supply appears similar to the power supply shown in
Figure 5, perform the following steps to connect the power supply to the T4240QDS system. For
power supply setup and connections:
a) Gather the following items from the packaging:
— 750 W Magna Gold power supply w/ AC power cord, see Figure 5
— 6-pin to 8-pin +12V supply power cable adapter, see Figure 6
Figure 5. Power supply
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QorIQ T4240 Development System Quick Start, Rev.1
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Connections and switch settings
Figure 6. 12 V power cable adapter
b) Attach the AC cable to the power supply. Note the location of the main power supply ON/OFF
switch near the AC plug.
c) The output cabling from the power supply consists of many cables, but only three of them are
attached to the T4240QDS board. Separate the three output power cables from the rest of the
cabling bundle, see Figure 7.
Figure 7. Output power cables to be separated from cabling bundle
d) Next, attach the 12 V power adapter cable to the 6-pin VGA1 connector of the power supply
as shown in Figure 8.
Note that the 2-pin part of the VGA1 connector is unused and does not attach to anything. Be
careful to attach the 6-pin end of the adapter cable to the 6-pin portion of the VGA1 power
supply connector. Also ensure that the latching mechanism of the VGA1 connector aligns with
the latching tab of the 6-pin adapter cable connector, as shown in Figure 9.

Figure 8. 12 V power adapter cable attached to the 6-pin VGA1 connector
Figure 9. Latch of VGA1 connector aligned with latching tab of adapter connector
e) To attach the power supply cables to the T4240QDS system:
– Attach the 2x4 P8 power supply connector to the EPS_BULK_12V header (J27) of the
T4240QDS board. Be careful that connector latch aligns with the latching tab of the mating
connector of the board.
– Attach the 2x4 end of the 12 V adapter cable to the EPS_12V header (J225) of the
T4240QDS board. Be careful that connector latch aligns with the latching tab of the mating
connector of the board.
– The main supply connector consists of two parts: a 2x2 section and a 2x10 section. Attach
the 2x2 section of the main power supply connector to the right-most side of the ATX24
connector (J30), and then attach the 2x10 section of the main power supply connector to the
left-most side of the ATX24 connector (J30). Be careful that connector latch aligns with the
latching tab of the mating connector of the board. Figure 10 and Figure 11 shows the before
and after images of these power supply connections.

QorIQ T4240 Development System Quick Start, Rev.1
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Connections and switch settings
Figure 10. Power supply connections (before insertion)
Figure 11. Completed power supply connections (after insertion)

4. Serial cable (Required): Attach serial cable to UART1_BOTTOM port of the T4240QDS as
shown in Figure 13. Attach other end of cable to the serial port of PC. This connection provides
visibility of boot activity to the COM port window of the PC. Configure the serial port of the host
PC with the settings shown in Figure 12.
Figure 12. Serial port configuration settings
5. Ethernet cable (Optional): Figure 13 shows Ethernet cable connection to the ENET TOP
connector. This ENET port is defined as FM1@DTSEC5. This connection is not required to boot
the system. However, it is useful in loading the boot images from an external boot image source.
Figure 13. Ethernet and serial connections.
6. JTAG / COP TAP (Optional): For additional development purposes, a TAP pod (such as
CodeWarrior USB TAP) can be attached to the COP/JTAG_TAP header at the location J216 on
the board. CCS software application is installed on the PC to support this system control interface.
The red cable edge should be oriented toward the left side of the connector where Pin 1 is located.
4.2 Configuring the T4240QDS in chassis
If the T4240QDS comes in a chassis, it appears as shown in Figure 14:

QorIQ T4240 Development System Quick Start, Rev.1
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Connections and switch settings
Figure 14. T4240QDS in chassis
The differences between configuring the T4240QDS standalone system and the T4240QDS in chassis are:
• In chassis, the main power supply is attached at the right hand side, inside the chassis. The main
power switch is located at the back. The main board is powered by pressing the POWER push
button at the front. It can also be powered by pressing the red push button switch (SW11) on the
main board. Note that all power cables are already attached to the main board in the shipped
configuration.
• In chassis, power LED at the front indicates when main board power is applied.
• In chassis, Reset push button at the front controls main reset of the system.
• In chassis, a SATA drive is included and is attached inside the chassis near the front of the unit. The
SATA drive is connected to the SATA1 port of the main board.
• In chassis, airflow is managed by three fans at the front.
4.3 Switch settings
Ensure that the switch settings for SW1 through SW9 are configured as shown in Figure 15. For more
details on decoding the switch settings, see the QorIQ T4240 Development System Reference Manual.

Figure 15. SW1-SW9 switch settings
4.3.1 Default switch settings
The default switch settings for the T4240QDS board are:
• It is important to have SW1= 0x17 . This setting lets RCW to be fetched from the on board 16 bit
NOR flash memory. As a backup, the RCW is also stored in the on board eMMC device. The
eMMC RCW image is accessed if
SW1= 0x20 and SW2= 0b0xxx xxxx .
• For PROMJET operation, SW6 position 1-4 should be 1000.
• SW9= 0x1f connects SD4 SerDes lanes 4-7 to the SATA connectors. For SRIO SerDes connections
in slots 6 and 8,
SW9= 0x5f . This connects SD4 lanes 4-7 to slot 8.
Table 4-3. Switch settings
Switches Settings
SW1 0x17
SW2 0xfe
SW3 0x0c
SW4 0x50
SW5 0xe2
SW6 0x0f
SW7 0xea
SW8 0xcd
SW9 0x1f

QorIQ T4240 Development System Quick Start, Rev.1
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Starting up and booting system
5 Starting up and booting system
To start up and boot the T4240QDS board:
1. Turn ON the power by toggling the switch on the back of the 600 W power supply. Only the
HOT_3V and HOT_5V LEDs should illuminate.
Figure 16. llluminated LEDs
2. Switch on the T4240QDS board by pressing the red POWER push button switch (SW11), as
shown in Figure 17.
Figure 17. Red POWER push button switch

3. After a few seconds, the board will turn on with the LEDs illuminated, as shown in the following
figures, and the U-Boot output will appear on the COM port screen.
Figure 18. Power LEDs after start up: All ON except POVDD
Figure 19. PASS LED ON after start up: All others are OFF

QorIQ T4240 Development System Quick Start, Rev.1
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Starting up and booting system
Figure 20. M7 LED ON after start up: All others are OFF
4. The following U-Boot text is displayed on the COM port screen:
U-Boot 2015.01QorIQ-SDK-V1.8+g6ba8eed (Jun 14 2015 - 04:47:06)
CPU0: T4240E, Version: 2.0, (0x82480020)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1800 MHz, CPU1:1800 MHz, CPU2:1800 MHz, CPU3:1800 MHz,
CPU4:1800 MHz, CPU5:1800 MHz, CPU6:1800 MHz, CPU7:1800 MHz,
CPU8:1800 MHz, CPU9:1800 MHz, CPU10:1800 MHz, CPU11:1800 MHz,
CCB:733.333 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz
FMAN1: 733.333 MHz
FMAN2: 733.333 MHz
QMAN: 366.667 MHz
PME: 533.333 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 1607001b 18101b16 00000000 00000000

00000010: 04362858 30548c00 ec020000 f5000000
00000020: 00000000 ee0000ee 00000000 000307fc
00000030: 00000000 00000000 00000000 00000028
Board: T4240QDS, Sys ID: 0x1e, Sys Ver: 0x12, vBank: 0
FPGA: v6 (T4240QDS_2014_0211_1852), build 547 on Wed Feb 12 00:52:40 2014
SERDES Reference Clocks: SERDES1=125MHz SERDES2=125MHz SERDES3=100MHz SERDES4=100MHz
I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM
Detected UDIMM
Detected UDIMM
22 GiB left unmapped
24 GiB (DDR3, 64-bit, CL=13, ECC on)
DDR Controller Interleaving Mode: 3-way 4KB
DDR Chip-Select Interleaving Mode: CS0+CS1
VID: Core voltage sensor error
VID: Could not read voltage sensor abort VID adjustment
Warning: Adjusting core voltage failed.
Flash: 128 MiB
L2: 2 MiB enabled
enable l2 for cluster 1 fec60000
enable l2 for cluster 2 feca0000
Corenet Platform Cache: 1.5 MiB enabled
Using SERDES1 Protocol: 1 (0x1)
Using SERDES2 Protocol: 27 (0x1b)
Using SERDES3 Protocol: 5 (0x5)
Using SERDES4 Protocol: 11 (0xb)
SRIO1: enabled
SRIO2: disabled
SEC0: RNG instantiated
NAND: 512 MiB
MMC: FSL_SDHC: 0
EEPROM: CRC mismatch (730852df != 365319b1)
PCIe1: Root Complex, no link, regs @ 0xfe240000

QorIQ T4240 Development System Quick Start, Rev.1
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Starting up and booting system
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, x1 gen1, regs @ 0xfe260000
02:00.0 - 8086:10d3 - Network controller
PCIe3: Bus 01 - 02
PCIe4: disabled
In: serial
Out: serial
Err: serial
Net: Fman1: Uploading microcode version 106.4.15
Fman2: Uploading microcode version 106.4.15
Phy 12 not found
PHY reset timed out
Phy 13 not found
PHY reset timed out
Phy 14 not found
PHY reset timed out
Phy 15 not found
PHY reset timed out
Phy 9 not found
PHY reset timed out
Phy 11 not found
PHY reset timed out
Phy 10 not found
PHY reset timed out
e1000: 68:05:ca:0f:23:a3
FM1@DTSEC5 [PRIME], FM1@TGEC1, FM1@TGEC2, FM2@DTSEC1, FM2@DTSEC2, FM2@DTSEC3, FM2@DTSEC4,
FM2@DTSEC5, FM2@DTSEC6, FM2@DTSEC9, FM2@DTSEC10, e1000#0
Warning: e1000#0 MAC addresses don't match:
Address in SROM is 68:05:ca:0f:23:a3
Address in environment is 00:04:9f:00:7a:0b
Hit any key to stop autoboot: 0
=>

6 Pre-loaded RCW and boot flash information
Following are the RCW default settings:
• 1667 MHz CPU, 733 MHz CCB, 1867 MT/s DDR
• RGMII-1 (TOP) = FM1@DTSEC5
• RGMII-2 (BOT) = FM2@DTSEC5
• SerDes REFCLK = 125 MHz for SD1 and SD2
• SerDes REFCLK = 100 MHz for SD3 and SD4
• SerDes1= Protocol 1 [XAUI in slot 1 and slot 2]
• SerDes2= Protocol 28 (decimal) [4x SGMII in slot 3 and slot 4]
• SerDes3= Protocol 6 [PCIe x4 in slot 5, SRIO x4 in slot 6]
• SerDes4= Protocol 12 (decimal) [PCIe x4 in slot 7, dual SATA ports, x2 Aurora]
The flash address range is
0xe8000000 to 0xefffffff . Each flash sector is 128 KB and there are 1024
sectors for a total of 128 MB of NOR flash space.
U-Boot is 512 KB and occupies the last 4 sectors starting at
0xeff80000 going upto 0xefffffff when
SW6[1:4] = 0000 .
The flash space is further divided into 8 virtual banks. With SW6[1:4] = 0000 the mapping is as follows:
The default boot bank is U-Boot from bank 0 at
0xef000000 with SW6[1:4]= 0000 .
U-Boot is always at
0xeff80000 .
An alternate U-Boot (golden) copy is located in Bank 4 with SW6[1:4]= 0100 .
The default FMan microcode location:
0xeff40000
On board NOR flash is loaded with complete NOR flash image files:
• rcw_1_28_6_12_1666MHz.bin
• fsl_fman_ucode_B4860_106_3_4.bin
• u-boot.bin
Table 6-4. Virtual banks
Banks Description
Bank7 e8000000 - e8ffffff
Bank6 e9000000 - e9ffffff
Bank5 ea000000 - eaffffff
Bank4 eb000000 - ebffffff
Bank3 ec000000 - ecffffff
Bank2 ed000000 - edffffff
Bank1 ee000000 - eeffffff
Bank0 ef000000 - efffffff

QorIQ T4240 Development System Quick Start, Rev.1
Freescale Semiconductor 19
Revision history
•uImage
• fsl-image-core-p5040ds-64b-20120615114727.rootfs.ext2.gz.u-boot
• t4240qds.dtb
NOTE
The NOR flash images are in QorIQ Linux SDK v1.8 e6500 Images ISO
file, which is shipped with the QDS board and available on:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=SDK
LINUX&fpsp=1&tab=Design_Tools_Tab
7 Revision history
The following table provides a revision history for this document.
Table 5. Document Revision History
Rev.
number Date Substantive change(s)
1 7 Oct 2015 T4240QDS Quick Start, Rev 1 release.
• Updated Section 4.3, “Switch settings
• Updated Section 4.3.1, “Default switch settings
• Updated U-Boot log in Section 5, “Starting up and booting system
• Updated Section 6, “Pre-loaded RCW and boot flash information
• Removed Chapter 7 “Connecting a 750W Power Supply“
• Moved Chapter 8 “Configuring T4240 QDS in Chassis” to Section 4.2
0 1 June 2013 T4240QDS Quick Start Guide Rev 0 release.

Document Number: T4240QDSQSG
Rev.1
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