Fujitsu F2MC-8L Series User manual

The following document contains information on Cypress products.

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
F2MC-8L
8-BIT MICROCONTROLLER
MB89120/120A SERIES
HARDWARE MANUAL
CM25-10111-3E

FUJITSU LIMITED
F2MC-8L
8-BIT MICROCONTROLLER
MB89120/120A SERIES
HARDWARE MANUAL

i
PREFACE
■Objective and Intended Readership
MB89120/120A Series was developed as one of the general purpose versions of the F2MC-8L
Series, which is a proprietary 8-bit single-chip microcontroller that supports application-specific
ICs (ASICs). MB89120/120A Series have a wide range of uses from portable phones to
consumer electric appliances and industrial equipment.
This manual, which is intended for engineers designing products using these MB89120/120A
Series Microcontollers, explains the functions and operations of theMB89120/120A Series. For
details on the instructions, refer to the F2MC(R)-8L MB89600 Series Programming Manual.
Trademarks
F2MC(R) is an acronym for Fujitsu Flexible Microcontroller and is a registered trademark of
Fujitsu Limited.
■Structure of This Manual
This manual consists of the following 14 chapters:
Chapter 1 Overview
This chapter describes the features and basic specifications of the MB89120/120A Series.
Chapter 2 Handling Devices
This chapter describes important points when using the MB89120/120A Series.
Chapter 3 CPU
This chapter describes the functions of CPU of the MB89120/120A Series.
Chapter 4 I/O Ports
This chapter describes the functions and operation of the I/O ports of the MB89120/120A
Series.
Chapter 5 Timebase Timer
This chapter describes the functions and operation of the timebase timer of the MB89120/
120A Series.
Chapter 6 Watchdog Timer
This chapter describes the functions and operation of the watchdog timer of the MB89120/
120A Series.
Chapter 7 8/16-Bit Timer/Counter
This chapter describes the functions and operation of the 8/16-bit timer/counter of the
MB89120/120A Series.
Chapter 8 8-Bit Serial I/O
This chapter describes the functions and operation the 8-bit serial I/O of the MB89120/120A
Series.
Chapter 9 Buzzer Output
This chapter describes the functions and operation of the buzzer output of the MB89120/
120A Series.

ii
Chapter 10 External Interrupt Circuit 1 (Edge)
This chapter describes the functions and operation of the external interrupt circuit 1 (edge) of
the MB89120/120A Series.
Chapter 11 External Interrupt Circuit 2 (Level)
This chapter describes the functions and operation of the external interrupt circuit 2 (Level)
of the MB89120/120A Series.
Chapter 12 Watch Prescaler
This chapter describes the functions and operation of the watch prescaler of the MB89120/
120A Series.
Chapter 13 Remote-Control Transmission Frequency Generator
This chapter describes the functions and operation of the remote-control transmission
frequency generator of the MB89120/120A Series.
Chapter 14 Peripheral Control Clock Output
This chapter describes the functions and operation of the peripheral control clock output of
the MB89120/120A Series.
In addition, I/O Map, Mask Options, Overview of Instructions, Instruction List, and Instruction
Map are described in the Appendixes.

iii
©2000 FUJITSU LIMITED Printed in Japan
1. The contents of this document are subject to change without notice. Customers are advised to consult
with FUJITSU sales representatives before ordering.
2. The information and circuit diagrams in this document are presented as examples of semiconductor
device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is
unable to assume responsibility for infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
3. The contents of this document may not be reproduced or copied without the permission of FUJITSU
LIMITED.
4. FUJITSU semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipments, industrial, communications, and measurement equipments,
personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls,
sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to
consult with FUJITSU sales representatives before such use. The company will not be responsible for
damages arising from such use without prior approval.
5. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions.
6. If any products described in this document represent goods or technologies subject to certain
restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior
authorization by Japanese government should be required for export of those products from Japan.

iv
READING THIS MANUAL
■Page Layout
Each section is organized on a page or on facing pages so that the contents of each section can
be viewed without turning pages.
The contents of each section are summarized immediately below the title. A rough overview of
this product can be obtained by reading through these summaries.
Also, higher level section headings are provided in lower sections to ensure that the user will
know to which section the text currently being read belongs without referring to the table of
contents or the cover of each chapter.
■How to search information
The following methods, other than using the table of contents or index, are also available for
searching reference information as necessary.
❍Register index
By using the register index, information can be searched with a register name, a bit name, or
abbreviations of these names.
❍Subtitle index
A subtitle index, whose subtitles included in each section are extracted, is provided to ensure
the provision of more detailed reference information than that provided in the contents.
■Example of description of register name and terminal name
❍Example of description of register name and bit name
By writing "1" in the sleep bit (STBC:SLP) of the standby control register....
Bit name
Register name
Register abbreviation
Bit abbreviation
Disable (TBTC:TBIE=0) the interrupt request output of the timebase timer.
Set data
Bit abbreviation
Register abbreviation

v
❍Example of a description of a shared terminal
P25/SCK terminal
Some terminals can share several functions by switching in the program setting. The
function names of shared terminal are separated by "/."
Interrupt is accepted when interrupt is enabled (CCR:I=1).
Current status
Bit abbreviation
Register abbreviation

vi
■Structure of facing pages and description rules of this manual
Chapter title
Summary of the section
Section title
ubtitle
igure title
Upper section
Reference :
Indicates the manual or item to be referenced.
Tip :
Describes helpful and convenient information.
Check :
Indicates items to be noted.
Read carefully.
Table title

vii
■Materials required for development and development tools
The following items are required for developing our product.
For the required materials and development tools, contact a Fujitsu salesperson.
❍Required manuals for development
Check column
The manual with * mark is provided with each product.
Additional manuals for development tools are provided with corresponding products.
❍Software product required for development
Check column
The type of software is dependent on the OS used.
For details, refer to the development tool catalog or the product guide of the F2MC.
F2MC-8L MB89120/120A series Datasheet
(Describes electrical characteristics and examples of our products.)
F2MC-8L MB89600 series Programming manual
(Manual for instructions of F2MC-8L series)
*F
2MC-8L MB89600 series C compiler manual
(Required only for developing with C language)
(Manual for program development and activation of C language)
*F
2MC-8L MB89600 series Assembler manual
(Manual for program development of assembly language)
*F
2MC-8L MB89600 series Support system manual
(Manual for activation of macro assembler, linker, and library manager)
*F
2MC-8L MB89600 series Software simulator manual
(Required only for evaluating by simulator)
(Manual for operation of software simulator)
C compiler (Required only for developing with C language)
Assembler, linker, librarian
Software simulator (Required only for evaluating by simulator)
Emulator debugger (Required only for evaluating by MB2140A series)

viii
❍Required items for evaluating one-time PROM and EPROM microcomputer (When writing
by the user)
Check column
❍Development tool
Check column
To use another manufacturer’s development product, check with the corresponding
manufacturer.
❍Reference materials
•F
2MC development tool catalog
• Microcomputer product guide
MB89P131, MB89P133A, or MB89P135A
ROM writer
(a writer that can be used for writing MBM27C256A)
Refer to the datasheet for the recommended writer.
Package conversion adopter for writing (Purchase from Sunhayato
Corporation)
Package Socket product number
FPT-48P-M13 (0.08 MM pitch) ROM-48QF2-28DP-8L
MB89PV130 (piggy/evaluation chip)
Evaluation tool
MB2141A + MB2144-505 + MB2144-203
(Main unit) (Pod) (Probe head)

ix
CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 MB89120/120A Series Features ............................................................................................................ 2
1.2 MB89120/120A Series Product Lineup .................................................................................................. 4
1.3 Differences among Products ................................................................................................................. 6
1.4 MB89120/120A Series Block Diagram .................................................................................................. 8
1.5 Pin Assignment ...................................................................................................................................... 9
1.6 Package Dimensions ........................................................................................................................... 12
1.7 Pin Functions ....................................................................................................................................... 15
1.8 I/O Circuit Types .................................................................................................................................. 18
CHAPTER 2 HANDLING DEVICES ................................................................................. 21
2.1 Notes on Handling Devices ................................................................................................................. 22
CHAPTER 3 CPU ............................................................................................................. 25
3.1 Memory Space ..................................................................................................................................... 26
3.1.1 Special Areas ................................................................................................................................. 28
3.1.2 Storing 16-bit Data in Memory ........................................................................................................ 30
3.2 Dedicated Registers ............................................................................................................................ 32
3.2.1 Condition Code Register (CCR) ..................................................................................................... 34
3.2.2 Register Bank Pointer (RP) ............................................................................................................ 37
3.3 General-Purpose Registers ................................................................................................................. 38
3.4 Interrupts ............................................................................................................................................. 40
3.4.1 Interrupt Level Setting Registers (ILR1, ILR2, ILR3) ...................................................................... 42
3.4.2 Interrupt Processing ....................................................................................................................... 44
3.4.3 Multiple Interrupts ........................................................................................................................... 47
3.4.4 Interrupt Processing Time .............................................................................................................. 49
3.4.5 Stack Operation during Interrupt Processing .................................................................................. 51
3.4.6 Stack Area for Interrupt Processing ................................................................................................ 52
3.5 Resets ................................................................................................................................................. 53
3.5.1 External Reset Pin .......................................................................................................................... 55
3.5.2 Reset Operation ............................................................................................................................. 56
3.5.3 Pin States During Reset ................................................................................................................. 58
3.6 Clocks .................................................................................................................................................. 59
3.6.1 Clock Generator ............................................................................................................................. 61
3.6.2 Clock Controller .............................................................................................................................. 63
3.6.3 System Clock Control Register (SYCC) ......................................................................................... 65
3.6.4 Clock Modes ................................................................................................................................... 68
3.6.5 Oscillation Stabilization Delay Time ............................................................................................... 71
3.7 Standby Modes (Low-power Consumption) ......................................................................................... 73
3.7.1 Standby Mode Operating States .................................................................................................... 75
3.7.2 Sleep Mode .................................................................................................................................... 77
3.7.3 Stop Mode ...................................................................................................................................... 78
3.7.4 Watch Mode ................................................................................................................................... 80
3.7.5 Standby Control Register (STBC) .................................................................................................. 81

x
3.7.6 State Transition Diagram 1 (Product with Power-on Reset Function in Dual-clock Configuration) 83
3.7.7 State Transition Diagram 2 (Product without Power-on Reset Function in Dual-clock
Configuration) ................................................................................................................................ 86
3.7.8 State Transition Diagram 3 (Products in Single-clock Configuration) ............................................ 89
3.7.9 Pin States in Standby Modes ......................................................................................................... 91
3.7.10 Notes on Using Standby Modes .................................................................................................... 93
3.8 Memory Access Modes ....................................................................................................................... 95
CHAPTER 4 I/O PORTS .................................................................................................. 97
4.1 Overview of I/O Ports .......................................................................................................................... 98
4.2 Port 0 ................................................................................................................................................ 100
4.2.1 Port 0 Registers (PDR0, DDR0) .................................................................................................. 103
4.2.2 Operation of Port 0 ...................................................................................................................... 105
4.3 Port 1 ................................................................................................................................................ 107
4.3.1 Port 1 Registers (PDR1, DDR1) .................................................................................................. 109
4.3.2 Operation of Port 1 ...................................................................................................................... 111
4.4 Port 2 ................................................................................................................................................ 113
4.4.1 Port 2 Register (PDR2) ................................................................................................................ 115
4.4.2 Operation of Port 2 ...................................................................................................................... 116
4.5 Port 3 ................................................................................................................................................ 117
4.5.1 Port 3 Registers (PDR3, DDR3) .................................................................................................. 120
4.5.2 Operation of Port 3 ...................................................................................................................... 122
4.6 Port 4 ................................................................................................................................................ 124
4.6.1 Port 4 Register (PDR4) ................................................................................................................ 126
4.6.2 Operation of Port 4 ...................................................................................................................... 127
4.7 Program Example for I/O Ports ......................................................................................................... 128
CHAPTER 5 TIMEBASE TIMER .................................................................................... 131
5.1 Overview of Timebase Timer ............................................................................................................ 132
5.2 Structure of Timebase Timer ............................................................................................................ 134
5.3 Timebase Timer Control Register (TBTC) ........................................................................................ 136
5.4 Timebase Timer Interrupt .................................................................................................................. 138
5.5 Operation of Timebase Timer ........................................................................................................... 139
5.6 Notes on Using Timebase Timer ...................................................................................................... 141
5.7 Program Example for Timebase Timer ............................................................................................. 143
CHAPTER 6 WATCHDOG TIMER ................................................................................. 145
6.1 Overview of Watchdog Timer ............................................................................................................ 146
6.2 Structure of Watchdog Timer ............................................................................................................ 147
6.3 Watchdog Timer Control Register (WDTC) ...................................................................................... 149
6.4 Operation of Watchdog Timer ........................................................................................................... 151
6.5 Notes on Using Watchdog Timer ...................................................................................................... 153
6.6 Program Example for Watchdog Timer ............................................................................................. 154
CHAPTER 7 8/16-BIT TIMER/COUNTER ...................................................................... 157
7.1 Overview of 8/16-bit Timer/Counter .................................................................................................. 158
7.2 Structure of 8/16-bit Timer/Counter .................................................................................................. 161
7.3 8/16-bit Timer/Counter Pins .............................................................................................................. 163

xi
7.4 8/16-bit Timer/Counter Registers ....................................................................................................... 165
7.4.1 Timer Control 1 Register (T1CR) .................................................................................................. 166
7.4.2 Timer Control 2 Register (T2CR) .................................................................................................. 169
7.4.3 Timer 1 Data Register (T1DR) ...................................................................................................... 171
7.4.4 Timer 2 Data Register (T2DR) ...................................................................................................... 173
7.5 8/16-bit Timer/Counter Interrupts ....................................................................................................... 175
7.6 Operation of Interval Timer Function ................................................................................................. 177
7.7 Operation of Counter Function .......................................................................................................... 179
7.8 Operation of Square Wave Output Initialization Function .................................................................. 182
7.9 Stop and Restart Operations of 8/16-bit Timer/Counter .................................................................... 184
7.10 States in Each Mode during 8/16-bit Timer/Counter Operation ......................................................... 185
7.11 Notes on Using 8/16-bit Timer/Counter ............................................................................................. 187
7.12 Program Examples for 8/16-bit Timer/Counter .................................................................................. 189
CHAPTER 8 8-BIT SERIAL I/O ...................................................................................... 193
8.1 Overview of 8-bit Serial I/O ................................................................................................................ 194
8.2 Structare of 8-bit Serial I/O ................................................................................................................ 195
8.3 8-bit Serial I/O Pins ............................................................................................................................ 197
8.4 8-bit Serial I/O Registers .................................................................................................................... 199
8.4.1 Serial Mode Register (SMR) ......................................................................................................... 200
8.4.2 Serial Data Register (SDR) .......................................................................................................... 203
8.5 8-bit Serial I/O Interrupts .................................................................................................................... 204
8.6 Operation of Serial Output ................................................................................................................. 205
8.7 Operation of Serial Input .................................................................................................................... 207
8.8 States in Each Mode during 8-bit Serial I/O Operation ...................................................................... 209
8.9 Notes on Using 8-bit Serial I/O .......................................................................................................... 212
8.10 Connection Example for 8-bit Serial I/O ............................................................................................ 213
8.11 Program Examples for 8-bit Serial I/O ............................................................................................... 215
CHAPTER 9 BUZZER OUTPUT .................................................................................... 219
9.1 Overview of Buzzer Output ................................................................................................................ 220
9.2 Structure of Buzzer Output ................................................................................................................ 222
9.3 Buzzer Output Pin .............................................................................................................................. 223
9.4 Buzzer Output Register ..................................................................................................................... 224
9.4.1 Buzzer Register (BZCR) ............................................................................................................... 225
9.5 Program Example for Buzzer Output ................................................................................................. 227
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) .......................................... 229
10.1 Overview of External Interrupt Circuit 1 (Edge) ................................................................................ 230
10.2 Structure of External Interrupt Circuit 1 ............................................................................................. 231
10.3 External Interrupt Circuit 1 Pins ......................................................................................................... 233
10.4 External Interrupt Circuit 1 Registers ................................................................................................. 235
10.4.1 External Interrupt 1 Control Register 1 (EIC1) .............................................................................. 236
10.4.2 External Interrupt 1 Control Register 2 (EIC2) .............................................................................. 238
10.5 External Interrupt Circuit 1 Interrupts ................................................................................................. 240
10.6 Operation of External Interrupt Circuit 1 ............................................................................................ 241
10.7 Program Example for External Interrupt Circuit 1 .............................................................................. 243

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CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) ........................................ 245
11.1 Overview of External Interrupt Circuit 2 (Level) ............................................................................... 246
11.2 Structure of External Interrupt Circuit 2 ............................................................................................. 247
11.3 External Interrupt Circuit 2 Pins ........................................................................................................ 249
11.4 External Interrupt Circuit 2 Registers ................................................................................................ 251
11.4.1 External Interrupt 2 Control Register (EIC2) ................................................................................ 252
11.4.2 External Interrupt 2 Flag Register (EIF2) ..................................................................................... 254
11.5 External Interrupt Circuit 2 Interrupts ................................................................................................ 255
11.6 Operation of External Interrupt Circuit 2 ........................................................................................... 256
11.7 Program Example for External Interrupt Circuit 2 ............................................................................. 258
CHAPTER 12 WATCH PRESCALER .............................................................................. 261
12.1 Overview of Watch Prescaler ............................................................................................................ 262
12.2 Structure of Watch Prescaler ............................................................................................................ 264
12.3 Watch Prescaler Control Register (WPCR) ...................................................................................... 266
12.4 Watch Prescaler Interrupts ............................................................................................................... 268
12.5 Operation of Watch Prescaler ........................................................................................................... 269
12.6 Notes on Using Watch Prescaler ...................................................................................................... 271
12.7 Program Example for Watch Prescaler ............................................................................................. 273
CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR .... 275
13.1 Overview of Remote-control Transmission Frequency Generator .................................................... 276
13.2 Structure of Remote-control Transmission Frequency Generator .................................................... 281
13.3 Remote-control Transmission Frequency Generator Pin .................................................................. 283
13.4 Remote-control Transmission Frequency Generator Registers ........................................................ 284
13.4.1 Remote-control Transmission Frequency Control Register 1 (RCR1) ......................................... 285
13.4.2 Remote-control Transmission Frequency Control Register 2 (RCR2) ......................................... 287
13.5 Operation of Remote-control Transmission Frequency Generator ................................................... 289
13.6 Notes on Using Remote-control Transmission Frequency Generator .............................................. 291
13.7 Program Example for Remote-control Transmission Frequency Generator ..................................... 294
CHAPTER 14 PERIPHERAL CONTROL CLOCK OUTPUT ........................................... 295
14.1 Overview of Peripheral Control Clock Output ................................................................................... 296
14.2 Structure of Peripheral Control Clock Output .................................................................................... 297
14.3 Peripheral Control Clock Output Pin ................................................................................................. 298
14.3.1 Peripheral Control Clock Register (SCGC) .................................................................................. 299
14.4 Program Example for Peripheral Control Clock Output .................................................................... 301
APPENDIX .......................................................................................................................... 303
APPENDIX A I/O Map ............................................................................................................................. 304
APPENDIX B Overview of Instructions .................................................................................................... 307
B.1 Addressing ..................................................................................................................................... 309
B.2 Special Instructions ........................................................................................................................ 313
B.3 Bit Manipulation Instructions (SETB, CLRB) .................................................................................. 317
B.4 F2MC-8L Instructions ..................................................................................................................... 318
B.5 Instruction Map ............................................................................................................................... 324
APPENDIX C Mask Options .................................................................................................................... 326
APPENDIX D Programming PROM ......................................................................................................... 328

xiii
D.1 Programming One-time PROM ....................................................................................................... 329
D.2 Programming EPROM with Piggyback/Evaluation Device .............................................................. 334
APPENDIX E MB89120 Series Pin States ............................................................................................... 336
INDEX ................................................................................................................................. 339

xiv
FIGURES
Figure 1.4-1 MB89120/120A Series Block Diagram ....................................................................................... 8
Figure 1.5-1 FTP-48P-M13 Pin Assignment ................................................................................................... 9
Figure 1.5-2 DIP-48P-M01 Pin Assignment .................................................................................................. 10
Figure 1.5-3 MQP-48C-P01 Pin Assignment ................................................................................................ 11
Figure 1.6-1 FPT-48P-M13 Package Dimensions ........................................................................................ 12
Figure 1.6-2 DIP-48P-M01 Package Dimensions ......................................................................................... 13
Figure 1.6-3 MQP-48C-P01 Package Dimensions ....................................................................................... 14
Figure 3.1-1 Memory Map ............................................................................................................................. 27
Figure 3.1-2 Allocation 16-bit Data in Memory .............................................................................................. 30
Figure 3.1-3 Allocation of 16-bit Data in an Instruction ................................................................................. 30
Figure 3.2-1 Dedicated Register Configuration ............................................................................................. 32
Figure 3.2-2 Structure of Condition Code Register ....................................................................................... 34
Figure 3.2-3 Change of Carry Flag by Shift Instruction ................................................................................. 35
Figure 3.2-4 Structure of Register Bank Pointer ........................................................................................... 37
Figure 3.2-5 Rule for Conversion of Actual Addresses of General-purpose Register Area .......................... 37
Figure 3.3-1 Register Bank Structure ............................................................................................................ 38
Figure 3.4-1 Structure of Interrupt Level Setting Registers ........................................................................... 42
Figure 3.4-2 Interrupt Processing .................................................................................................................. 45
Figure 3.4-3 Example of Multiple Interrupts .................................................................................................. 47
Figure 3.4-4 Interrupt Processing Time ......................................................................................................... 49
Figure 3.4-5 Stack Operation at Start of Interrupt Processing ...................................................................... 51
Figure 3.4-6 Stack Area for Interrupt Processing .......................................................................................... 52
Figure 3.5-1 Block Diagram of External Reset Pin ........................................................................................ 55
Figure 3.5-2 Reset Operation Flowchart ....................................................................................................... 56
Figure 3.6-1 Clock Supply Map ..................................................................................................................... 60
Figure 3.6-2 Connection Example for Crystal or Ceramic Resonator ........................................................... 61
Figure 3.6-3 Connection Example for External Clock ................................................................................... 62
Figure 3.6-4 Block Diagram of Clock Controller ............................................................................................ 63
Figure 3.6-5 System Clock Control Register (SYCC) ................................................................................... 65
Figure 3.6-6 Operation of an Oscillator after Starting Oscillation .................................................................. 71
Figure 3.7-1 Standby Control Register (STBC) ............................................................................................. 81
Figure 3.7-2 State Transition Diagram 1 (Product with Power-on Reset Function in
Dual-clock Configuration) ......................................................................................................... 83
Figure 3.7-3 State Transition Diagram 2 (Product without Power-on Reset Function in
Dual-clock Configuration) ......................................................................................................... 86

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Figure 3.7-4 State Transition Diagram 3 (Product with Power-on Reset Function) ....................................... 89
Figure 3.7-5 State Transition Diagram 3 (Product without Power-on Reset Function) .................................. 89
Figure 3.8-1 Mode Data Structure ................................................................................................................. 95
Figure 3.8-2 Memory Access Selection Operation ........................................................................................ 96
Figure 4.2-1 Block Diagram of Port 0 Pin ................................................................................................... 102
Figure 4.3-1 Block Diagram of Port 1 Pin .................................................................................................... 108
Figure 4.4-1 Block Diagram of Port 2 Pin .................................................................................................... 114
Figure 4.5-1 Block Diagram of Port 3 Pins (P30 to P32, P34 to P36) .......................................................... 118
Figure 4.5-2 Block Diagram of Port 3 Pins (P33, P37) ................................................................................ 118
Figure 4.6-1 Block Diagram of Port 4 Pin .................................................................................................... 125
Figure 4.7-1 Connection Example for an Eight-Segment LED .................................................................... 128
Figure 5.2-1 Block Diagram of Timebase Timer .......................................................................................... 134
Figure 5.3-1 Timebase Timer Control Register (TBTC) ............................................................................... 136
Figure 5.5-1 Interval Timer Function Settings .............................................................................................. 139
Figure 5.5-2 Timebase Timer Operation ...................................................................................................... 140
Figure 5.6-1 Effect on Buzzer Output of Clearing Timebase Timer ............................................................. 142
Figure 6.2-1 Block Diagram of Watchdog Timer .......................................................................................... 147
Figure 6.3-1 Watchdog Timer Control Register (WDTC) ............................................................................. 149
Figure 6.4-1 Watchdog Timer Clear and Interval Time ................................................................................ 152
Figure 7.2-1 Block Diagram of 8/16-bit Timer/Counter ................................................................................ 161
Figure 7.3-1 Block Diagram of 8/16-bit Timer/Counter Pin (P33/EC/SCO) ................................................. 164
Figure 7.3-2 Block Diagram of 8/16-bit Timer/Counter Pin (P34/TO/INT0) ................................................. 164
Figure 7.4-1 8/16-bit Timer/Counter Registers ............................................................................................ 165
Figure 7.4-2 Timer 1 Control Register (T1CR) ............................................................................................. 166
Figure 7.4-3 Timer 2 Control Register (T2CR) ............................................................................................. 169
Figure 7.4-4 Timer 1 Data Register (T1DR) ................................................................................................. 171
Figure 7.4-5 Timer 2 Data Register (T2DR) ................................................................................................. 173
Figure 7.6-1 Settings for Interval Timer Function (Timer 1) ......................................................................... 177
Figure 7.6-2 Settings for Interval Timer Function (Timer 2) ......................................................................... 177
Figure 7.6-3 Operation of Interval Timer Function (Timer 1) in 8-bit Mode .................................................. 178
Figure 7.6-4 Settings for Interval Timer Function (in 16-bit Mode) .............................................................. 178
Figure 7.7-1 Settings for Counter Function (in 8-bit Mode) .......................................................................... 179
Figure 7.7-2 Settings for Counter Function (in 16-bit Mode) ........................................................................ 180
Figure 7.7-3 Operation of Counter Functions in 16-bit Mode ....................................................................... 181
Figure 7.8-1 Initialization Equivalent Circuit for Square Wave Output ......................................................... 182
Figure 7.8-2 Initial setup operation of the square wave output .................................................................... 183
Figure 7.10-1 Counter Operation during Subclock or Standby Modes and Operation Halt ........................... 186
Figure 7.11-1 Operation When Timer Stop Bit is Used .................................................................................. 187