GigaDevice Semiconductor GD32A50 Series User manual

GigaDevice Semiconductor Inc.
GD32A50x
Arm® Cortex®-M33 32-bit MCU
User Manual
Revision 1.0
(Sep. 2022)

GD32A50x User Manual
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Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................16
List of Tables ................................................................................................................22
1. System and memory architecture ........................................................................25
1.1. Arm®Cortex®-M33 processor....................................................................................... 25
1.2. System architecture....................................................................................................... 26
1.3. Memory map................................................................................................................... 28
1.3.1. On-chip SRAM memory........................................................................................................ 32
1.3.2. On-chip Flash memory ......................................................................................................... 34
1.4. Boot configuration......................................................................................................... 34
1.5. System configuration controller .................................................................................. 35
1.6. System configuration registers.................................................................................... 36
1.6.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 36
1.6.2. System configuration register 1 (SYSCFG_CFG1) .............................................................. 37
1.6.3. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 37
1.6.4. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 39
1.6.5. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 40
1.6.6. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 41
1.6.7. System configuration register 2 (SYSCFG_CFG2) .............................................................. 42
1.6.8. System status register (SYSCFG_STAT) ............................................................................. 43
1.6.9. System configuration register 3 (SYSCFG_CFG3) .............................................................. 44
1.6.10. TIMER input source select register (SYSCFG_TIMERINSEL) ............................................ 45
1.7. Device electronic signature.......................................................................................... 47
1.7.1. Memory density information.................................................................................................. 48
1.7.2. Unique device ID (96 bits) .................................................................................................... 48
2. Flash memory controller (FMC)............................................................................50
2.1. Overview ......................................................................................................................... 50
2.2. Characteristics............................................................................................................... 50
2.3. Function overview.......................................................................................................... 50
2.3.1. Flash memory architecture ................................................................................................... 50
2.3.2. Error Checking and Correcting (ECC) .................................................................................. 54
2.3.3. Read operations ................................................................................................................... 55
2.3.4. Dual bank architecture with read-while-write (RWW) capability ........................................... 56
2.3.5. Unlock the FMC_CTLx register ............................................................................................ 56
2.3.6. Page erase............................................................................................................................ 57

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2.3.7. Mass erase ........................................................................................................................... 58
2.3.8. Main flash programming ....................................................................................................... 59
2.3.9. Main Flash Fast Programming.............................................................................................. 61
2.3.10. Check blank command ......................................................................................................... 64
2.3.11. OTP programming ................................................................................................................ 64
2.3.12. Shared RAM ......................................................................................................................... 64
2.3.13. Data Flash operation ............................................................................................................ 65
2.3.14. Emulated EEPROM .............................................................................................................. 65
2.3.15. Option bytes 0 erase............................................................................................................. 66
2.3.16. Option bytes programming ................................................................................................... 67
2.3.17. Option bytes description ....................................................................................................... 68
2.3.18. erase / program protection.................................................................................................... 73
2.3.19. Security protection ................................................................................................................ 76
2.3.20. Error description.................................................................................................................... 76
2.4. Register definition.......................................................................................................... 79
2.4.1. Wait state register (FMC_WS).............................................................................................. 79
2.4.2. ECC control and status register (FMC_ECCCS).................................................................. 80
2.4.3. Unlock key register 0 (FMC_KEY0)...................................................................................... 82
2.4.4. Status register 0 (FMC_STAT0)............................................................................................ 82
2.4.5. Control register 0 (FMC_CTL0) ............................................................................................ 83
2.4.6. Address register 0 (FMC_ADDR0) ....................................................................................... 85
2.4.7. Option byte unlock key register (FMC_OBKEY)................................................................... 85
2.4.8. Unlock key register 1 (FMC_KEY1)...................................................................................... 86
2.4.9. Status register 1 (FMC_STAT1)............................................................................................ 86
2.4.10. Control register 1 (FMC_CTL1) ............................................................................................ 87
2.4.11. Address register 1 (FMC_ADDR1) ....................................................................................... 89
2.4.12. EEPROM counter register (FMC_EPCNT)........................................................................... 89
2.4.13. Option byte status register (FMC_OBSTAT)......................................................................... 90
2.4.14. Erase / Program protection register 0 (FMC_WP0).............................................................. 90
2.4.15. Erase / Program protection register 1 (FMC_WP1).............................................................. 91
2.4.16. Option byte 1 control and status register (FMC_OB1CS) .................................................... 91
2.4.17. Product ID register (FMC_PID)............................................................................................. 92
3. Power management unit (PMU) ............................................................................94
3.1. Overview ......................................................................................................................... 94
3.2. Characteristics ............................................................................................................... 94
3.3. Function overview.......................................................................................................... 94
3.3.1. Backup domain ..................................................................................................................... 95
3.3.2. VDD / VDDA power domain ...................................................................................................... 96
3.3.3. 1.1V power domain............................................................................................................... 99
3.3.4. Power saving modes ............................................................................................................ 99
3.4. Register definition........................................................................................................ 102

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3.4.1. Control register (PMU_CTL) ............................................................................................... 102
3.4.2. Control and status register (PMU_CS) ............................................................................... 103
4. Backup registers (BKP).......................................................................................106
4.1. Overview ....................................................................................................................... 106
4.2. Characteristics ............................................................................................................. 106
4.3. Function overview........................................................................................................ 106
4.3.1. RTC clock calibration .......................................................................................................... 106
4.3.2. Tamper detection ................................................................................................................ 106
4.4. Register definition........................................................................................................ 108
4.4.1. Backup data register x (BKP_DATAx) (x= 0..9) .................................................................. 108
4.4.2. RTC signal output control register (BKP_OCTL)................................................................ 108
4.4.3. Tamper pin control register (BKP_TPCTL) ......................................................................... 109
4.4.4. Tamper control and status register (BKP_TPCS) ................................................................110
5. Reset and clock unit (RCU)................................................................................. 112
5.1. Reset control unit (RCTL) ........................................................................................... 112
5.1.1. Overview ..............................................................................................................................112
5.1.2. Function overview ................................................................................................................112
5.2. Clock control unit (CCTL) ........................................................................................... 113
5.2.1. Overview ..............................................................................................................................113
5.2.2. Characteristics .....................................................................................................................115
5.2.3. Function overview ................................................................................................................115
5.3. Register definition........................................................................................................ 120
5.3.1. Control register (RCU_CTL) ............................................................................................... 120
5.3.2. Configuration register 0 (RCU_CFG0) ............................................................................... 122
5.3.3. Interrupt register (RCU_INT) .............................................................................................. 125
5.3.4. APB2 reset register (RCU_APB2RST) ............................................................................... 128
5.3.5. APB1 reset register (RCU_APB1RST) ............................................................................... 130
5.3.6. AHB enable register (RCU_AHBEN) .................................................................................. 132
5.3.7. APB2 enable register (RCU_APB2EN) .............................................................................. 133
5.3.8. APB1 enable register (RCU_APB1EN) .............................................................................. 135
5.3.9. Backup domain control register (RCU_BDCTL) ................................................................. 137
5.3.10. Reset source /clock register (RCU_RSTSCK) ................................................................... 138
5.3.11. AHB reset register (RCU_AHBRST)................................................................................... 141
5.3.12. Configuration register 1 (RCU_CFG1) ............................................................................... 143
5.3.13. Configuration register 2 (RCU_CFG2) ............................................................................... 144
5.3.14. Voltage key register (RCU_VKEY) ..................................................................................... 145
5.3.15. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 146
6. Interrupt/event controller (EXTI).........................................................................147
6.1. Overview ....................................................................................................................... 147

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6.2. Characteristics ............................................................................................................. 147
6.3. Interrupts function overview ...................................................................................... 147
6.4. External interrupt and event (EXTI) block diagram.................................................. 151
6.5. External Interrupt and Event function overview ...................................................... 151
6.6. Register definition........................................................................................................ 153
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 153
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 153
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 154
6.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 154
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 154
6.6.6. Pending register (EXTI_PD) ............................................................................................... 155
7. Trigger selection controller (TRIGSEL)..............................................................156
7.1. Overview ....................................................................................................................... 156
7.2. Characteristics ............................................................................................................. 156
7.3. Function overview........................................................................................................ 156
7.4. Internal connect ........................................................................................................... 157
7.5. Register definition........................................................................................................ 162
7.5.1. Trigger selection for EXTOUT0 register (TRIGSEL_EXTOUT0) ........................................ 162
7.5.2. Trigger selection for EXTOUT1 register (TRIGSEL_EXTOUT1) ........................................ 163
7.5.3. Trigger selection for ADC0 register (TRIGSEL_ADC0) ...................................................... 164
7.5.4. Trigger selection for ADC1 register (TRIGSEL_ADC1) ...................................................... 164
7.5.5. Trigger selection for DAC register (TRIGSEL_DAC) .......................................................... 165
7.5.6. Trigger selection for TIMER0_ITI register (TRIGSEL_TIMER0IN) ..................................... 165
7.5.7. Trigger selection for TIMER0_BRKIN register (TRIGSEL_TIMER0BRKIN) ...................... 166
7.5.8. Trigger selection for TIMER7_ITI register (TRIGSEL_TIMER7IN) ..................................... 167
7.5.9. Trigger selection for TIMER7_BRKIN register (TRIGSEL_TIMER7BRKIN) ...................... 168
7.5.10. Trigger selection for TIMER19_ITI register (TRIGSEL_TIMER19IN)................................. 169
7.5.11. Trigger selection for TIMER19_BRKIN register (TRIGSEL_TIMER19BRKIN) .................. 170
7.5.12. Trigger selection for TIMER20_ITI register (TRIGSEL_TIMER20IN)................................. 171
7.5.13. Trigger selection for TIMER20_BRKIN register (TRIGSEL_TIMER20BRKIN) .................. 172
7.5.14. Trigger selection for TIMER1_ITI register (TRIGSEL_TIMER1IN) ..................................... 173
7.5.15. Trigger selection for MFCOM register (TRIGSEL_MFCOM).............................................. 174
7.5.16. Trigger selection for CAN0 register (TRIGSEL_CAN0) ...................................................... 175
7.5.17. Trigger selection for CAN1 register (TRIGSEL_CAN1) ...................................................... 176
8. General-purpose and alternate-function I/Os (GPIO and AFIO).......................177
8.1. Overview ....................................................................................................................... 177
8.2. Characteristics............................................................................................................. 177
8.3. Function overview........................................................................................................ 177

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8.3.1. GPIO pin configuration ....................................................................................................... 179
8.3.2. External interrupt/event lines .............................................................................................. 179
8.3.3. Alternate functions (AF) ...................................................................................................... 179
8.3.4. Additional functions............................................................................................................. 179
8.3.5. Input configuration .............................................................................................................. 180
8.3.6. Output configuration ........................................................................................................... 180
8.3.7. Analog configuration ........................................................................................................... 181
8.3.8. Alternate function (AF) configuration .................................................................................. 181
8.3.9. GPIO locking function ......................................................................................................... 182
8.3.10. GPIO single cycle toggle function....................................................................................... 182
8.4. Register definition........................................................................................................ 183
8.4.1. Port control register (GPIOx_CTL, x=A..F)......................................................................... 183
8.4.2. Port output mode register (GPIOx_OMODE, x=A..F)......................................................... 185
8.4.3. Port output speed register (GPIOx_OSPD, x=A..F) ........................................................... 186
8.4.4. Port pull-up/down register (GPIOx_PUD, x=A..F) .............................................................. 188
8.4.5. Port input status register (GPIOx_ISTAT, x=A..F)............................................................... 190
8.4.6. Port output control register (GPIOx_OCTL, x=A..F) ........................................................... 190
8.4.7. Port bit operate register (GPIOx_BOP, x=A..F) .................................................................. 190
8.4.8. Port configuration lock register (GPIOx_LOCK, x=A..F) .................................................... 191
8.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A..F) ....................................... 192
8.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A..F) ....................................... 193
8.4.11. Bit clear register (GPIOx_BC, x=A..F) ................................................................................ 194
8.4.12. Port bit toggle register (GPIOx_TG, x=A..F)....................................................................... 195
9. Multi-function communication Interface (MFCOM) ...........................................196
9.1. Overview ....................................................................................................................... 196
9.2. Characteristics............................................................................................................. 196
9.3. Block diagram .............................................................................................................. 196
9.4. Function overview........................................................................................................ 197
9.4.1. Clocking and resets ............................................................................................................ 197
9.4.2. Shifter.................................................................................................................................. 197
9.4.3. Timer ................................................................................................................................... 199
9.4.4. Pin....................................................................................................................................... 201
9.4.5. Interrupts and DMA requests .............................................................................................. 202
9.4.6. Triggers ............................................................................................................................... 202
9.4.7. Typical configuration of application..................................................................................... 203
9.5. Register definition........................................................................................................ 213
9.5.1. Control register (MFCOM_CTL) ......................................................................................... 213
9.5.2. Pin data register (MFCOM_PINDATA) ............................................................................... 213
9.5.3. Shifter status register (MFCOM_SSTAT)............................................................................ 214
9.5.4. Shifter error register (MFCOM_SERR)............................................................................... 214
9.5.5. Timer status register (MFCOM_TMSTAT) .......................................................................... 215

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9.5.6. Shifter status interrupt enable register (MFCOM_SSIEN).................................................. 216
9.5.7. Shifter error interrupt enable register (MFCOM_SEIEN).................................................... 216
9.5.8. Timer status interrupt enable register (MFCOM_TMSIEN) ................................................ 217
9.5.9. Shifter status DMA enable register (MFCOM_SSDMAEN) ................................................ 217
9.5.10. Shifter control x register (MFCOM_SCTLx)........................................................................ 218
9.5.11. Shifter configuration x register (MFCOM_SCFGx) ............................................................. 219
9.5.12. Shifter buffer x register (MFCOM_SBUFx) ......................................................................... 220
9.5.13. Shifter buffer x bit swapped register (MFCOM_SBUFBISx)............................................... 220
9.5.14. Shifter buffer x byte swapped register (MFCOM_SBUFBYSx) .......................................... 221
9.5.15. Shifter buffer x bit byte swapped register (MFCOM_SBUFBBSx) ..................................... 221
9.5.16. Timer control x register (MFCOM_TMCTLx) ...................................................................... 222
9.5.17. Timer configuration x register (MFCOM_TMCFGx) ........................................................... 223
9.5.18. Timer compare x register (MFCOM_TMCMPx).................................................................. 225
10. CRC calculation unit (CRC)..............................................................................227
10.1. Overview.................................................................................................................... 227
10.2. Characteristics.......................................................................................................... 227
10.3. Function overview .................................................................................................... 228
10.4. Register definition .................................................................................................... 229
10.4.1. Data register (CRC_DATA) ................................................................................................. 229
10.4.2. Free data register (CRC_FDATA) ....................................................................................... 229
10.4.3. Control register (CRC_CTL) ............................................................................................... 230
10.4.4. Initialization data register (CRC_IDATA)............................................................................. 230
10.4.5. Polynomial register (CRC_POLY)....................................................................................... 231
11. Direct memory access controller (DMA).........................................................232
11.1. Overview.................................................................................................................... 232
11.2. Characteristics.......................................................................................................... 232
11.3. Block diagram........................................................................................................... 233
11.4. Function overview.................................................................................................... 233
11.4.1. DMA operation .................................................................................................................... 233
11.4.2. Peripheral handshake......................................................................................................... 235
11.4.3. Arbitration............................................................................................................................ 235
11.4.4. Address generation............................................................................................................. 236
11.4.5. Circular mode...................................................................................................................... 236
11.4.6. Memory to memory mode................................................................................................... 236
11.4.7. Channel configuration ......................................................................................................... 236
11.4.8. Interrupt............................................................................................................................... 237
11.4.9. DMA request mapping ........................................................................................................ 238
11.5. Register definition.................................................................................................... 239
11.5.1. Interrupt flag register (DMA_INTF) ..................................................................................... 239
11.5.2. Interrupt flag clear register (DMA_INTC) ............................................................................ 240

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11.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 240
11.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 242
11.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ...................................... 243
11.5.6. Channel x memory base address register (DMA_CHxMADDR) ........................................ 243
12. DMA request multiplexer (DMAMUX) ..............................................................245
12.1. Overview.................................................................................................................... 245
12.2. Characteristics.......................................................................................................... 245
12.3. Block diagram........................................................................................................... 246
12.4. Function overview.................................................................................................... 246
12.4.1. DMAMUX signals................................................................................................................ 247
12.4.2. DMAMUX request multiplexer ............................................................................................ 247
12.4.3. DMAMUX request generator .............................................................................................. 250
12.4.4. Channel configurations ....................................................................................................... 250
12.4.5. Interrupt............................................................................................................................... 251
12.4.6. DMAMUX mapping ............................................................................................................. 251
12.5. Register definition.................................................................................................... 256
12.5.1. Request multiplexer channel x configuration register (DMAMUX_RM_CHxCFG) ............. 256
12.5.2. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) ....................... 257
12.5.3. Request multiplexer channel interrupt flag clear register (DMAMUX_RM_INTC).............. 257
12.5.4. Request generator channel x configuration register (DMAMUX_RG_CHxCFG) ............... 258
12.5.5. Request generator interrupt flag register (DMAMUX_RG_INTF) ....................................... 259
12.5.6. Request generator interrupt flag clear register (DMAMUX_RG_INTC).............................. 259
13. Debug (DBG) .....................................................................................................261
13.1. Introduction............................................................................................................... 261
13.2. JTAG/SW function overview.................................................................................... 261
13.2.1. Switch JTAG or SW interface ............................................................................................. 261
13.2.2. Pin assignment ................................................................................................................... 261
13.2.3. JTAG daisy chained structure............................................................................................. 262
13.2.4. Debug reset ........................................................................................................................ 262
13.2.5. JEDEC-106 ID code ........................................................................................................... 262
13.3. Debug hold function overview................................................................................ 262
13.3.1. Debug support for power saving mode............................................................................... 262
13.3.2. Debug support for TIMER, I2C, WWDGT and FWDGT ..................................................... 263
13.4. Registers definition.................................................................................................. 264
13.4.1. ID code register (DBG_ID).................................................................................................. 264
13.4.2. Control register (DBG_CTL) ............................................................................................... 264
14. Analog-to-digital converter (ADC)...................................................................267
14.1. Overview.................................................................................................................... 267

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14.2. Characteristics.......................................................................................................... 267
14.3. Pins and internal signals......................................................................................... 268
14.4. Function overview.................................................................................................... 269
14.4.1. Foreground calibration function.......................................................................................... 269
14.4.2. ADC clock ........................................................................................................................... 270
14.4.3. ADC enable......................................................................................................................... 270
14.4.4. Routine sequence............................................................................................................... 270
14.4.5. Operation modes ................................................................................................................ 270
14.4.6. Conversion result threshold monitor function ..................................................................... 273
14.4.7. Data alignment.................................................................................................................... 273
14.4.8. Sample time configuration .................................................................................................. 274
14.4.9. External trigger configuration.............................................................................................. 274
14.4.10. DMA request ....................................................................................................................... 274
14.4.11. ADC internal channels........................................................................................................ 275
14.4.12. Programmable resolution (DRES) ...................................................................................... 276
14.4.13. On-chip hardware oversampling......................................................................................... 276
14.5. ADC sync mode ........................................................................................................ 278
14.5.1. Free mode........................................................................................................................... 279
14.5.2. Routine parallel mode......................................................................................................... 279
14.5.3. Routine follow-up fast mode ............................................................................................... 280
14.5.4. Routine follow-up slow mode.............................................................................................. 280
14.6. ADC interrupts .......................................................................................................... 281
14.7. Register definition .................................................................................................... 282
14.7.1. Status register (ADC_STAT) ............................................................................................... 282
14.7.2. Control register 0 (ADC_CTL0) .......................................................................................... 283
14.7.3. Control register 1 (ADC_CTL1) .......................................................................................... 285
14.7.4. Sample time register 0 (ADC_SAMPT0) ............................................................................ 286
14.7.5. Sample time register 1 (ADC_SAMPT1) ............................................................................ 287
14.7.6. Watchdog high threshold register 0 (ADC_WDHT0) .......................................................... 288
14.7.7. Watchdog low threshold register 0 (ADC_WDLT0) ............................................................ 288
14.7.8. Routine sequence register 0 (ADC_RSQ0)........................................................................ 289
14.7.9. Routine sequence register 1 (ADC_RSQ1)........................................................................ 289
14.7.10. Routine sequence register 2 (ADC_RSQ2)........................................................................ 290
14.7.11. Routine data register (ADC_RDATA).................................................................................. 290
14.7.12. Oversample control register (ADC_OVSAMPCTL) ............................................................ 291
14.7.13. Watchdog 1 Channel Selection Register (ADC_WD1SR).................................................. 292
14.7.14. Watchdog threshold register 1 (ADC_WDT1)..................................................................... 293
15. Digital-to-analog converter (DAC) ...................................................................295
15.1. Overview.................................................................................................................... 295
15.2. Characteristics.......................................................................................................... 295

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15.3. Function overview .................................................................................................... 296
15.3.1. DAC enable......................................................................................................................... 296
15.3.2. DAC output buffer ............................................................................................................... 296
15.3.3. DAC data configuration....................................................................................................... 296
15.3.4. DAC trigger ......................................................................................................................... 296
15.3.5. DAC workflow ..................................................................................................................... 297
15.3.6. DAC noise wave ................................................................................................................. 297
15.3.7. DAC output calculate .......................................................................................................... 298
15.3.8. DMA request ....................................................................................................................... 298
15.4. Registers definition.................................................................................................. 299
15.4.1. Control register (DAC_CTL) ............................................................................................... 299
15.4.2. Software trigger register (DAC_SWT) ................................................................................ 300
15.4.3. DAC_OUT 12-bit right-aligned data holding register (OUT_R12DH) ................................. 301
15.4.4. DAC_OUT 12-bit left-aligned data holding register (OUT_L12DH).................................... 301
15.4.5. DAC_OUT 8-bit right-aligned data holding register (OUT_R8DH) ..................................... 302
15.4.6. DAC_OUT data output register (OUT_DO) ........................................................................ 302
15.4.7. DAC Status register (DAC_STAT) ...................................................................................... 302
16. Watchdog timer (WDGT) ..................................................................................304
16.1. Free watchdog timer (FWDGT) ............................................................................... 304
16.1.1. Overview ............................................................................................................................. 304
16.1.2. Characteristics .................................................................................................................... 304
16.1.3. Function overview ............................................................................................................... 304
16.1.4. Register definition ............................................................................................................... 307
16.2. Window watchdog timer (WWDGT)........................................................................ 311
16.2.1. Overview ..............................................................................................................................311
16.2.2. Characteristics .....................................................................................................................311
16.2.3. Function overview ................................................................................................................311
16.2.4. Register definition ............................................................................................................... 314
17. Real-time clock (RTC).......................................................................................316
17.1. Overview.................................................................................................................... 316
17.2. Characteristics.......................................................................................................... 316
17.3. Function overview .................................................................................................... 316
17.3.1. RTC reset............................................................................................................................ 317
17.3.2. RTC reading........................................................................................................................ 317
17.3.3. RTC configuration ............................................................................................................... 317
17.3.4. RTC flag assertion .............................................................................................................. 318
17.4. Register definition .................................................................................................... 320
17.4.1. RTC interrupt enable register (RTC_INTEN)...................................................................... 320
17.4.2. RTC control register (RTC_CTL) ........................................................................................ 320
17.4.3. RTC prescaler high register (RTC_PSCH) ......................................................................... 321