GigaDevice Semiconductor GD32E502 Series User manual

GigaDevice Semiconductor Inc.
GD32E502xx
Arm® Cortex®-M33 32-bit MCU
User Manual
Revision 1.1
(Sep. 2023)

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Table of Contents
Table of Contents.................................................................................................................2
List of Figures ....................................................................................................................16
List of Tables ......................................................................................................................22
1. System and memory architecture ............................................................................25
1.1. Arm®Cortex®-M33 processor...................................................................................25
1.2. Systemarchitecture.................................................................................................26
1.3. Memory map.............................................................................................................28
1.3.1. On-chip SRAM memory ..........................................................................................32
1.3.2. On-chip Flash memory............................................................................................34
1.4. Boot configuration...................................................................................................34
1.5. Systemconfiguration controller..............................................................................35
1.6. Systemconfiguration registers...............................................................................36
1.6.1. System configuration register 0 (SYSCFG_CFG0) ......................................................36
1.6.2. System configuration register 1 (SYSCFG_CFG1) ......................................................37
1.6.3. EXTI sources selection register 0 (SYSCFG_EXTISS0) ...............................................37
1.6.4. EXTI sources selection register 1 (SYSCFG_EXTISS1) ...............................................38
1.6.5. EXTI sources selection register 2 (SYSCFG_EXTISS2) ...............................................40
1.6.6. EXTI sources selection register 3 (SYSCFG_EXTISS3) ...............................................41
1.6.7. System configuration register 2 (SYSCFG_CFG2) ......................................................42
1.6.8. System status register (SYSCFG_STAT) ...................................................................43
1.6.9. System configuration register 3 (SYSCFG_CFG3) ......................................................44
1.6.10. TIMER input source select register (SYSCFG_TIMERINSEL).......................................45
1.7. Device electronic signature.....................................................................................47
1.7.1. Memory density information.....................................................................................48
1.7.2. Unique device ID (96 bits) .......................................................................................48
2. Flash me mory controller (FMC) ................................................................................50
2.1. Overview...................................................................................................................50
2.2. Characteristics.........................................................................................................50
2.3. Function overview....................................................................................................50
2.3.1. Flash memory architecture ......................................................................................50
2.3.2. Error Checking and Correcting (ECC)........................................................................54
2.3.3. Read operations ....................................................................................................55
2.3.4. Dual bank architecture with read-while-write (RWW) capability......................................56
2.3.5. Unlock the FMC_CTLx register ................................................................................56
2.3.6. Page erase ...........................................................................................................57

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2.3.7. Mass erase...........................................................................................................58
2.3.8. Main flash programming..........................................................................................59
2.3.9. Main Flash Fast Programming..................................................................................61
2.3.10. Check blank command............................................................................................64
2.3.11. OTP programming..................................................................................................64
2.3.12. Shared RAM .........................................................................................................64
2.3.13. Data Flash operation ..............................................................................................65
2.3.14. Emulated EEPROM................................................................................................66
2.3.15. Option bytes 0 erase...............................................................................................67
2.3.16. Option bytes programming.......................................................................................67
2.3.17. Option bytes description..........................................................................................68
2.3.18. Erase / program protection ......................................................................................73
2.3.19. Security protection .................................................................................................76
2.3.20. Error description ....................................................................................................76
2.4. Register definition....................................................................................................79
2.4.1. Wait state register (FMC_WS)..................................................................................79
2.4.2. ECC control and status register (FMC_ECCCS)..........................................................80
2.4.3. Unlock key register 0 (FMC_KEY0)...........................................................................82
2.4.4. Status register 0 (FMC_STAT0)................................................................................82
2.4.5. Control register 0 (FMC_CTL0) ................................................................................83
2.4.6. Address register 0 (FMC_ADDR0)............................................................................85
2.4.7. Option byte unlock key register (FMC_OBKEY) ..........................................................85
2.4.8. Unlock key register 1 (FMC_KEY1)...........................................................................86
2.4.9. Status register 1 (FMC_STAT1)................................................................................86
2.4.10. Control register 1 (FMC_CTL1) ................................................................................87
2.4.11. Address register 1 (FMC_ADDR1)............................................................................89
2.4.12. EEPROM counter register (FMC_EPCNT) .................................................................89
2.4.13. Option byte status register (FMC_OBSTAT) ...............................................................90
2.4.14. Erase / Program protection register 0 (FMC_WP0)......................................................91
2.4.15. Erase / Program protection register 1 (FMC_WP1)......................................................91
2.4.16. Option byte 1 control and status register (FMC_OB1CS)..............................................91
2.4.17. Product ID register (FMC_PID).................................................................................92
3. Power management unit (PMU) ................................................................................94
3.1. Overview...................................................................................................................94
3.2. Characteristics.........................................................................................................94
3.3. Function overview....................................................................................................94
3.3.1. Backup domain......................................................................................................95
3.3.2. VDD / VDDA power domain.........................................................................................96
3.3.3. 1.1V power domain ................................................................................................99
3.3.4. Power saving modes ..............................................................................................99
3.4. Register definition..................................................................................................102

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3.4.1. Control register (PMU_CTL) ..................................................................................102
3.4.2. Control and status register (PMU_CS).....................................................................103
4. Backup registers (BKP)............................................................................................106
4.1. Overview.................................................................................................................106
4.2. Characteristics.......................................................................................................106
4.3. Function overview..................................................................................................106
4.3.1. RTC clock calibration............................................................................................106
4.3.2. Tamper detection .................................................................................................106
4.4. Register definition..................................................................................................108
4.4.1. Backup data register x (BKP_DATAx) (x= 0..9) .........................................................108
4.4.2. RTC signal output control register (BKP_OCTL)........................................................108
4.4.3. Tamper pin control register (BKP_TPCTL)................................................................109
4.4.4. Tamper control and status register (BKP_TPCS).......................................................110
5. Reset and clock unit (RCU) ..................................................................................... 112
5.1. Reset control unit (RCTL) ......................................................................................112
5.1.1. Overview ............................................................................................................112
5.1.2. Function overview ................................................................................................112
5.2. Clock control unit (CCTL) ......................................................................................113
5.2.1. Overview ............................................................................................................113
5.2.2. Characteristics.....................................................................................................115
5.2.3. Function overview ................................................................................................115
5.3. Register definition..................................................................................................120
5.3.1. Control register (RCU_CTL)...................................................................................120
5.3.2. Configuration register 0 (RCU_CFG0).....................................................................122
5.3.3. Interrupt register (RCU_INT) ..................................................................................125
5.3.4. APB2 reset register (RCU_APB2RST).....................................................................128
5.3.5. APB1 reset register (RCU_APB1RST).....................................................................130
5.3.6. AHB enable register (RCU_AHBEN).......................................................................132
5.3.7. APB2 enable register (RCU_APB2EN)....................................................................133
5.3.8. APB1 enable register (RCU_APB1EN)....................................................................135
5.3.9. Backup domain control register (RCU_BDCTL).........................................................137
5.3.10. Reset source /clock register (RCU_RSTSCK)...........................................................138
5.3.11. AHB reset register (RCU_AHBRST)........................................................................141
5.3.12. Configuration register 1 (RCU_CFG1).....................................................................143
5.3.13. Configuration register 2 (RCU_CFG2).....................................................................144
5.3.14. Voltage key register (RCU_VKEY)..........................................................................145
5.3.15. Deep-sleep mode voltage register (RCU_DSV).........................................................146
6. Interrupt / event controller (EXTI)...........................................................................147
6.1. Overview.................................................................................................................147

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6.2. Characteristics.......................................................................................................147
6.3. Interrupts function overview..................................................................................147
6.4. External interrupt and event (EXTI) block diagram ...............................................151
6.5. External Interrupt and Event function overview....................................................151
6.6. Register definition..................................................................................................154
6.6.1. Interrupt enable register (EXTI_INTEN) ...................................................................154
6.6.2. Event enable register (EXTI_EVEN)........................................................................154
6.6.3. Rising edge trigger enable register (EXTI_RTEN)......................................................155
6.6.4. Falling edge trigger enable register (EXTI_FTEN) .....................................................155
6.6.5. Software interrupt event register (EXTI_SWIEV).......................................................155
6.6.6. Pending register (EXTI_PD)...................................................................................156
7. Trigger selection controller (TRIGSEL) .................................................................157
7.1. Overview.................................................................................................................157
7.2. Characteristics.......................................................................................................157
7.3. Function overview..................................................................................................157
7.4. Internal connect .....................................................................................................158
7.5. Register definition..................................................................................................163
7.5.1. Trigger selection for EXTOUT0 register (TRIGSEL_EXTOUT0) ...................................163
7.5.2. Trigger selection for EXTOUT1 register (TRIGSEL_EXTOUT1) ...................................164
7.5.3. Trigger selection for ADC0 register (TRIGSEL_ADC0)...............................................165
7.5.4. Trigger selection for ADC1 register (TRIGSEL_ADC1)...............................................165
7.5.5. Trigger selection for DAC register (TRIGSEL_DAC) ..................................................166
7.5.6. Trigger selection for TIMER0_ITI register (TRIGSEL_TIMER0IN) ................................166
7.5.7. Trigger selection for TIMER0_BRKIN register (TRIGSEL_TIMER0BRKIN)....................167
7.5.8. Trigger selection for TIMER7_ITI register (TRIGSEL_TIMER7IN) ................................168
7.5.9. Trigger selection for TIMER7_BRKIN register (TRIGSEL_TIMER7BRKIN)....................169
7.5.10. Trigger selection for TIMER19_ITI register (TRIGSEL_TIMER19IN).............................170
7.5.11. Trigger selection for TIMER19_BRKIN register (TRIGSEL_TIMER19BRKIN) ................171
7.5.12. Trigger selection for TIMER20_ITI register (TRIGSEL_TIMER20IN).............................172
7.5.13. Trigger selection for TIMER20_BRKIN register (TRIGSEL_TIMER20BRKIN) ................173
7.5.14. Trigger selection for TIMER1_ITI register (TRIGSEL_TIMER1IN) ................................174
7.5.15. Trigger selection for MFCOM register (TRIGSEL_MFCOM)........................................175
7.5.16. Trigger selection for CAN0 register (TRIGSEL_CAN0) ...............................................176
7.5.17. Trigger selection for CAN1 register (TRIGSEL_CAN1) ...............................................177
8. General-purpose and alternate-function I/Os (GPIO and AFIO).........................178
8.1. Overview.................................................................................................................178
8.2. Characteristics.......................................................................................................178
8.3. Function overview..................................................................................................178

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8.3.1. GPIO pin configuration..........................................................................................180
8.3.2. External interrupt/event lines..................................................................................180
8.3.3. Alternate functions (AF).........................................................................................180
8.3.4. Additional functions ..............................................................................................180
8.3.5. Input configuration................................................................................................181
8.3.6. Output configuration.............................................................................................181
8.3.7. Analog configuration.............................................................................................182
8.3.8. Alternate function (AF) configuration .......................................................................182
8.3.9. GPIO locking function...........................................................................................183
8.3.10. GPIO single cycle toggle function ...........................................................................183
8.4. Register definition..................................................................................................184
8.4.1. Port control register (GPIOx_CTL, x=A..F) ...............................................................184
8.4.2. Port output mode register (GPIOx_OMODE, x=A..F) .................................................186
8.4.3. Port output speed register (GPIOx_OSPD, x=A..F)....................................................187
8.4.4. Port pull-up/down register (GPIOx_PUD, x=A..F) ......................................................189
8.4.5. Port input status register (GPIOx_ISTAT, x=A..F).......................................................191
8.4.6. Port output control register (GPIOx_OCTL, x=A..F) ...................................................191
8.4.7. Port bit operate register (GPIOx_BOP, x=A..F)..........................................................191
8.4.8. Port configuration lock register (GPIOx_LOCK, x=A..F)..............................................192
8.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A..F) ..................................193
8.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A..F)..................................194
8.4.11. Bit clear register (GPIOx_BC, x=A..F)......................................................................195
8.4.12. Port bit toggle register (GPIOx_TG, x=A..F)..............................................................196
9. Multi-function communication Interface (MFCOM)..............................................197
9.1. Overview.................................................................................................................197
9.2. Characteristics.......................................................................................................197
9.3. Block diagram........................................................................................................197
9.4. Function overview..................................................................................................198
9.4.1. Clocking and resets..............................................................................................198
9.4.2. Shifter ................................................................................................................198
9.4.3. Timer..................................................................................................................200
9.4.4. Pin.....................................................................................................................202
9.4.5. Interrupts and DMA requests..................................................................................203
9.4.6. Triggers ..............................................................................................................203
9.4.7. Typical configuration of application..........................................................................204
9.5. Register definition..................................................................................................214
9.5.1. Control register (MFCOM_CTL)..............................................................................214
9.5.2. Pin data register (MFCOM_PINDATA).....................................................................214
9.5.3. Shifter status register (MFCOM_SSTAT)..................................................................215
9.5.4. Shifter error register (MFCOM_SERR) ....................................................................215
9.5.5. Timer status register (MFCOM_TMSTAT) ................................................................216

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9.5.6. Shifter status interrupt enable register (MFCOM_SSIEN) ...........................................217
9.5.7. Shifter error interrupt enable register (MFCOM_SEIEN).............................................217
9.5.8. Timer status interrupt enable register (MFCOM_TMSIEN)..........................................218
9.5.9. Shifter status DMA enable register (MFCOM_SSDMAEN)..........................................218
9.5.10. Shifter control x register (MFCOM_SCTLx) ..............................................................219
9.5.11. Shifter configuration x register (MFCOM_SCFGx).....................................................220
9.5.12. Shifter buffer x register (MFCOM_SBUFx) ...............................................................221
9.5.13. Shifter buffer x bit swapped register (MFCOM_SBUFBISx).........................................221
9.5.14. Shifter buffer x byte swapped register (MFCOM_SBUFBYSx).....................................222
9.5.15. Shifter buffer x bit byte swapped register (MFCOM_SBUFBBSx).................................222
9.5.16. Timer control x register (MFCOM_TMCTLx).............................................................223
9.5.17. Timer configuration x register (MFCOM_TMCFGx)....................................................224
9.5.18. Timer compare x register (MFCOM_TMCMPx) .........................................................226
10. CRC calculation unit (CRC) ..................................................................................228
10.1. Overview .............................................................................................................228
10.2. Characteristics....................................................................................................228
10.3. Function overview ..............................................................................................229
10.4. Register definition ..............................................................................................230
10.4.1. Data register (CRC_DATA)....................................................................................230
10.4.2. Free data register (CRC_FDATA) ...........................................................................230
10.4.3. Control register (CRC_CTL)...................................................................................231
10.4.4. Initialization data register (CRC_IDATA)...................................................................231
10.4.5. Polynomial register (CRC_POLY) ...........................................................................232
11. Direct memory access controller (DMA) ............................................................233
11.1. Overview.............................................................................................................233
11.2. Characteristics....................................................................................................233
11.3. Block diagram.....................................................................................................234
11.4. Function overview..............................................................................................234
11.4.1. DMA operation.....................................................................................................234
11.4.2. Peripheral handshake...........................................................................................236
11.4.3. Arbitration...........................................................................................................237
11.4.4. Address generation ..............................................................................................237
11.4.5. Circular mode......................................................................................................237
11.4.6. Memory to memory mode......................................................................................237
11.4.7. Channel configuration...........................................................................................237
11.4.8. Interrupt..............................................................................................................238
11.4.9. DMA request mapping ..........................................................................................239
11.5. Register definition ..............................................................................................240
11.5.1. Interrupt flag register (DMA_INTF)..........................................................................240
11.5.2. Interrupt flag clear register (DMA_INTC) ..................................................................241

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11.5.3. Channel x control register (DMA_CHxCTL) ..............................................................241
11.5.4. Channel x counter register (DMA_CHxCNT).............................................................243
11.5.5. Channel x peripheral base address register (DMA_CHxPADDR) .................................244
11.5.6. Channel x memory base address register (DMA_CHxMADDR)...................................244
12. DMA request multiplexer (DMAMUX) ..................................................................246
12.1. Overview.............................................................................................................246
12.2. Characteristics....................................................................................................246
12.3. Block diagram.....................................................................................................247
12.4. Function overview..............................................................................................247
12.4.1. DMAMUX signals.................................................................................................248
12.4.2. DMAMUX request multiplexer ................................................................................248
12.4.3. DMAMUX request generator..................................................................................251
12.4.4. Channel configurations .........................................................................................252
12.4.5. Interrupt..............................................................................................................252
12.4.6. DMAMUX mapping...............................................................................................252
12.5. Register definition ..............................................................................................257
12.5.1. Request multiplexer channel x configuration register (DMAMUX_RM_CHxCFG)............257
12.5.2. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) ....................258
12.5.3. Request multiplexer channel interrupt flag clear register (DMAMUX_RM_INTC) ............258
12.5.4. Request generator channel x configuration register (DMAMUX_RG_CHxCFG)..............259
12.5.5. Request generator interrupt flag register (DMAMUX_RG_INTF) ..................................260
12.5.6. Request generator interrupt flag clear register (DMAMUX_RG_INTC) ..........................260
13. Debug (DBG)...........................................................................................................262
13.1. Introduction.........................................................................................................262
13.2. JTAG/SW function overview...............................................................................262
13.2.1. Switch JTAG or SW interface.................................................................................262
13.2.2. Pin assignment ....................................................................................................262
13.2.3. JTAG daisy chained structure.................................................................................263
13.2.4. Debug reset ........................................................................................................263
13.2.5. JEDEC-106 ID code.............................................................................................263
13.3. Debug hold function overview............................................................................263
13.3.1. Debug support for power saving mode ....................................................................263
13.3.2. Debug support for TIMER, I2C, WWDGT and FWDGT...............................................264
13.4. Registers definition.............................................................................................265
13.4.1. ID code register (DBG_ID).....................................................................................265
13.4.2. Control register (DBG_CTL)...................................................................................265
14. Analog-to-digital converter (ADC).......................................................................268
14.1. Overview .............................................................................................................268

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14.2. Characteristics....................................................................................................268
14.3. Pins and internal signals ....................................................................................269
14.4. Function overview..............................................................................................270
14.4.1. Foreground calibration function..............................................................................270
14.4.2. ADC clock...........................................................................................................271
14.4.3. ADC enable.........................................................................................................271
14.4.4. Routine sequence................................................................................................271
14.4.5. Operation modes .................................................................................................271
14.4.6. Conversion result threshold monitor function............................................................274
14.4.7. Data alignment ....................................................................................................275
14.4.8. Sample time configuration.....................................................................................275
14.4.9. External trigger configuration.................................................................................276
14.4.10. DMA request .......................................................................................................276
14.4.11. ADC internal channels ..........................................................................................276
14.4.12. Programmable resolution (DRES)...........................................................................277
14.4.13. On-chip hardware oversampling.............................................................................278
14.5. ADC sync mode ..................................................................................................279
14.5.1. Free mode ..........................................................................................................280
14.5.2. Routine parallel mode...........................................................................................281
14.5.3. Routine follow-up fast mode...................................................................................281
14.5.4. Routine follow-up slow mode .................................................................................282
14.6. ADC interrupts ....................................................................................................283
14.7. Register definition ..............................................................................................284
14.7.1. Status register (ADC_STAT) ..................................................................................284
14.7.2. Control register 0 (ADC_CTL0) ..............................................................................285
14.7.3. Control register 1 (ADC_CTL1) ..............................................................................287
14.7.4. Sample time register 0 (ADC_SAMPT0) ..................................................................288
14.7.5. Sample time register 1 (ADC_SAMPT1) ..................................................................289
14.7.6. Watchdog high threshold register 0 (ADC_WDHT0)...................................................290
14.7.7. Watchdog low threshold register 0 (ADC_WDLT0).....................................................290
14.7.8. Routine sequence register 0 (ADC_RSQ0) ..............................................................291
14.7.9. Routine sequence register 1 (ADC_RSQ1) ..............................................................291
14.7.10. Routine sequence register 2 (ADC_RSQ2) ..............................................................292
14.7.11. Routine data register (ADC_RDATA).......................................................................293
14.7.12. Oversample control register (ADC_OVSAMPCTL) ....................................................293
14.7.13. Watchdog 1 Channel Selection Register (ADC_WD1SR)............................................295
14.7.14. Watchdog threshold register 1 (ADC_WDT1)............................................................295
15. Digital-to-analog converter (DAC) .......................................................................297
15.1. Overview .............................................................................................................297
15.2. Characteristics....................................................................................................297

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15.3. Function overview ..............................................................................................298
15.3.1. DAC enable.........................................................................................................298
15.3.2. DAC output buffer ................................................................................................298
15.3.3. DAC data configuration.........................................................................................298
15.3.4. DAC trigger.........................................................................................................298
15.3.5. DAC workflow......................................................................................................299
15.3.6. DAC noise wave ..................................................................................................299
15.3.7. DAC output calculate............................................................................................300
15.3.8. DMA request .......................................................................................................300
15.4. Registers definition.............................................................................................301
15.4.1. Control register (DAC_CTL)...................................................................................301
15.4.2. Software trigger register (DAC_SWT)......................................................................302
15.4.3. DAC_OUT 12-bit right-aligned data holding register (OUT_R12DH).............................303
15.4.4. DAC_OUT 12-bit left-aligned data holding register (OUT_L12DH) ...............................303
15.4.5. DAC_OUT 8-bit right-aligned data holding register (OUT_R8DH).................................304
15.4.6. DAC_OUT data output register (OUT_DO)...............................................................304
15.4.7. DAC Status register (DAC_STAT)...........................................................................304
16. Watchdog timer (WDGT) .......................................................................................306
16.1. Free watchdog timer (FWDGT)...........................................................................306
16.1.1. Overview ............................................................................................................306
16.1.2. Characteristics.....................................................................................................306
16.1.3. Function overview ................................................................................................306
16.1.4. Register definition ................................................................................................309
16.2. Window watchdog timer (WWDGT)....................................................................313
16.2.1. Overview ............................................................................................................313
16.2.2. Characteristics.....................................................................................................313
16.2.3. Function overview ................................................................................................313
16.2.4. Register definition ................................................................................................316
17. Real-time clock (RTC)............................................................................................318
17.1. Overview .............................................................................................................318
17.2. Characteristics....................................................................................................318
17.3. Function overview ..............................................................................................318
17.3.1. RTC reset...........................................................................................................319
17.3.2. RTC reading........................................................................................................319
17.3.3. RTC configuration................................................................................................320
17.3.4. RTC flag assertion................................................................................................320
17.4. Register definition ..............................................................................................322
17.4.1. RTC interrupt enable register (RTC_INTEN).............................................................322
17.4.2. RTC control register (RTC_CTL).............................................................................322
17.4.3. RTC prescaler high register (RTC_PSCH) ...............................................................323

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17.4.4. RTC prescaler low register (RTC_PSCL) .................................................................324
17.4.5. RTC divider high register (RTC_DIVH) ....................................................................324
17.4.6. RTC divider low register (RTC_DIVL)......................................................................324
17.4.7. RTC counter high register (RTC_CNTH) ..................................................................325
17.4.8. RTC counter low register (RTC_CNTL)....................................................................325
17.4.9. RTC alarm high register (RTC_ALRMH) ..................................................................326
17.4.10. RTC alarm low register (RTC_ALRML)....................................................................326
18. TIMER.......................................................................................................................327
18.1. Advanced timer (TIMERx, x=0, 7, 19, 20)............................................................328
18.1.1. Overview ............................................................................................................328
18.1.2. Characteristics.....................................................................................................328
18.1.3. Block diagram......................................................................................................329
18.1.4. Function overview ................................................................................................329
18.1.5. Registers definition (TIMERx, x=0, 7, 19, 20)............................................................364
18.2. General level0 timer (TIMERx, x=1) ....................................................................422
18.2.1. Overview ............................................................................................................422
18.2.2. Characteristics.....................................................................................................422
18.2.3. Block diagram......................................................................................................422
18.2.4. Function overview ................................................................................................423
18.2.5. Registers definition (TIMERx, x=1)..........................................................................439
18.3. Basic timer (TIMERx, x=5, 6)...............................................................................462
18.3.1. Overview ............................................................................................................462
18.3.2. Characteristics.....................................................................................................462
18.3.3. Block diagram......................................................................................................462
18.3.4. Function overview ................................................................................................462
18.3.5. Registers definition (TIMERx, x=5, 6) ......................................................................466
19. Universal synchronous/asynchronous receiver /transmitter (USART).........471
19.1. Overview.............................................................................................................471
19.2. Characteristics....................................................................................................471
19.3. Function overview..............................................................................................472
19.3.1. USART frame format ............................................................................................473
19.3.2. Baud rate generation............................................................................................474
19.3.3. USART transmitter ...............................................................................................475
19.3.4. USART receiver ...................................................................................................476
19.3.5. Use DMA for data buffer access .............................................................................477
19.3.6. Hardware flow control ...........................................................................................479
19.3.7. Multi-processor communication..............................................................................480
19.3.8. LIN mode............................................................................................................481
19.3.9. Synchronous mode ..............................................................................................482
19.3.10. IrDA SIR ENDEC mode.........................................................................................483
19.3.11. Half-duplex communication mode...........................................................................485

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19.3.12. Smartcard (ISO7816-3) mode................................................................................485
19.3.13. ModBus communication........................................................................................487
19.3.14. Receive FIFO......................................................................................................487
19.3.15. Wakeup from Deep-sleep mode .............................................................................488
19.3.16. USART interrupts .................................................................................................488
19.4. Register definition ..............................................................................................491
19.4.1. Control register 0 (USART_CTL0)...........................................................................491
19.4.2. Control register 1 (USART_CTL1)...........................................................................493
19.4.3. Control register 2 (USART_CTL2)...........................................................................496
19.4.4. Baud rate generator register (USART_BAUD) ..........................................................498
19.4.5. Prescaler and guard time configuration register (USART_GP).....................................499
19.4.6. Receiver timeout register (USART_RT) ...................................................................500
19.4.7. Command register (USART_CMD) .........................................................................501
19.4.8. Status register (USART_STAT) ..............................................................................501
19.4.9. Interrupt status clear register (USART_INTC) ...........................................................505
19.4.10. Receive data register (USART_RDATA) ..................................................................506
19.4.11. Transmit data register (USART_TDATA) ..................................................................507
19.4.12. USART coherence control register (USART_CHC) ....................................................507
19.4.13. USART receive FIFO control and status register (USART_RFCS) ...............................508
20. Inter-integrated circuit interface (I2C).................................................................510
20.1. Overview.............................................................................................................510
20.2. Characteristics....................................................................................................510
20.3. Function overview..............................................................................................510
20.3.1. Clock requirements ..............................................................................................511
20.3.2. I2C communication flow ........................................................................................512
20.3.3. Noise filter...........................................................................................................515
20.3.4. I2C timings configuration.......................................................................................515
20.3.5. I2C reset.............................................................................................................517
20.3.6. Data transfer .......................................................................................................517
20.3.7. I2C slave mode....................................................................................................519
20.3.8. I2C master mode .................................................................................................524
20.3.9. SMBus support ....................................................................................................529
20.3.10. SMBus mode.......................................................................................................532
20.3.11. Use DMA for data transfer .....................................................................................534
20.3.12. I2C error and interrupts .........................................................................................534
20.3.13. I2C debug mode ..................................................................................................535
20.4. Register definition ..............................................................................................536
20.4.1. Control register 0 (I2C_CTL0) ................................................................................536
20.4.2. Control register 1 (I2C_CTL1) ................................................................................538
20.4.3. Slave address register 0 (I2C_SADDR0) .................................................................540
20.4.4. Slave address register 1 (I2C_SADDR1) .................................................................541

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20.4.5. Timing register (I2C_TIMING) ................................................................................542
20.4.6. Timeout register (I2C_TIMEOUT) ...........................................................................543
20.4.7. Status register (I2C_STAT) ....................................................................................544
20.4.8. Status clear register (I2C_STATC) ..........................................................................547
20.4.9. PEC register (I2C_PEC)........................................................................................548
20.4.10. Receive data register (I2C_RDATA)........................................................................548
20.4.11. Transmit data register (I2C_TDATA)........................................................................548
20.4.12. Control register 2 (I2C_CTL2) ................................................................................549
21. Serial peripheral interface/Inter-IC sound (SPI/I2S)..........................................550
21.1. Overview .............................................................................................................550
21.2. Characteristics....................................................................................................550
21.2.1. SPI characteristics ...............................................................................................550
21.2.2. I2S characteristics................................................................................................550
21.3. SPI function overview.........................................................................................551
21.3.1. SPI block diagram ..............................................................................................551
21.3.2. SPI signal description ...........................................................................................551
21.3.3. SPI clock timing and data format ............................................................................552
21.3.4. NSS function.......................................................................................................553
21.3.5. SPI operating modes ............................................................................................554
21.3.6. DMA function.......................................................................................................563
21.3.7. CRC function.......................................................................................................563
21.3.8. SPI interrupts ......................................................................................................564
21.4. I2S function overview.........................................................................................565
21.4.1. I2S block diagram ................................................................................................565
21.4.2. I2S signal description............................................................................................566
21.4.3. I2S audio standards..............................................................................................566
21.4.4. I2S clock.............................................................................................................574
21.4.5. Operation............................................................................................................575
21.4.6. DMA function.......................................................................................................579
21.4.7. I2S interrupts.......................................................................................................579
21.5. Register definition ..............................................................................................581
21.5.1. Control register 0 (SPI_CTL0) ................................................................................581
21.5.2. Control register 1 (SPI_CTL1) ................................................................................583
21.5.3. Status register (SPI_STAT)....................................................................................584
21.5.4. Data register (SPI_DATA)......................................................................................585
21.5.5. CRC polynomial register (SPI_CRCPOLY)...............................................................586
21.5.6. RX CRC register (SPI_RCRC) ...............................................................................586
21.5.7. TX CRC register (SPI_TCRC) ................................................................................587
21.5.8. I2S control register (SPI_I2SCTL)...........................................................................588
21.5.9. I2S clock prescaler register (SPI_I2SPSC)...............................................................589
21.5.10. Quad-SPI mode control register (SPI_QCTL) of SPI0 ................................................590

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22. Comparator (CMP) .................................................................................................592
22.1. Overview .............................................................................................................592
22.2. Characteristic......................................................................................................592
22.3. Function overview..............................................................................................592
22.3.1. CMP inputs and outputs ........................................................................................593
22.3.2. CMP output blanking ............................................................................................593
22.3.3. CMP register write protection.................................................................................594
22.3.4. CMP power mode ................................................................................................594
22.3.5. CMP hysteresis....................................................................................................594
22.3.6. CMP interrupt......................................................................................................595
22.4. Register definition ..............................................................................................596
22.4.1. CMP Control/status register (CMP_CS)...................................................................596
23. Controller area network (CAN).............................................................................599
23.1. Overview .............................................................................................................599
23.2. Characteristics....................................................................................................599
23.3. Function overview ..............................................................................................600
23.3.1. Mailbox descriptor................................................................................................601
23.3.2. Rx FIFO descriptor...............................................................................................606
23.3.3. Communication modes .........................................................................................612
23.3.4. Power saving modes ............................................................................................613
23.3.5. Data transmission ................................................................................................614
23.3.6. Data reception.....................................................................................................618
23.3.7. Data reception in Pretended Networking mode .........................................................625
23.3.8. CAN FD operation................................................................................................628
23.3.9. Errors and states..................................................................................................631
23.3.10. Communication parameters...................................................................................634
23.3.11. Interrupts ............................................................................................................637
23.4. Example for a typical configuration flow of CAN...............................................637
23.5. CAN registers......................................................................................................640
23.5.1. Control register 0 (CAN_CTL0) ..............................................................................640
23.5.2. Control register 1 (CAN_CTL1) ..............................................................................642
23.5.3. Timer register (CAN_TIMER) .................................................................................644
23.5.4. Receive mailbox public filter register (CAN_RMPUBF)...............................................644
23.5.5. Error register 0 (CAN_ERR0).................................................................................645
23.5.6. Error register 1 (CAN_ERR1).................................................................................645
23.5.7. Interrupt enable register (CAN_INTEN)....................................................................648
23.5.8. Status register (CAN_STAT) ..................................................................................649
23.5.9. Control register 2 (CAN_CTL2) ..............................................................................650
23.5.10. CRC for classical frame register (CAN_CRCC).........................................................652
23.5.11. Receive FIFO public filter register (CAN_RFIFOPUBF)..............................................653

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23.5.12. Receive FIFO identifier filter matching number register (CAN_RFIFOIFMN)..................653
23.5.13. Bit timing register (CAN_BT)..................................................................................654
23.5.14. Receive FIFO/mailbox private filter x register (CAN_RFIFOMPFx)(x=0..31) ..................655
23.5.15. Pretended Networking mode control register 0 (CAN_PN_CTL0).................................655
23.5.16. Pretended Networking mode timeout register (CAN_PN_TO)......................................657
23.5.17. Pretended Networking mode status register (CAN_PN_STAT) ....................................657
23.5.18. Pretended Networking mode expected identifier 0 register (CAN_PN_EID0) .................658
23.5.19. Pretended Networking mode expected DLC register (CAN_PN_EDLC) ........................659
23.5.20. Pretended Networking mode expected data low 0 register (CAN_PN_EDL0).................659
23.5.21. Pretended Networking mode expected data low 1 register (CAN_PN_EDL1).................660
23.5.22. Pretended Networking mode identifier filter / expected identifier 1 register
(CAN_PN_IFEID1) ............................................................................................................661
23.5.23. Pretended Networking mode data 0 filter / expected data high 0 register
(CAN_PN_DF0EDH0)........................................................................................................661
23.5.24. Pretended Networking mode data 1 filter / expected data high 1 register
(CAN_PN_DF1EDH1)........................................................................................................662
23.5.25. Pretended Networking mode received wakeup mailbox x control status information register
(CAN_PN_RWMxCS)(x=0..3)..............................................................................................663
23.5.26. Pretended Networking mode received wakeup mailbox x identifier register
(CAN_PN_RWMxI)(x=0..3) .................................................................................................664
23.5.27. Pretended Networking mode received wakeup mailbox x data 0 register
(CAN_PN_RWMxD0)(x=0..3)..............................................................................................664
23.5.28. Pretended Networking mode received wakeup mailbox x data 1 register
(CAN_PN_RWMxD1)(x=0..3)..............................................................................................665
23.5.29. FD control register (CAN_FDCTL) ..........................................................................665
23.5.30. FD bit timing register (CAN_FDBT) .........................................................................666
23.5.31. CRC for classical and FD frame register (CAN_CRCCFD)..........................................667
24. Appendix .................................................................................................................669
24.1. List of abbreviations used in register ................................................................669
24.2. List of terms........................................................................................................669
24.3. Available peripherals..........................................................................................670
25. Revision history .....................................................................................................671

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List of Figures
Figure 1-1. The structure of the Cortex®-M33 processor....................................................................26
Figure 1-2. Series system architecture of GD32E502xx series........................................................28
Figure 1-3. ECC decoder...................................................................................................................................33
Figure 2-1. Process of page erase operation...........................................................................................58
Figure 2-2. Process of mass erase operation..........................................................................................59
Figure 2-3. Process of word program operation.....................................................................................61
Figure 2-4. Process of fast programming operation.............................................................................63
Figure 3-1. Power supply overview..............................................................................................................95
Figure 3-2. Waveform of the POR / PDR.....................................................................................................96
Figure 3-3. Waveform of the BOR .................................................................................................................97
Figure 3-4. Waveform of the LVD threshold.............................................................................................98
Figure 3-5. Waveform of the OVD threshold.............................................................................................98
Figure 5-1. The system reset circuit...........................................................................................................113
Figure 5-2. Clock tree........................................................................................................................................114
Figure 5-3. HXTAL clock source...................................................................................................................115
Figure 5-4. HXTAL clock source in bypass mode ................................................................................116
Figure 6-1. Block diagram of EXTI..............................................................................................................151
Figure 7-1. TRIGSEL main composition example ................................................................................158
Figure 8-1. Basic structure of a general-pupose I/O...........................................................................179
Figure 8-2. Basic structure of Input configuration..............................................................................181
Figure 8-3. Basic structure of Output configuration...........................................................................181
Figure 8-4. Basic structure of Analog configuration..........................................................................182
Figure 8-5. Basic structure of Alternate function configuration....................................................183
Figure 9-1. MFCOM block diagram.............................................................................................................197
Figure 9-2. Shifter microarchitecture.........................................................................................................199
Figure 10-1. Block diagram of CRC calculation unit...........................................................................228
Figure 11-1. Block diagram of DMA............................................................................................................234
Figure 11-2. Handshake mechanism..........................................................................................................236
Figure 11-3. DMA interrupt logic..................................................................................................................239
Figure 12-1. Block diagram of DMAMUX..................................................................................................247
Figure 12-2. Synchronization mode...........................................................................................................249
Figure 12-3. Event generation.......................................................................................................................250
Figure 14-1. ADC module block diagram (for ADC0 and ADC1)....................................................270
Figure 14-2. Single operation mode...........................................................................................................271
Figure 14-3. Continuous operation mode................................................................................................272
Figure 14-4. Scan operation mode, continuous disable ...................................................................273
Figure 14-5. Scan operation mode, continuous enable.....................................................................273
Figure 14-6. Discontinuous operation mode..........................................................................................274
Figure 14-7. 12-bit Data alignment..............................................................................................................275
Figure 14-8. 6-bit Data alignment................................................................................................................275

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Figure 14-9. 20-bit to 16-bit result truncation.........................................................................................278
Figure 14-10. Numerical example with 5-bits shift and rounding.................................................279
Figure 14-11. ADC sync block diagram....................................................................................................280
Figure 14-12. Routine parallel mode on 16 channels.........................................................................281
Figure 14-13. Routine follow-up fast mode on 1 channel in continuous operation mode.282
Figure 14-14. Routine follow-up slow mode on 1 channel...............................................................282
Figure 15-1. DAC block diagram..................................................................................................................297
Figure 15-2. DAC LFSR algorithm...............................................................................................................299
Figure 15-3. DAC triangle noise wave .......................................................................................................300
Figure 16-1. Free watchdog block diagram ............................................................................................307
Figure 16-2. Window watchdog timer block diagram.........................................................................313
Figure 16-3. Window watchdog timing diagram ...................................................................................314
Figure 17-1. Block diagram of RTC.............................................................................................................319
Figure 17-2. RTC second and alarm waveform example (RTC_PSC = 3, RTC_ALRM = 2).321
Figure 17-3. RTC second and overflow waveform example (RTC_PSC= 3) .............................321
Figure 18-1. Advanced timer block diagram...........................................................................................329
Figure 18-2. Timing chart of internal clock divided by 1...................................................................330
Figure 18-3. Timing chart of PSC value change from 0 to 2............................................................331
Figure 18-4. Timing chart of up counting mode, PSC=0/2 ...............................................................332
Figure 18-5. Timing chart of up counting mode, change TIMERx_CAR on the go................333
Figure 18-6. Timing chart of down counting mode, PSC=0/2.........................................................334
Figure 18-7. Timing chart of down counting mode, change TIMERx_CAR on the go..........334
Figure 18-8. Timing chart of center-aligned counting mode...........................................................336
Figure 18-9. Repetition counter timing chart of center-aligned counting mode ....................337
Figure 18-10. Repetition counter timing chart of up counting mode ..........................................337
Figure 18-11. Repetition counter timing chart of down counting mode.....................................338
Figure 18-12. Channel 0 input capture principle...................................................................................339
Figure 18-13. Multi mode channel 0 input capture principle...........................................................339
Figure 18-14. Channel output compare principle (when MCHxMSEL = 2’00, x=0, 1, 2, 3)..341
Figure 18-15. Channel output compare principle (when MCHxMSEL = 2’01, x=0, 1, 2, 3)..341
Figure 18-16. Channel output compare principle (with complementary output when
MCHxMSEL = 2’11, x=0,1,2,3)...............................................................................................................341
Figure 18-17. Output-compare under three modes.............................................................................343
Figure 18-18. EAPWM timechart..................................................................................................................344
Figure 18-19. CAPWM timechart..................................................................................................................344
Figure 18-20. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD).............................346
Figure 18-21. Channel x output PWM with (CHxVAL = CHxCOMVAL_ADD).............................346
Figure 18-22. Channel x output PWM with (CHxVAL > CHxCOMVAL_ADD).............................346
Figure 18-23. Channel x output PWM with CHxVAL or CHxCOMVAL_ADD exceeds CARL
...........................................................................................................................................................................347
Figure 18-24. Channel x output PWM duty cycle changing with CHxCOMVAL_ADD ..........347
Figure 18-25. Four Channels outputs in Composite PWM mode ..................................................348
Figure 18-26. CHx_O output with a pulse in edge-aligned mode (CHxOMPSEL≠2’b00).....349
Figure 18-27. CHx_O output with a pulse in center-aligned mode (CHxOMPSEL≠2’b00) ..349

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Figure 18-28. Channel output complementary PWM with dead-time insertion.......................352
Figure 18-29. Break function diagram.......................................................................................................353
Figure 18-30. Output behavior of the channel in response to a break (the break high active)
...........................................................................................................................................................................354
Figure 18-31. Counter behavior with CI0FE0 polarity non-inverted in mode 2.......................355
Figure 18-32. Counter behavior with CI0FE0 polarity inverted in mode 2.................................356
Figure 18-33. Hall sensor is used for BLDC motor ..............................................................................357
Figure 18-34. Hall sensor timing between two timers........................................................................357
Figure 18-35. Restart mode............................................................................................................................358
Figure 18-36. Pause mode..............................................................................................................................359
Figure 18-37. Event mode...............................................................................................................................359
Figure 18-38. Single pulse mode TIMERx_CHxCV=0x04, TIMERx_CAR=0x99 ........................360
Figure 18-39. TIMER0 master/slave mode example ............................................................................361
Figure 18-40. Triggering TIMER0 with enable signal of TIMER1....................................................362
Figure 18-41. Triggering TIMER0 and TIMER1 with TIMER1’s CI0 input ....................................363
Figure 18-42. General Level 0 timer block diagram.............................................................................423
Figure 18-43. Timing chart of internal clock divided by 1................................................................424
Figure 18-44. Timing chart of PSC value change from 0 to 2.........................................................425
Figure 18-45. Timing chart of up counting mode, PSC=0/2.............................................................426
Figure 18-46. Timing chart of up counting, change TIMERx_CAR on the go..........................426
Figure 18-47. Timing chart of down counting mode, PSC=0/2.......................................................427
Figure 18-48. Timing chart of down counting mode, change TIMERx_CAR on the go.......428
Figure 18-49. Timing chart of center-aligned counting mode.........................................................429
Figure 18-50. Channels input capture principle....................................................................................430
Figure 18-51. Channel output compare principle (x=0,1,2,3) ..........................................................431
Figure 18-52. Output-compare under three modes.............................................................................432
Figure 18-53. EAPWM timechart..................................................................................................................433
Figure 18-54. CAPWM timechart..................................................................................................................433
Figure 18-55. Counter behavior with CI0FE0 polarity non-inverted in mode 2.......................435
Figure 18-56. Counter behavior with CI0FE0 polarity inverted in mode 2.................................435
Figure 18-57. Restart mode............................................................................................................................436
Figure 18-58. Pause mode..............................................................................................................................436
Figure 18-59. Event mode...............................................................................................................................437
Figure 18-60. Single pulse mode TIMERx_CHxCV = 0x04, TIMERx_CAR=0x99 .....................438
Figure 18-61. Basic timer block diagram.................................................................................................462
Figure 18-62. Timing chart of internal clock divided by 1................................................................463
Figure 18-63. Timing chart of PSC value change from 0 to 2.........................................................463
Figure 18-64. Timing chart of up counting mode, PSC=0/2.............................................................464
Figure 18-65. Timing chart of up counting mode, change TIMERx_CAR on the go .............465
Figure 19-1. USART module block diagram............................................................................................473
Figure 19-2. USART character frame (8 bits data and 1 stop bit)..................................................473
Figure 19-3. USART transmit procedure ..................................................................................................475
Figure 19-4. Oversampling method of a receive frame bit (OSB=0) ............................................477
Figure 19-5. Configuration step when using DMA for USART transmission ...........................478

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Figure 19-6. Configuration step when using DMA for USART reception...................................479
Figure 19-7. Hardware flow control between two USARTs ..............................................................479
Figure 19-8. Hardware flow control ............................................................................................................480
Figure 19-9. Break frame occurs during idle state ..............................................................................482
Figure 19-10. Break frame occurs during a frame ...............................................................................482
Figure 19-11. Example of USART in synchronous mode..................................................................483
Figure 19-12. 8-bit format USART synchronous waveform (CLEN=1) ........................................483
Figure 19-13. IrDA SIR ENDEC module.....................................................................................................484
Figure 19-14. IrDA data modulation............................................................................................................484
Figure 19-15. ISO7816-3 frame format.......................................................................................................485
Figure 19-16. USART Receive FIFO structure........................................................................................488
Figure 19-17. USART interrupt mapping diagram................................................................................490
Figure 20-1. I2C module block diagram....................................................................................................511
Figure 20-2. Data validation...........................................................................................................................512
Figure 20-3. START and STOP signal........................................................................................................513
Figure 20-4. I2C communication flow with 10-bit address (Master Transmit) .........................513
Figure 20-5. I2C communication flow with 7-bit address (Master Transmit)............................514
Figure 20-6. I2C communication flow with 7-bit address (Master Receive)..............................514
Figure 20-7. I2C communication flow with 10-bit address (Master Receive when HEAD10R=0)
...........................................................................................................................................................................514
Figure 20-8. I2C communication flow with 10-bit address (Master Receive when HEAD10R=1)
...........................................................................................................................................................................514
Figure 20-9. Data hold time............................................................................................................................515
Figure 20-10. Data setup time .......................................................................................................................516
Figure 20-11. Data transmission ..................................................................................................................518
Figure 20-12. Data reception.........................................................................................................................518
Figure 20-13. I2C initialization in slave mode ........................................................................................521
Figure 20-14. Programming model for slave transmitting when SS=0.......................................522
Figure 20-15. Programming model for slave transmitting when SS=1 .......................................523
Figure 20-16. Programming model for slave receiving......................................................................524
Figure 20-17. I2C initialization in master mode.....................................................................................525
Figure 20-18. Programming model for master transmitting (N<=255) ........................................526
Figure 20-19. Programming model for master transmitting (N>255) ...........................................527
Figure 20-20. Programming model for master receiving (N<=255)...............................................528
Figure 20-21. Programming model for master receiving (N>255) .................................................529
Figure 20-22. SMBus Master Transmitter and Slave Receiver communication flow ............533
Figure 20-23. SMBus Master Receiver and Slave Transmitter communication flow ............533
Figure 21-1. Block diagram of SPI..............................................................................................................551
Figure 21-2. SPI timing diagram in normal mode.................................................................................552
Figure 21-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0)......................553
Figure 21-4. A typical full-duplex connection........................................................................................556
Figure 21-5. A typical simplex connection (Master: Receive, Slave: Transmit) .....................556
Figure 21-6. A typical simplex connection (Master: Transmit only, Slave: Receive)...........556
Figure 21-7. A typical bidirectional connection....................................................................................556

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Figure 21-8. Timing diagram of TI master mode with discontinuous transfer........................558
Figure 21-9. Timing diagram of TI master mode with continuous transfer...............................559
Figure 21-10. Timing diagram of TI slave mode....................................................................................559
Figure 21-11. Timing diagram of NSS pulse with continuous transmit......................................560
Figure 21-12. Timing diagram of quad write operation in Quad-SPI mode...............................561
Figure 21-13. Timing diagram of quad read operation in Quad-SPI mode................................562
Figure 21-14. Block diagram of I2S.............................................................................................................565
Figure 21-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ........566
Figure 21-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ........567
Figure 21-17. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ........567
Figure 21-18. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ........567
Figure 21-19. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ........567
Figure 21-20. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ........567
Figure 21-21. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ........568
Figure 21-22. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ........568
Figure 21-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ....568
Figure 21-24. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ....568
Figure 21-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ....569
Figure 21-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ....569
Figure 21-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ....569
Figure 21-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1)....569
Figure 21-29. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ....569
Figure 21-30. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ....569
Figure 21-31. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) .....570
Figure 21-32. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) .....570
Figure 21-33. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) .....570
Figure 21-34. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) .....570
Figure 21-35. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0)..................................................................................................................................571
Figure 21-36. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1)..................................................................................................................................571
Figure 21-37. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0)..................................................................................................................................571
Figure 21-38. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1)..................................................................................................................................571
Figure 21-39. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0)..................................................................................................................................571
Figure 21-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1)..................................................................................................................................572
Figure 21-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0)..................................................................................................................................572
Figure 21-42. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1)..................................................................................................................................572
Figure 21-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00,