GigaDevice Semiconductor GD32VW55 Series User manual

GigaDevice Semiconductor Inc.
GD32VW55x
RISC-V 32-bit MCU
For GD32VW553xx
User Manual
Revision 1.0
( Oct. 2023 )

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Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................16
List of Tables ................................................................................................................21
1. System and memory architecture ........................................................................23
1.1. RISC-V processor ...................................................................................................... 23
1.2. System architecture .................................................................................................. 24
1.3. Memory map .............................................................................................................. 25
1.3.1. On-chip SRAM memory........................................................................................................ 29
1.3.2. On-chip flash memory overview ........................................................................................... 29
1.4. Boot configuration..................................................................................................... 29
1.5. System configuration registers (SYSCFG) .............................................................. 32
1.5.1. Configuration register 0 (SYSCFG_CFG0) .......................................................................... 32
1.5.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 32
1.5.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 33
1.5.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 34
1.5.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 34
1.5.6. I/O compensation control register (SYSCFG_CPSCTL) ...................................................... 35
1.5.7. SYSCFG configuration register 1 (SYSCFG_CFG1) ........................................................... 36
1.5.8. SYSCFG shared SRAM configuration register (SYSCFG_SCFG) ...................................... 36
1.5.9. TIMER trigger selection register (SYSCFG_TIMERxCFG)(x = 0..2).................................... 37
1.6. Device electronic signature ...................................................................................... 40
1.6.1. Memory density information.................................................................................................. 40
1.6.2. Unique device ID (96 bits) .................................................................................................... 40
2. Flash memory controller (FMC)............................................................................42
2.1. Overview .................................................................................................................... 42
2.2. Characteristics........................................................................................................... 42
2.3. Function overview..................................................................................................... 42
2.3.1. Flash memory architecture ................................................................................................... 42
2.3.2. Read operations ................................................................................................................... 43
2.3.3. Unlock the FMC_CTL register .............................................................................................. 43
2.3.4. Page erase............................................................................................................................ 44
2.3.5. Mass erase ........................................................................................................................... 45
2.3.6. Main flash programming ....................................................................................................... 46
2.3.7. Option bytes.......................................................................................................................... 48
2.3.8. Security protection ................................................................................................................ 49

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2.3.9. Wirte protection..................................................................................................................... 50
2.3.10. FLASH interrupts .................................................................................................................. 51
2.4. Register definition..................................................................................................... 52
2.4.1. Unlock key register (FMC_KEY)........................................................................................... 52
2.4.2. Option byte unlock key register (FMC_OBKEY)................................................................... 52
2.4.3. Status register (FMC_STAT)................................................................................................. 52
2.4.4. Control register (FMC_CTL) ................................................................................................. 53
2.4.5. Address register (FMC_ADDR) ............................................................................................ 55
2.4.6. Option byte status register (FMC_OBSTAT)......................................................................... 55
2.4.7. Option byte register (FMC_OBR) ......................................................................................... 56
2.4.8. Option byte user value register (FMC_OBUSER) ................................................................ 57
2.4.9. Option byte write protection area register 0 (FMC_OBWRP0)............................................. 57
2.4.10. Option byte write protection area register 1 (FMC_OBWRP1)............................................. 58
2.4.11. NO RTDEC region register x (FMC_NODECx)( x = 0…3) ................................................... 58
2.4.12. Offset region register (FMC_OFRG)..................................................................................... 59
2.4.13. Offset value register (FMC_OFVR) ...................................................................................... 59
2.4.14. Product ID0 register (FMC_PID0)......................................................................................... 60
2.4.15. Product ID1 register (FMC_PID1)......................................................................................... 60
2.4.16. RF Trim register 0 (FMC_RFT0)........................................................................................... 60
2.4.17. RF Trim register 1 (FMC_RFT1)........................................................................................... 61
2.4.18. WIFI Trim register x (FMC_WFTx)( x = 0…15) .................................................................... 61
3. Electronic fuse (EFUSE)........................................................................................63
3.1. Overview .................................................................................................................... 63
3.2. Characteristics........................................................................................................... 63
3.3. Function overview..................................................................................................... 63
3.3.1. Block diagram ....................................................................................................................... 63
3.3.2. Efuse architecture ................................................................................................................. 64
3.3.3. Efuse macro description ....................................................................................................... 64
3.3.4. Read operation ..................................................................................................................... 66
3.3.5. Program operation ................................................................................................................ 66
3.4. Register definition..................................................................................................... 67
3.4.1. Control and status register (EFUSE_CS) ............................................................................. 67
3.4.2. Address register (EFUSE_ADDR) ........................................................................................ 68
3.4.3. Control register 0 (EFUSE_CTL0) ........................................................................................ 69
3.4.4. Control register 1 (EFUSE_CTL1) ........................................................................................ 69
3.4.5. Flash protection control register (EFUSE_FPCTL) .............................................................. 70
3.4.6. User byte control register (EFUSE_USERCTL) ................................................................... 71
3.4.7. EFUSE reserved register x (EFUSE_RESx) (x = 0…2) ....................................................... 72
3.4.8. Firmware AES key register x (EFUSE_AESKEYx) (x = 0…3).............................................. 72
3.4.9. RoTPK key register x (EFUSE_ROTPKKEYx) (x = 0…7).................................................... 72
3.4.10. Product UID register x (EFUSE_PUIDx) (x = 0…3) ............................................................. 73

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3.4.11. HUK key register x (EFUSE_HUKKEYx) (x = 0…3)............................................................. 73
3.4.12. User data register x (EFUSE_USER_DATAx) (x = 0…7) ..................................................... 73
3.4.13. Boot address register (EFUSE_BOOTADDR)...................................................................... 74
4. Power management unit (PMU) ............................................................................75
4.1. Overview .................................................................................................................... 75
4.2. Characteristics........................................................................................................... 75
4.3. Function overview..................................................................................................... 76
4.3.1. Backup domain ..................................................................................................................... 76
4.3.2. VDD / VDDA power domain ...................................................................................................... 77
4.3.3. 1.1V power domain............................................................................................................... 79
4.3.4. Power saving modes ............................................................................................................ 79
4.4. Register definition..................................................................................................... 85
4.4.1. Control register 0 (PMU_CTL0) ............................................................................................ 85
4.4.2. Control and status register 0 (PMU_CS0) ............................................................................ 86
4.4.3. Control register 1 (PMU_CTL1) ............................................................................................ 88
4.4.4. Control and status register 1 (PMU_CS1) ............................................................................ 90
4.4.5. Parameter register 0 (PMU_PAR0) ...................................................................................... 91
4.4.6. Parameter register 1 (PMU_PAR1) ...................................................................................... 92
4.4.7. Parameter register 2 (PMU_PAR2) ...................................................................................... 92
4.4.8. RF Control register (PMU_RFCTL) ...................................................................................... 93
4.4.9. RF timer parameter register (PMU_RFPAR) ........................................................................ 94
4.4.10. PMU interrupt flag register(PMU_INTF) ............................................................................... 95
4.4.11. PMU interrupt enable register(PMU_INTEN) ....................................................................... 95
4.4.12. PMU interrupt clear register(PMU_INTC) ............................................................................. 96
5. Reset and clock unit (RCU)...................................................................................97
5.1. Reset control unit (RCTL) ......................................................................................... 97
5.1.1. Overview ............................................................................................................................... 97
5.1.2. Function overview ................................................................................................................. 97
5.2. Clock control unit (CCTL) ......................................................................................... 98
5.2.1. Overview ............................................................................................................................... 98
5.2.2. Characteristics .................................................................................................................... 100
5.2.3. Function overview ............................................................................................................... 100
5.3. Register definition................................................................................................... 105
5.3.1. Control register (RCU_CTL) ............................................................................................... 105
5.3.2. PLL register (RCU_PLL) ..................................................................................................... 107
5.3.3. Clock configuration register 0 (RCU_CFG0) ...................................................................... 107
5.3.4. Clock interrupt register (RCU_INT) .....................................................................................110
5.3.5. AHB1 reset register (RCU_AHB1RST) ...............................................................................112
5.3.6. AHB2 reset register (RCU_AHB2RST) ...............................................................................113
5.3.7. AHB3 reset register (RCU_AHB3RST) ...............................................................................114

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5.3.8. APB1 reset register (RCU_APB1RST) ................................................................................115
5.3.9. APB2 reset register (RCU_APB2RST) ................................................................................116
5.3.10. AHB1 enable register (RCU_AHB1EN) ...............................................................................118
5.3.11. AHB2 enable register (RCU_AHB2EN) .............................................................................. 120
5.3.12. AHB3 enable register (RCU_AHB3EN) .............................................................................. 120
5.3.13. APB1 enable register (RCU_APB1EN) .............................................................................. 121
5.3.14. APB2 enable register (RCU_APB2EN) .............................................................................. 123
5.3.15. AHB1 sleep mode enable register (RCU_AHB1SPEN) ..................................................... 124
5.3.16. Backup domain control register (RCU_BDCTL) ................................................................. 125
5.3.17. Reset source / clock register (RCU_RSTSCK) .................................................................. 126
5.3.18. PLLDIG clock configuration register 0 (RCU_PLLDIGCFG0) ............................................ 128
5.3.19. Clock configuration register 1 (RCU_CFG1) ...................................................................... 128
5.3.20. Additional clock control register (RCU_ADDCTL) .............................................................. 130
5.3.21. PLLDIG clock configuration register 1 (RCU_PLLDIGCFG1) ............................................ 131
5.3.22. Voltage key register (RCU_VKEY) ..................................................................................... 131
5.3.23. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 132
6. Interrupt / event controller (EXTI).......................................................................133
6.1. Overview .................................................................................................................. 133
6.2. Characteristics......................................................................................................... 133
6.3. Function overview................................................................................................... 133
6.4. External interrupt and event block diagram .......................................................... 136
6.5. External interrupt and event function overview .................................................... 136
6.6. Register definition................................................................................................... 139
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 139
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 139
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 140
6.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 140
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 141
6.6.6. Pending register (EXTI_PD) ............................................................................................... 142
7. General-purpose and alternate-function I/Os (GPIO and AFIO).......................143
7.1. Overview .................................................................................................................. 143
7.2. Characteristics......................................................................................................... 143
7.3. Function overview................................................................................................... 143
7.3.1. GPIO pin configuration ....................................................................................................... 145
7.3.2. External interrupt / event lines ............................................................................................ 145
7.3.3. Alternate functions (AF) ...................................................................................................... 145
7.3.4. Additional functions............................................................................................................. 145
7.3.5. Input configuration .............................................................................................................. 146
7.3.6. Output configuration ........................................................................................................... 146
7.3.7. Analog configuration ........................................................................................................... 147

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7.3.8. Alternate function (AF) configuration .................................................................................. 147
7.3.9. GPIO locking function ......................................................................................................... 148
7.3.10. GPIO I/O compensation cell ............................................................................................... 148
7.3.11. GPIO single cycle toggle function....................................................................................... 148
7.4. Register definition................................................................................................... 149
7.4.1. Port control register (GPIOx_CTL, x = A…C) ..................................................................... 149
7.4.2. Port output mode register (GPIOx_OMODE, x = A...C) ..................................................... 150
7.4.3. Port output speed register (GPIOx_OSPD, x = A...C) ........................................................ 152
7.4.4. Port pull-up/pull-down register (GPIOx_PUD, x = A…C).................................................... 154
7.4.5. Port input status register (GPIOx_ISTAT, x = A...C) ........................................................... 156
7.4.6. Port output control register (GPIOx_OCTL, x = A...C)........................................................ 156
7.4.7. Port bit operate register (GPIOx_BOP, x = A…C) .............................................................. 157
7.4.8. Port configuration lock register (GPIOx_LOCK, x = A…C)................................................. 157
7.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x = A...C).................................... 158
7.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x = A…C) ................................... 159
7.4.11. Bit clear register (GPIOx_BC, x = A...C)............................................................................. 160
7.4.12. Port bit toggle register (GPIOx_TG, x = A…C)................................................................... 161
8. Cyclic redundancy checks management unit (CRC) ........................................162
8.1. Overview .................................................................................................................. 162
8.2. Characteristics......................................................................................................... 162
8.3. Function overview ................................................................................................... 163
8.4. Register definition ................................................................................................... 164
8.4.1. Data register (CRC_DATA) ................................................................................................. 164
8.4.2. Free data register (CRC_FDATA) ....................................................................................... 164
8.4.3. Control register (CRC_CTL) ............................................................................................... 165
9. True random number generator (TRNG) ............................................................166
9.1. Overview .................................................................................................................. 166
9.2. Characteristics......................................................................................................... 166
9.3. Function overview................................................................................................... 166
9.3.1. Operation flow..................................................................................................................... 167
9.3.2. Error flags ........................................................................................................................... 167
9.4. Register definition................................................................................................... 168
9.4.1. Control register (TRNG_CTL)............................................................................................. 168
9.4.2. Status register (TRNG_STAT) ............................................................................................ 168
9.4.3. Data register (TRNG_DATA)............................................................................................... 169
10. Direct memory access controller (DMA).........................................................171
10.1. Overview............................................................................................................... 171
10.2. Characteristics..................................................................................................... 171

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10.3. Block diagram ...................................................................................................... 172
10.4. Function overview................................................................................................ 172
10.4.1. Peripheral handshake......................................................................................................... 174
10.4.2. Data process....................................................................................................................... 175
10.4.3. Address generation............................................................................................................. 180
10.4.4. Circular mode...................................................................................................................... 181
10.4.5. Switch-buffer mode............................................................................................................. 181
10.4.6. Transfer flow controller ....................................................................................................... 182
10.4.7. Transfer operation............................................................................................................... 182
10.4.8. Transfer finish ..................................................................................................................... 183
10.4.9. Channel configuration......................................................................................................... 185
10.5. Interrupts.............................................................................................................. 186
10.5.1. Flag ..................................................................................................................................... 186
10.5.2. Exception ............................................................................................................................ 187
10.5.3. Error .................................................................................................................................... 188
10.6. Register definition................................................................................................ 190
10.6.1. Interrupt flag register 0 (DMA_INTF0) ................................................................................ 190
10.6.2. Interrupt flag register 1 (DMA_INTF1) ................................................................................ 191
10.6.3. Interrupt flag clear register 0 (DMA_INTC0)....................................................................... 191
10.6.4. Interrupt flag clear register 1 (DMA_INTC1)....................................................................... 192
10.6.5. Channel x control register (DMA_CHxCTL) (x = 0..7) ........................................................ 193
10.6.6. Channel x counter register (DMA_CHxCNT) (x = 0..7) ...................................................... 197
10.6.7. Channel x peripheral base address register (DMA_CHxPADDR) (x = 0..7) ...................... 197
10.6.8. Channel x memory 0 base address register (DMA_CHxM0ADDR) (x = 0..7).................... 198
10.6.9. Channel x memory 1 base address register (DMA_CHxM1ADDR) (x = 0..7).................... 198
10.6.10. Channel x FIFO control register (DMA_CHxFCTL) (x = 0..7)............................................. 199
11. Debug (DBG) .....................................................................................................201
11.1. Overview............................................................................................................... 201
11.2. JTAG function overview ...................................................................................... 201
11.2.1. Pin assignment ................................................................................................................... 201
11.2.2. JTAG daisy chained structure............................................................................................. 201
11.2.3. Debug reset ........................................................................................................................ 202
11.3. Debug hold function overview ............................................................................ 202
11.3.1. Debug support for power saving mode............................................................................... 202
11.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and RTC ............................................ 202
11.4. Register definition................................................................................................ 203
11.4.1. ID code register (DBG_ID).................................................................................................. 203
11.4.2. Control register 0 (DBG_CTL0) .......................................................................................... 203
11.4.3. Control register 1 (DBG_CTL1) .......................................................................................... 204
11.4.4. Control register 2 (DBG_CTL2) .......................................................................................... 205

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12. Analog to digital converter (ADC) ...................................................................207
12.1. Overview............................................................................................................... 207
12.2. Characteristics..................................................................................................... 207
12.3. Pins and internal signals..................................................................................... 208
12.4. Function overview................................................................................................ 209
12.4.1. ADC clock .......................................................................................................................... 209
12.4.2. ADCON switch................................................................................................................... 209
12.4.3. Routine sequence............................................................................................................. 209
12.4.4. Operation modes .............................................................................................................. 210
12.4.5. Conversion result threshold monitor function .............................................................. 213
12.4.6. Data storage mode ........................................................................................................... 213
12.4.7. Sampling time configuration ........................................................................................... 214
12.4.8. External trigger configuration ......................................................................................... 214
12.4.9. DMA request ...................................................................................................................... 215
12.4.10. Overflow detection ........................................................................................................... 215
12.4.11. ADC internal channels ..................................................................................................... 215
12.4.12. Programmable resolution (DRES) - fast conversion mode .......................................... 216
12.4.13. On-chip hardware oversampling..................................................................................... 216
12.4.14. ADC interrupts .................................................................................................................. 218
12.5. Register definition................................................................................................ 219
12.5.1. Status register (ADC_STAT) ............................................................................................ 219
12.5.2. Control register 0 (ADC_CTL0)........................................................................................ 220
12.5.3. Control register 1 (ADC_CTL1)........................................................................................ 221
12.5.4. Sample time register 0 (ADC_SAMPT0) ......................................................................... 223
12.5.5. Sample time register 1 (ADC_SAMPT1) ......................................................................... 224
12.5.6. Watchdog high threshold register (ADC_WDHT) .......................................................... 224
12.5.7. Watchdog low threshold register (ADC_WDLT) ............................................................ 225
12.5.8. Routine sequence register 0 (ADC_RSQ0) .................................................................... 225
12.5.9. Routine sequence register 1 (ADC_RSQ1) .................................................................... 226
12.5.10. Routine sequence register 2 (ADC_RSQ2) .................................................................... 226
12.5.11. Routine data register (ADC_RDATA) .............................................................................. 227
12.5.12. Oversampling control register (ADC_OVSAMPCTL) .................................................... 227
12.5.13. Commom control register (ADC_CCTL)......................................................................... 228
13. Watchdog timer (WDGT) ..................................................................................230
13.1. Free watchdog timer (FWDGT)............................................................................ 230
13.1.1. Overview ............................................................................................................................. 230
13.1.2. Characteristics .................................................................................................................... 230
13.1.3. Function overview ............................................................................................................... 230
13.1.4. Register definition ............................................................................................................... 233
13.2. Window watchdog timer (WWDGT)..................................................................... 236
13.2.1. Overview ............................................................................................................................. 236

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13.2.2. Characteristics .................................................................................................................... 236
13.2.3. Function overview ............................................................................................................... 236
13.2.4. Register definition ............................................................................................................... 239
14. Real time clock (RTC).......................................................................................241
14.1. Overview............................................................................................................... 241
14.2. Characteristics..................................................................................................... 241
14.3. Function overview................................................................................................ 242
14.3.1. Block diagram ..................................................................................................................... 242
14.3.2. Clock source and prescalers .............................................................................................. 242
14.3.3. Shadow registers introduction ............................................................................................ 243
14.3.4. Configurable and field maskable alarm .............................................................................. 243
14.3.5. Configurable periodic auto-wakeup counter ....................................................................... 244
14.3.6. RTC initialization and configuration .................................................................................... 244
14.3.7. Calendar reading ................................................................................................................ 245
14.3.8. Resetting the RTC .............................................................................................................. 247
14.3.9. RTC shift function ............................................................................................................... 247
14.3.10. RTC reference clock detection ........................................................................................... 248
14.3.11. RTC coarse digital calibration............................................................................................. 248
14.3.12. RTC smooth digital calibration ............................................................................................ 249
14.3.13. Time-stamp function ........................................................................................................... 251
14.3.14. Tamper detection ................................................................................................................ 251
14.3.15. Calibration clock output ...................................................................................................... 252
14.3.16. Alarm output........................................................................................................................ 253
14.3.17. RTC power saving mode management .............................................................................. 253
14.3.18. RTC interrupts..................................................................................................................... 253
14.4. Register definition................................................................................................ 255
14.4.1. Time register (RTC_TIME).................................................................................................. 255
14.4.2. Date register (RTC_DATE) ................................................................................................. 255
14.4.3. Control register (RTC_CTL)................................................................................................ 256
14.4.4. Status register (RTC_STAT) ............................................................................................... 259
14.4.5. Prescaler register (RTC_PSC) ........................................................................................... 261
14.4.6. Wakeup timer register (RTC_WUT).................................................................................... 261
14.4.7. Coarse calibration register (RTC_COSC)........................................................................... 262
14.4.8. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 263
14.4.9. Alarm 1 time and date register (RTC_ALRM1TD).............................................................. 264
14.4.10. Write protection key register (RTC_WPK) .......................................................................... 265
14.4.11. Sub second register (RTC_SS) .......................................................................................... 265
14.4.12. Shift function control register (RTC_SHIFTCTL) ................................................................ 266
14.4.13. Time of time stamp register (RTC_TTS)............................................................................. 266
14.4.14. Date of time stamp register (RTC_DTS)............................................................................. 267
14.4.15. Sub second of time stamp register (RTC_SSTS) ............................................................... 268
14.4.16. High resolution frequency compensation register (RTC_HRFC) ....................................... 268

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14.4.17. Tamper register (RTC_TAMP) ............................................................................................ 269
14.4.18. Alarm 0 sub second register (RTC_ALRM0SS) ................................................................. 271
14.4.19. Alarm 1 sub second register (RTC_ALRM1SS) ................................................................. 272
14.4.20. Backup registers (RTC_BKPx) (x = 0…19) ........................................................................ 273
15. Timer (TIMERx) .................................................................................................275
15.1. Advanced timer (TIMERx, x=0) ............................................................................ 276
15.1.1. Overview ............................................................................................................................. 276
15.1.2. Characteristics .................................................................................................................... 276
15.1.3. Block diagram ..................................................................................................................... 277
15.1.4. Function overview ............................................................................................................... 277
15.1.5. TIMERx registers(x=0)........................................................................................................ 305
15.2. General level0 timer (TIMERx, x=1, 2) ................................................................. 332
15.2.1. Overview ............................................................................................................................. 332
15.2.2. Characteristics .................................................................................................................... 332
15.2.3. Block diagram ..................................................................................................................... 332
15.2.4. Function overview ............................................................................................................... 333
15.2.5. TIMERx registers(x=1, 2).................................................................................................... 349
15.3. General level4 timer (TIMERx, x=15,16) .............................................................. 372
15.3.1. Overview ............................................................................................................................. 372
15.3.2. Characteristics .................................................................................................................... 372
15.3.3. Block diagram ..................................................................................................................... 372
15.3.4. Function overview ............................................................................................................... 373
15.3.5. TIMERx registers(x=15, 16)................................................................................................ 387
15.4. Basic timer (TIMERx, x=5) ................................................................................... 403
15.4.1. Overview ............................................................................................................................. 403
15.4.2. Characteristics .................................................................................................................... 403
15.4.3. Block diagram ..................................................................................................................... 403
15.4.4. Function overview ............................................................................................................... 403
15.4.5. TIMERx registers(x=5)........................................................................................................ 407
16. Universal synchronous/asynchronous receiver /transmitter (USART)........412
16.1. Overview............................................................................................................... 412
16.2. Characteristics..................................................................................................... 412
16.3. Function overview................................................................................................ 414
16.3.1. USART frame format .......................................................................................................... 414
16.3.2. Baud rate generation .......................................................................................................... 415
16.3.3. USART transmitter.............................................................................................................. 416
16.3.4. USART receiver .................................................................................................................. 417
16.3.5. Use DMA for data buffer access ......................................................................................... 419
16.3.6. Hardware flow control ......................................................................................................... 420
16.3.7. Multi-processor communication .......................................................................................... 421