GigaDevice Semiconductor GD32VW55 Series User manual

GigaDevice Semiconductor Inc.
GD32VW55x
RISC-V 32-bit MCU
For GD32VW553xx
User Manual
Revision 1.0
( Oct. 2023 )

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Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................16
List of Tables ................................................................................................................21
1. System and memory architecture ........................................................................23
1.1. RISC-V processor ...................................................................................................... 23
1.2. System architecture .................................................................................................. 24
1.3. Memory map .............................................................................................................. 25
1.3.1. On-chip SRAM memory........................................................................................................ 29
1.3.2. On-chip flash memory overview ........................................................................................... 29
1.4. Boot configuration..................................................................................................... 29
1.5. System configuration registers (SYSCFG) .............................................................. 32
1.5.1. Configuration register 0 (SYSCFG_CFG0) .......................................................................... 32
1.5.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 32
1.5.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 33
1.5.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 34
1.5.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 34
1.5.6. I/O compensation control register (SYSCFG_CPSCTL) ...................................................... 35
1.5.7. SYSCFG configuration register 1 (SYSCFG_CFG1) ........................................................... 36
1.5.8. SYSCFG shared SRAM configuration register (SYSCFG_SCFG) ...................................... 36
1.5.9. TIMER trigger selection register (SYSCFG_TIMERxCFG)(x = 0..2).................................... 37
1.6. Device electronic signature ...................................................................................... 40
1.6.1. Memory density information.................................................................................................. 40
1.6.2. Unique device ID (96 bits) .................................................................................................... 40
2. Flash memory controller (FMC)............................................................................42
2.1. Overview .................................................................................................................... 42
2.2. Characteristics........................................................................................................... 42
2.3. Function overview..................................................................................................... 42
2.3.1. Flash memory architecture ................................................................................................... 42
2.3.2. Read operations ................................................................................................................... 43
2.3.3. Unlock the FMC_CTL register .............................................................................................. 43
2.3.4. Page erase............................................................................................................................ 44
2.3.5. Mass erase ........................................................................................................................... 45
2.3.6. Main flash programming ....................................................................................................... 46
2.3.7. Option bytes.......................................................................................................................... 48
2.3.8. Security protection ................................................................................................................ 49

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2.3.9. Wirte protection..................................................................................................................... 50
2.3.10. FLASH interrupts .................................................................................................................. 51
2.4. Register definition..................................................................................................... 52
2.4.1. Unlock key register (FMC_KEY)........................................................................................... 52
2.4.2. Option byte unlock key register (FMC_OBKEY)................................................................... 52
2.4.3. Status register (FMC_STAT)................................................................................................. 52
2.4.4. Control register (FMC_CTL) ................................................................................................. 53
2.4.5. Address register (FMC_ADDR) ............................................................................................ 55
2.4.6. Option byte status register (FMC_OBSTAT)......................................................................... 55
2.4.7. Option byte register (FMC_OBR) ......................................................................................... 56
2.4.8. Option byte user value register (FMC_OBUSER) ................................................................ 57
2.4.9. Option byte write protection area register 0 (FMC_OBWRP0)............................................. 57
2.4.10. Option byte write protection area register 1 (FMC_OBWRP1)............................................. 58
2.4.11. NO RTDEC region register x (FMC_NODECx)( x = 0…3) ................................................... 58
2.4.12. Offset region register (FMC_OFRG)..................................................................................... 59
2.4.13. Offset value register (FMC_OFVR) ...................................................................................... 59
2.4.14. Product ID0 register (FMC_PID0)......................................................................................... 60
2.4.15. Product ID1 register (FMC_PID1)......................................................................................... 60
2.4.16. RF Trim register 0 (FMC_RFT0)........................................................................................... 60
2.4.17. RF Trim register 1 (FMC_RFT1)........................................................................................... 61
2.4.18. WIFI Trim register x (FMC_WFTx)( x = 0…15) .................................................................... 61
3. Electronic fuse (EFUSE)........................................................................................63
3.1. Overview .................................................................................................................... 63
3.2. Characteristics........................................................................................................... 63
3.3. Function overview..................................................................................................... 63
3.3.1. Block diagram ....................................................................................................................... 63
3.3.2. Efuse architecture ................................................................................................................. 64
3.3.3. Efuse macro description ....................................................................................................... 64
3.3.4. Read operation ..................................................................................................................... 66
3.3.5. Program operation ................................................................................................................ 66
3.4. Register definition..................................................................................................... 67
3.4.1. Control and status register (EFUSE_CS) ............................................................................. 67
3.4.2. Address register (EFUSE_ADDR) ........................................................................................ 68
3.4.3. Control register 0 (EFUSE_CTL0) ........................................................................................ 69
3.4.4. Control register 1 (EFUSE_CTL1) ........................................................................................ 69
3.4.5. Flash protection control register (EFUSE_FPCTL) .............................................................. 70
3.4.6. User byte control register (EFUSE_USERCTL) ................................................................... 71
3.4.7. EFUSE reserved register x (EFUSE_RESx) (x = 0…2) ....................................................... 72
3.4.8. Firmware AES key register x (EFUSE_AESKEYx) (x = 0…3).............................................. 72
3.4.9. RoTPK key register x (EFUSE_ROTPKKEYx) (x = 0…7).................................................... 72
3.4.10. Product UID register x (EFUSE_PUIDx) (x = 0…3) ............................................................. 73

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3.4.11. HUK key register x (EFUSE_HUKKEYx) (x = 0…3)............................................................. 73
3.4.12. User data register x (EFUSE_USER_DATAx) (x = 0…7) ..................................................... 73
3.4.13. Boot address register (EFUSE_BOOTADDR)...................................................................... 74
4. Power management unit (PMU) ............................................................................75
4.1. Overview .................................................................................................................... 75
4.2. Characteristics........................................................................................................... 75
4.3. Function overview..................................................................................................... 76
4.3.1. Backup domain ..................................................................................................................... 76
4.3.2. VDD / VDDA power domain ...................................................................................................... 77
4.3.3. 1.1V power domain............................................................................................................... 79
4.3.4. Power saving modes ............................................................................................................ 79
4.4. Register definition..................................................................................................... 85
4.4.1. Control register 0 (PMU_CTL0) ............................................................................................ 85
4.4.2. Control and status register 0 (PMU_CS0) ............................................................................ 86
4.4.3. Control register 1 (PMU_CTL1) ............................................................................................ 88
4.4.4. Control and status register 1 (PMU_CS1) ............................................................................ 90
4.4.5. Parameter register 0 (PMU_PAR0) ...................................................................................... 91
4.4.6. Parameter register 1 (PMU_PAR1) ...................................................................................... 92
4.4.7. Parameter register 2 (PMU_PAR2) ...................................................................................... 92
4.4.8. RF Control register (PMU_RFCTL) ...................................................................................... 93
4.4.9. RF timer parameter register (PMU_RFPAR) ........................................................................ 94
4.4.10. PMU interrupt flag register(PMU_INTF) ............................................................................... 95
4.4.11. PMU interrupt enable register(PMU_INTEN) ....................................................................... 95
4.4.12. PMU interrupt clear register(PMU_INTC) ............................................................................. 96
5. Reset and clock unit (RCU)...................................................................................97
5.1. Reset control unit (RCTL) ......................................................................................... 97
5.1.1. Overview ............................................................................................................................... 97
5.1.2. Function overview ................................................................................................................. 97
5.2. Clock control unit (CCTL) ......................................................................................... 98
5.2.1. Overview ............................................................................................................................... 98
5.2.2. Characteristics .................................................................................................................... 100
5.2.3. Function overview ............................................................................................................... 100
5.3. Register definition................................................................................................... 105
5.3.1. Control register (RCU_CTL) ............................................................................................... 105
5.3.2. PLL register (RCU_PLL) ..................................................................................................... 107
5.3.3. Clock configuration register 0 (RCU_CFG0) ...................................................................... 107
5.3.4. Clock interrupt register (RCU_INT) .....................................................................................110
5.3.5. AHB1 reset register (RCU_AHB1RST) ...............................................................................112
5.3.6. AHB2 reset register (RCU_AHB2RST) ...............................................................................113
5.3.7. AHB3 reset register (RCU_AHB3RST) ...............................................................................114

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5.3.8. APB1 reset register (RCU_APB1RST) ................................................................................115
5.3.9. APB2 reset register (RCU_APB2RST) ................................................................................116
5.3.10. AHB1 enable register (RCU_AHB1EN) ...............................................................................118
5.3.11. AHB2 enable register (RCU_AHB2EN) .............................................................................. 120
5.3.12. AHB3 enable register (RCU_AHB3EN) .............................................................................. 120
5.3.13. APB1 enable register (RCU_APB1EN) .............................................................................. 121
5.3.14. APB2 enable register (RCU_APB2EN) .............................................................................. 123
5.3.15. AHB1 sleep mode enable register (RCU_AHB1SPEN) ..................................................... 124
5.3.16. Backup domain control register (RCU_BDCTL) ................................................................. 125
5.3.17. Reset source / clock register (RCU_RSTSCK) .................................................................. 126
5.3.18. PLLDIG clock configuration register 0 (RCU_PLLDIGCFG0) ............................................ 128
5.3.19. Clock configuration register 1 (RCU_CFG1) ...................................................................... 128
5.3.20. Additional clock control register (RCU_ADDCTL) .............................................................. 130
5.3.21. PLLDIG clock configuration register 1 (RCU_PLLDIGCFG1) ............................................ 131
5.3.22. Voltage key register (RCU_VKEY) ..................................................................................... 131
5.3.23. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 132
6. Interrupt / event controller (EXTI).......................................................................133
6.1. Overview .................................................................................................................. 133
6.2. Characteristics......................................................................................................... 133
6.3. Function overview................................................................................................... 133
6.4. External interrupt and event block diagram .......................................................... 136
6.5. External interrupt and event function overview .................................................... 136
6.6. Register definition................................................................................................... 139
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 139
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 139
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 140
6.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 140
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 141
6.6.6. Pending register (EXTI_PD) ............................................................................................... 142
7. General-purpose and alternate-function I/Os (GPIO and AFIO).......................143
7.1. Overview .................................................................................................................. 143
7.2. Characteristics......................................................................................................... 143
7.3. Function overview................................................................................................... 143
7.3.1. GPIO pin configuration ....................................................................................................... 145
7.3.2. External interrupt / event lines ............................................................................................ 145
7.3.3. Alternate functions (AF) ...................................................................................................... 145
7.3.4. Additional functions............................................................................................................. 145
7.3.5. Input configuration .............................................................................................................. 146
7.3.6. Output configuration ........................................................................................................... 146
7.3.7. Analog configuration ........................................................................................................... 147

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7.3.8. Alternate function (AF) configuration .................................................................................. 147
7.3.9. GPIO locking function ......................................................................................................... 148
7.3.10. GPIO I/O compensation cell ............................................................................................... 148
7.3.11. GPIO single cycle toggle function....................................................................................... 148
7.4. Register definition................................................................................................... 149
7.4.1. Port control register (GPIOx_CTL, x = A…C) ..................................................................... 149
7.4.2. Port output mode register (GPIOx_OMODE, x = A...C) ..................................................... 150
7.4.3. Port output speed register (GPIOx_OSPD, x = A...C) ........................................................ 152
7.4.4. Port pull-up/pull-down register (GPIOx_PUD, x = A…C).................................................... 154
7.4.5. Port input status register (GPIOx_ISTAT, x = A...C) ........................................................... 156
7.4.6. Port output control register (GPIOx_OCTL, x = A...C)........................................................ 156
7.4.7. Port bit operate register (GPIOx_BOP, x = A…C) .............................................................. 157
7.4.8. Port configuration lock register (GPIOx_LOCK, x = A…C)................................................. 157
7.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x = A...C).................................... 158
7.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x = A…C) ................................... 159
7.4.11. Bit clear register (GPIOx_BC, x = A...C)............................................................................. 160
7.4.12. Port bit toggle register (GPIOx_TG, x = A…C)................................................................... 161
8. Cyclic redundancy checks management unit (CRC) ........................................162
8.1. Overview .................................................................................................................. 162
8.2. Characteristics......................................................................................................... 162
8.3. Function overview ................................................................................................... 163
8.4. Register definition ................................................................................................... 164
8.4.1. Data register (CRC_DATA) ................................................................................................. 164
8.4.2. Free data register (CRC_FDATA) ....................................................................................... 164
8.4.3. Control register (CRC_CTL) ............................................................................................... 165
9. True random number generator (TRNG) ............................................................166
9.1. Overview .................................................................................................................. 166
9.2. Characteristics......................................................................................................... 166
9.3. Function overview................................................................................................... 166
9.3.1. Operation flow..................................................................................................................... 167
9.3.2. Error flags ........................................................................................................................... 167
9.4. Register definition................................................................................................... 168
9.4.1. Control register (TRNG_CTL)............................................................................................. 168
9.4.2. Status register (TRNG_STAT) ............................................................................................ 168
9.4.3. Data register (TRNG_DATA)............................................................................................... 169
10. Direct memory access controller (DMA).........................................................171
10.1. Overview............................................................................................................... 171
10.2. Characteristics..................................................................................................... 171

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10.3. Block diagram ...................................................................................................... 172
10.4. Function overview................................................................................................ 172
10.4.1. Peripheral handshake......................................................................................................... 174
10.4.2. Data process....................................................................................................................... 175
10.4.3. Address generation............................................................................................................. 180
10.4.4. Circular mode...................................................................................................................... 181
10.4.5. Switch-buffer mode............................................................................................................. 181
10.4.6. Transfer flow controller ....................................................................................................... 182
10.4.7. Transfer operation............................................................................................................... 182
10.4.8. Transfer finish ..................................................................................................................... 183
10.4.9. Channel configuration......................................................................................................... 185
10.5. Interrupts.............................................................................................................. 186
10.5.1. Flag ..................................................................................................................................... 186
10.5.2. Exception ............................................................................................................................ 187
10.5.3. Error .................................................................................................................................... 188
10.6. Register definition................................................................................................ 190
10.6.1. Interrupt flag register 0 (DMA_INTF0) ................................................................................ 190
10.6.2. Interrupt flag register 1 (DMA_INTF1) ................................................................................ 191
10.6.3. Interrupt flag clear register 0 (DMA_INTC0)....................................................................... 191
10.6.4. Interrupt flag clear register 1 (DMA_INTC1)....................................................................... 192
10.6.5. Channel x control register (DMA_CHxCTL) (x = 0..7) ........................................................ 193
10.6.6. Channel x counter register (DMA_CHxCNT) (x = 0..7) ...................................................... 197
10.6.7. Channel x peripheral base address register (DMA_CHxPADDR) (x = 0..7) ...................... 197
10.6.8. Channel x memory 0 base address register (DMA_CHxM0ADDR) (x = 0..7).................... 198
10.6.9. Channel x memory 1 base address register (DMA_CHxM1ADDR) (x = 0..7).................... 198
10.6.10. Channel x FIFO control register (DMA_CHxFCTL) (x = 0..7)............................................. 199
11. Debug (DBG) .....................................................................................................201
11.1. Overview............................................................................................................... 201
11.2. JTAG function overview ...................................................................................... 201
11.2.1. Pin assignment ................................................................................................................... 201
11.2.2. JTAG daisy chained structure............................................................................................. 201
11.2.3. Debug reset ........................................................................................................................ 202
11.3. Debug hold function overview ............................................................................ 202
11.3.1. Debug support for power saving mode............................................................................... 202
11.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and RTC ............................................ 202
11.4. Register definition................................................................................................ 203
11.4.1. ID code register (DBG_ID).................................................................................................. 203
11.4.2. Control register 0 (DBG_CTL0) .......................................................................................... 203
11.4.3. Control register 1 (DBG_CTL1) .......................................................................................... 204
11.4.4. Control register 2 (DBG_CTL2) .......................................................................................... 205

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12. Analog to digital converter (ADC) ...................................................................207
12.1. Overview............................................................................................................... 207
12.2. Characteristics..................................................................................................... 207
12.3. Pins and internal signals..................................................................................... 208
12.4. Function overview................................................................................................ 209
12.4.1. ADC clock .......................................................................................................................... 209
12.4.2. ADCON switch................................................................................................................... 209
12.4.3. Routine sequence............................................................................................................. 209
12.4.4. Operation modes .............................................................................................................. 210
12.4.5. Conversion result threshold monitor function .............................................................. 213
12.4.6. Data storage mode ........................................................................................................... 213
12.4.7. Sampling time configuration ........................................................................................... 214
12.4.8. External trigger configuration ......................................................................................... 214
12.4.9. DMA request ...................................................................................................................... 215
12.4.10. Overflow detection ........................................................................................................... 215
12.4.11. ADC internal channels ..................................................................................................... 215
12.4.12. Programmable resolution (DRES) - fast conversion mode .......................................... 216
12.4.13. On-chip hardware oversampling..................................................................................... 216
12.4.14. ADC interrupts .................................................................................................................. 218
12.5. Register definition................................................................................................ 219
12.5.1. Status register (ADC_STAT) ............................................................................................ 219
12.5.2. Control register 0 (ADC_CTL0)........................................................................................ 220
12.5.3. Control register 1 (ADC_CTL1)........................................................................................ 221
12.5.4. Sample time register 0 (ADC_SAMPT0) ......................................................................... 223
12.5.5. Sample time register 1 (ADC_SAMPT1) ......................................................................... 224
12.5.6. Watchdog high threshold register (ADC_WDHT) .......................................................... 224
12.5.7. Watchdog low threshold register (ADC_WDLT) ............................................................ 225
12.5.8. Routine sequence register 0 (ADC_RSQ0) .................................................................... 225
12.5.9. Routine sequence register 1 (ADC_RSQ1) .................................................................... 226
12.5.10. Routine sequence register 2 (ADC_RSQ2) .................................................................... 226
12.5.11. Routine data register (ADC_RDATA) .............................................................................. 227
12.5.12. Oversampling control register (ADC_OVSAMPCTL) .................................................... 227
12.5.13. Commom control register (ADC_CCTL)......................................................................... 228
13. Watchdog timer (WDGT) ..................................................................................230
13.1. Free watchdog timer (FWDGT)............................................................................ 230
13.1.1. Overview ............................................................................................................................. 230
13.1.2. Characteristics .................................................................................................................... 230
13.1.3. Function overview ............................................................................................................... 230
13.1.4. Register definition ............................................................................................................... 233
13.2. Window watchdog timer (WWDGT)..................................................................... 236
13.2.1. Overview ............................................................................................................................. 236

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13.2.2. Characteristics .................................................................................................................... 236
13.2.3. Function overview ............................................................................................................... 236
13.2.4. Register definition ............................................................................................................... 239
14. Real time clock (RTC).......................................................................................241
14.1. Overview............................................................................................................... 241
14.2. Characteristics..................................................................................................... 241
14.3. Function overview................................................................................................ 242
14.3.1. Block diagram ..................................................................................................................... 242
14.3.2. Clock source and prescalers .............................................................................................. 242
14.3.3. Shadow registers introduction ............................................................................................ 243
14.3.4. Configurable and field maskable alarm .............................................................................. 243
14.3.5. Configurable periodic auto-wakeup counter ....................................................................... 244
14.3.6. RTC initialization and configuration .................................................................................... 244
14.3.7. Calendar reading ................................................................................................................ 245
14.3.8. Resetting the RTC .............................................................................................................. 247
14.3.9. RTC shift function ............................................................................................................... 247
14.3.10. RTC reference clock detection ........................................................................................... 248
14.3.11. RTC coarse digital calibration............................................................................................. 248
14.3.12. RTC smooth digital calibration ............................................................................................ 249
14.3.13. Time-stamp function ........................................................................................................... 251
14.3.14. Tamper detection ................................................................................................................ 251
14.3.15. Calibration clock output ...................................................................................................... 252
14.3.16. Alarm output........................................................................................................................ 253
14.3.17. RTC power saving mode management .............................................................................. 253
14.3.18. RTC interrupts..................................................................................................................... 253
14.4. Register definition................................................................................................ 255
14.4.1. Time register (RTC_TIME).................................................................................................. 255
14.4.2. Date register (RTC_DATE) ................................................................................................. 255
14.4.3. Control register (RTC_CTL)................................................................................................ 256
14.4.4. Status register (RTC_STAT) ............................................................................................... 259
14.4.5. Prescaler register (RTC_PSC) ........................................................................................... 261
14.4.6. Wakeup timer register (RTC_WUT).................................................................................... 261
14.4.7. Coarse calibration register (RTC_COSC)........................................................................... 262
14.4.8. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 263
14.4.9. Alarm 1 time and date register (RTC_ALRM1TD).............................................................. 264
14.4.10. Write protection key register (RTC_WPK) .......................................................................... 265
14.4.11. Sub second register (RTC_SS) .......................................................................................... 265
14.4.12. Shift function control register (RTC_SHIFTCTL) ................................................................ 266
14.4.13. Time of time stamp register (RTC_TTS)............................................................................. 266
14.4.14. Date of time stamp register (RTC_DTS)............................................................................. 267
14.4.15. Sub second of time stamp register (RTC_SSTS) ............................................................... 268
14.4.16. High resolution frequency compensation register (RTC_HRFC) ....................................... 268

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14.4.17. Tamper register (RTC_TAMP) ............................................................................................ 269
14.4.18. Alarm 0 sub second register (RTC_ALRM0SS) ................................................................. 271
14.4.19. Alarm 1 sub second register (RTC_ALRM1SS) ................................................................. 272
14.4.20. Backup registers (RTC_BKPx) (x = 0…19) ........................................................................ 273
15. Timer (TIMERx) .................................................................................................275
15.1. Advanced timer (TIMERx, x=0) ............................................................................ 276
15.1.1. Overview ............................................................................................................................. 276
15.1.2. Characteristics .................................................................................................................... 276
15.1.3. Block diagram ..................................................................................................................... 277
15.1.4. Function overview ............................................................................................................... 277
15.1.5. TIMERx registers(x=0)........................................................................................................ 305
15.2. General level0 timer (TIMERx, x=1, 2) ................................................................. 332
15.2.1. Overview ............................................................................................................................. 332
15.2.2. Characteristics .................................................................................................................... 332
15.2.3. Block diagram ..................................................................................................................... 332
15.2.4. Function overview ............................................................................................................... 333
15.2.5. TIMERx registers(x=1, 2).................................................................................................... 349
15.3. General level4 timer (TIMERx, x=15,16) .............................................................. 372
15.3.1. Overview ............................................................................................................................. 372
15.3.2. Characteristics .................................................................................................................... 372
15.3.3. Block diagram ..................................................................................................................... 372
15.3.4. Function overview ............................................................................................................... 373
15.3.5. TIMERx registers(x=15, 16)................................................................................................ 387
15.4. Basic timer (TIMERx, x=5) ................................................................................... 403
15.4.1. Overview ............................................................................................................................. 403
15.4.2. Characteristics .................................................................................................................... 403
15.4.3. Block diagram ..................................................................................................................... 403
15.4.4. Function overview ............................................................................................................... 403
15.4.5. TIMERx registers(x=5)........................................................................................................ 407
16. Universal synchronous/asynchronous receiver /transmitter (USART)........412
16.1. Overview............................................................................................................... 412
16.2. Characteristics..................................................................................................... 412
16.3. Function overview................................................................................................ 414
16.3.1. USART frame format .......................................................................................................... 414
16.3.2. Baud rate generation .......................................................................................................... 415
16.3.3. USART transmitter.............................................................................................................. 416
16.3.4. USART receiver .................................................................................................................. 417
16.3.5. Use DMA for data buffer access ......................................................................................... 419
16.3.6. Hardware flow control ......................................................................................................... 420
16.3.7. Multi-processor communication .......................................................................................... 421

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16.3.8. LIN mode ............................................................................................................................ 422
16.3.9. Synchronous mode............................................................................................................. 423
16.3.10. IrDA SIR ENDEC mode ...................................................................................................... 424
16.3.11. Half-duplex communication mode ...................................................................................... 426
16.3.12. Smartcard (ISO7816-3) mode ............................................................................................ 426
16.3.13. ModBus communication ..................................................................................................... 428
16.3.14. Receive FIFO...................................................................................................................... 428
16.3.15. Wakeup from deep-sleep mode.......................................................................................... 429
16.3.16. USART interrupts................................................................................................................ 429
16.4. Register definition................................................................................................ 432
16.4.1. Control register 0 (USART_CTL0)...................................................................................... 432
16.4.2. Control register 1 (USART_CTL1)...................................................................................... 434
16.4.3. Control register 2 (USART_CTL2)...................................................................................... 437
16.4.4. Baud rate generator register (USART_BAUD) ................................................................... 440
16.4.5. Prescaler and guard time configuration register (USART_GP) .......................................... 440
16.4.6. Receiver timeout register (USART_RT) ............................................................................. 441
16.4.7. Command register (USART_CMD) .................................................................................... 442
16.4.8. Status register (USART_STAT) .......................................................................................... 443
16.4.9. Interrupt status clear register (USART_INTC).................................................................... 446
16.4.10. Receive data register (USART_RDATA) ............................................................................ 448
16.4.11. Transmit data register (USART_TDATA) ............................................................................ 448
16.4.12. USART coherence control register (USART_CHC)............................................................ 449
16.4.13. USART receive FIFO control and status register (USART_RFCS).................................... 449
17. Inter-integrated circuit interface (I2C).............................................................451
17.1. Overview............................................................................................................... 451
17.2. Characteristics..................................................................................................... 451
17.3. Function overview................................................................................................ 451
17.3.1. Clock requirements............................................................................................................. 452
17.3.2. I2C communication flow...................................................................................................... 453
17.3.3. Noise filter ........................................................................................................................... 456
17.3.4. I2C timings .......................................................................................................................... 456
17.3.5. Software reset..................................................................................................................... 458
17.3.6. Data transfer ....................................................................................................................... 458
17.3.7. I2C slave mode................................................................................................................... 461
17.3.8. I2C master mode ................................................................................................................ 466
17.3.9. SMBus support ................................................................................................................... 471
17.3.10. SMBus mode ...................................................................................................................... 474
17.3.11. Wakeup from Deep-sleep mode ......................................................................................... 476
17.3.12. Use DMA for data transfer .................................................................................................. 476
17.3.13. I2C error and interrupts....................................................................................................... 477
17.3.14. I2C debug mode ................................................................................................................. 477

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17.4. Register definition................................................................................................ 478
17.4.1. Control register 0 (I2C_CTL0) ............................................................................................ 478
17.4.2. Control register 1 (I2C_CTL1) ............................................................................................ 480
17.4.3. Slave address register 0 (I2C_SADDR0) ........................................................................... 482
17.4.4. Slave address register 1 (I2C_SADDR1) ........................................................................... 483
17.4.5. Timing register (I2C_TIMING) ............................................................................................ 484
17.4.6. Timeout register (I2C_TIMEOUT)....................................................................................... 485
17.4.7. Status register (I2C_STAT) ................................................................................................. 486
17.4.8. Status clear register (I2C_STATC) ..................................................................................... 489
17.4.9. PEC register (I2C_PEC) ..................................................................................................... 490
17.4.10. Receive data register (I2C_RDATA) ................................................................................... 490
17.4.11. Transmit data register (I2C_TDATA)................................................................................... 490
17.4.12. Control register 2 (I2C_CTL2) ............................................................................................ 491
18. Serial peripheral interface (SPI).......................................................................492
18.1. Overview............................................................................................................... 492
18.2. Characteristics..................................................................................................... 492
18.2.1. SPI characteristics .............................................................................................................. 492
18.3. SPI function overview.......................................................................................... 492
18.3.1. SPI block diagram............................................................................................................... 492
18.3.2. SPI signal description ......................................................................................................... 493
18.3.3. SPI clock timing and data format ........................................................................................ 493
18.3.4. NSS function ....................................................................................................................... 494
18.3.5. SPI operating modes .......................................................................................................... 495
18.3.6. DMA function....................................................................................................................... 501
18.3.7. CRC function....................................................................................................................... 501
18.3.8. SPI interrupts ...................................................................................................................... 502
18.4. Register definition................................................................................................ 504
18.4.1. Control register 0 (SPI_CTL0) ............................................................................................ 504
18.4.2. Control register 1 (SPI_CTL1) ............................................................................................ 506
18.4.3. Status register (SPI_STAT)................................................................................................. 507
18.4.4. Data register (SPI_DATA) ................................................................................................... 508
18.4.5. CRC polynomial register (SPI_CRCPOLY) ........................................................................ 508
18.4.6. RX CRC register (SPI_RCRC) ........................................................................................... 509
18.4.7. TX CRC register (SPI_TCRC) ............................................................................................ 510
19. Quad-SPI interface (QSPI)................................................................................ 511
19.1. Overview................................................................................................................511
19.2. Characteristics......................................................................................................511
19.3. Function overview.................................................................................................511
19.3.1. QSPI block diagram.............................................................................................................511
19.3.2. QSPI command format ....................................................................................................... 512

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19.3.3. QSPI signal line modes ...................................................................................................... 514
19.3.4. CSN and SCK ..................................................................................................................... 514
19.4. Operating modes.................................................................................................. 514
19.4.1. Normal mode ...................................................................................................................... 515
19.4.2. Read polling mode.............................................................................................................. 516
19.4.3. Memory map mode............................................................................................................. 517
19.5. QSPI configuration............................................................................................... 517
19.5.1. Flash configuration ............................................................................................................. 517
19.5.2. IP configuration ................................................................................................................... 517
19.6. Send instruction only once ................................................................................. 518
19.7. Error and interrupts ............................................................................................. 518
19.8. Register definition................................................................................................ 520
19.8.1. Control register (QSPI_CTL) .............................................................................................. 520
19.8.2. Device configuration register (QSPI_DCFG)...................................................................... 522
19.8.3. Status register (QSPI_STAT) .............................................................................................. 523
19.8.4. Status clear register (QSPI_STATC) .................................................................................. 524
19.8.5. Data length register (QSPI_DTLEN)................................................................................... 525
19.8.6. Transfer configuration register (QSPI_TCFG) .................................................................... 526
19.8.7. Address register (QSPI_ADDR) ......................................................................................... 528
19.8.8. Alternate bytes register (QSPI_ALTE) ................................................................................ 528
19.8.9. Data register (QSPI_DATA) ................................................................................................ 528
19.8.10. Status mask register (QSPI_STATMK)............................................................................... 529
19.8.11. Status match register (QSPI_STATMATCH) ...................................................................... 529
19.8.12. Interval register (QSPI_INTERVAL).................................................................................... 530
19.8.13. Timeout register (QSPI_TMOUT) ....................................................................................... 530
19.8.14. FIFO flush register (QSPI_FLUSH) .................................................................................... 531
20. Cryptographic Acceleration Unit (CAU)..........................................................532
20.1. Overview............................................................................................................... 532
20.2. Characteristics..................................................................................................... 532
20.3. CAU data type and initialization vectors ............................................................ 533
20.3.1. Data type............................................................................................................................. 533
20.3.2. Initialization vectors ............................................................................................................ 534
20.4. Cryptographic acceleration processor............................................................... 534
20.4.1. DES / TDES cryptographic acceleration processor............................................................ 535
20.4.2. AES cryptographic acceleration processor......................................................................... 539
20.5. Operating modes.................................................................................................. 546
20.6. CAU DMA interface .............................................................................................. 547
20.7. CAU interrupts...................................................................................................... 547

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20.8. CAU suspended mode......................................................................................... 548
20.9. Register definition................................................................................................ 550
20.9.1. Control register (CAU_CTL) ............................................................................................... 550
20.9.2. Status register 0 (CAU_STAT0) .......................................................................................... 551
20.9.3. Data input register (CAU_DI).............................................................................................. 552
20.9.4. Data output register (CAU_DO).......................................................................................... 553
20.9.5. DMA enable register (CAU_DMAEN) ................................................................................. 553
20.9.6. Interrupt enable register (CAU_INTEN).............................................................................. 554
20.9.7. Status register 1 (CAU_STAT1) .......................................................................................... 554
20.9.8. Interrupt flag register (CAU_INTF)...................................................................................... 555
20.9.9. Key registers (CAU_KEY0…3(H / L)) ................................................................................. 555
20.9.10. Initial vector registers (CAU_IV0…1(H / L))........................................................................ 558
20.9.11. GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) (x = 0…7) .......... 559
20.9.12. GCM mode context switch register x (CAU_GCMCTXSx) (x = 0…7)................................ 560
21. Hash Acceleration Unit (HAU) .........................................................................561
21.1. Overview............................................................................................................... 561
21.2. Characteristics..................................................................................................... 561
21.3. HAU data type....................................................................................................... 561
21.4. HAU core............................................................................................................... 563
21.4.1. Automatic data padding ...................................................................................................... 563
21.4.2. Digest computing ................................................................................................................ 564
21.4.3. Hash mode.......................................................................................................................... 565
21.4.4. HMAC mode ....................................................................................................................... 565
21.5. HAU suspended mode......................................................................................... 565
21.5.1. Transfer data by CPU ......................................................................................................... 566
21.5.2. Transfer data by DMA......................................................................................................... 566
21.6. HAU interrupt........................................................................................................ 567
21.6.1. Input FIFO interrupt ............................................................................................................ 567
21.6.2. Calculation completion interrupt ......................................................................................... 567
21.7. Register definition................................................................................................ 568
21.7.1. HAU control register (HAU_CTL)........................................................................................ 568
21.7.2. HAU data input register (HAU_DI)...................................................................................... 569
21.7.3. HAU configuration register (HAU_CFG) ............................................................................. 570
21.7.4. HAU data output register (HAU_DO0…7) .......................................................................... 571
21.7.5. HAU interrupt enable register (HAU_INTEN) ..................................................................... 573
21.7.6. HAU status and flag register (HAU_STAT) ......................................................................... 573
21.7.7. Context switch register x (HAU_CTXSx) (x = 0...53).......................................................... 574
22. Public Key Cryptographic Acceleration Unit (PKCAU)..................................575
22.1. Overview ............................................................................................................... 575

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22.2. Characteristics ..................................................................................................... 575
22.3. Function overview................................................................................................ 575
22.3.1. Operands ............................................................................................................................ 576
22.3.2. RSA algorithm ..................................................................................................................... 576
22.3.3. ECC algorithm..................................................................................................................... 578
22.3.4. Integer arithmetic operations .............................................................................................. 579
22.3.5. Elliptic curve operations in Fp domain ................................................................................ 589
22.3.6. PKCAU operation process.................................................................................................. 595
22.3.7. Processing times ................................................................................................................ 596
22.3.8. Status, errors and interrupts ............................................................................................... 597
22.4. Register definition................................................................................................ 599
22.4.1. Control register (PKCAU_CTL)........................................................................................... 599
22.4.2. Status register (PKCAU_STAT) .......................................................................................... 600
22.4.3. Status clear register (PKCAU_STATC)............................................................................... 601
23. Infrared ray port (IFRP) ....................................................................................603
23.1. Overview............................................................................................................... 603
23.2. Characteristics..................................................................................................... 603
23.3. Function overview................................................................................................ 603
24. Wireless.............................................................................................................605
24.1. Overview............................................................................................................... 605
24.2. Wi-Fi...................................................................................................................... 605
24.2.1. Characteristics .................................................................................................................... 605
24.3. BLE........................................................................................................................ 606
24.3.1. Characteristics .................................................................................................................... 606
24.4. Radio..................................................................................................................... 607
25. Appendix ...........................................................................................................608
25.1. List of abbreviations used in register................................................................. 608
25.2. List of terms.......................................................................................................... 608
25.3. Available peripherals........................................................................................... 609
26. Revision history................................................................................................610

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List of Figures
Figure 1-1. GD32VW55x system architecture.......................................................................... 25
Figure 2-1. Process of page erase operation........................................................................... 45
Figure 2-2. Process of mass erase operation.......................................................................... 46
Figure 2-3. Process of word program operation ..................................................................... 48
Figure 3-1. Block diagram of Efuse controller......................................................................... 63
Figure 4-1. Power supply overview........................................................................................... 76
Figure 4-2. Waveform of the POR / PDR................................................................................... 78
Figure 4-3. Waveform of the LVD threshold............................................................................. 78
Figure 4-4. RF sequence ............................................................................................................ 82
Figure 5-1. The system reset circuit ......................................................................................... 98
Figure 5-2. Clock tree ................................................................................................................. 99
Figure 5-3. HXTAL clock source.............................................................................................. 100
Figure 5-4. HXTAL clock source in bypass mode ................................................................. 101
Figure 6-1. Block diagram of EXTI .......................................................................................... 136
Figure 7-1. Basic structure of a general-pupose I/O............................................................. 144
Figure 7-2. Basic structure of Input configuration................................................................ 146
Figure 7-3. Basic structure of Output configuration............................................................. 147
Figure 7-4. Basic structure of Analog configuration ............................................................ 147
Figure 7-5. Basic structure of Alternate function configuration.......................................... 148
Figure 8-1. Block diagram of CRC calculation unit............................................................... 162
Figure 9-1. TRNG block diagram ............................................................................................. 166
Figure 10-1. Block diagram of DMA........................................................................................ 172
Figure 10-2. Data stream for three transfer modes............................................................... 173
Figure 10-3. Handshake mechanism....................................................................................... 174
Figure 10-4. Data packing/unpacking when PWIDTH = ‘00’ ................................................. 179
Figure 10-5. Data packing / unpacking when PWIDTH = ‘01’ ............................................... 180
Figure 10-6. Data packing/unpacking when PWIDTH = ‘10’ ................................................. 180
Figure 10-7. DMA operation of switch-buffer mode.............................................................. 182
Figure 10-8. System connection of DMA................................................................................ 189
Figure 12-1. ADC module block diagram................................................................................ 209
Figure 12-2. Single operation mode........................................................................................ 210
Figure 12-3. Continuous conversion mode.............................................................................211
Figure 12-4. Scan operation mode, continuous disable....................................................... 212
Figure 12-5. Scan operation mode, continuous enable........................................................ 212
Figure 12-6. Discontinuous operation mode ......................................................................... 212
Figure 12-7. 12-bit Data storage mode.................................................................................... 213
Figure 12-8. 6-bit Data storage mode...................................................................................... 213
Figure 12-9. 20-bit to 16-bit result truncation ........................................................................ 217
Figure 12-10. A numerical example with 5-bit shifting and rounding ................................. 217
Figure 13-1. Free watchdog timer block diagram.................................................................. 231

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Figure 13-2. Window watchdog timer block diagram ........................................................... 237
Figure 13-3. Window watchdog timing diagram.................................................................... 238
Figure 14-1. Block diagram of RTC......................................................................................... 242
Figure 15-1. Advanced timer block diagram.......................................................................... 277
Figure 15-2. Normal mode, internal clock divided by 1........................................................ 278
Figure 15-3. Timing chart of PSC value change from 0 to 2 ................................................ 279
Figure 15-4. Timing chart of up counting mode, PSC=0/2 ................................................... 280
Figure 15-5. Timing chart of up counting mode, change TIMERx_CAR ongoing.............. 280
Figure 15-6. Timing chart of down counting mode, PSC=0/2 .............................................. 281
Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR ongoing......... 282
Figure 15-8. Timing chart of center-aligned counting mode................................................ 283
Figure 15-9. Repetition timechart for center-aligned counter.............................................. 284
Figure 15-10. Repetition timechart for up-counter................................................................ 284
Figure 15-11. Repetition timechart for down-counter ........................................................... 285
Figure 15-12. Channel input capture principle ...................................................................... 286
Figure 15-13. Channel output compare principle (with complementary output, x=0,1,2). 287
Figure 15-14. Channel output compare principle (CH3_O) .................................................. 287
Figure 15-15. Output-compare in three modes...................................................................... 289
Figure 15-16. Timing chart of EAPWM.................................................................................... 290
Figure 15-17. Timing chart of CAPWM.................................................................................... 290
Figure 15-18. Complementary output with dead-time insertion. ......................................... 293
Figure 15-19. Output behavior of the channel in response to a break (the break high active)
............................................................................................................................................. 294
Figure 15-20. Counter behavior with CI0FE0 polarity non-inverted in mode 2.................. 295
Figure 15-21. Counter behavior with CI0FE0 polarity inverted in mode 2.......................... 295
Figure 15-22. Hall sensor is used to BLDC motor................................................................. 296
Figure 15-23. Hall sensor timing between two timers........................................................... 297
Figure 15-24. Restart mode...................................................................................................... 298
Figure 15-25. Pause mode........................................................................................................ 298
Figure 15-26. Event mode ........................................................................................................ 299
Figure 15-27. Single pulse mode, TIMERx_CHxCV = 4, TIMERx_CAR=99 ......................... 300
Figure 15-28. Trigger mode of TIMER0 controlled by enable signal of TIMER2................ 301
Figure 15-29. Trigger mode of TIMER0 controlled by update signal of TIMER2................ 301
Figure 15-30. Pause mode of TIMER0 controlled by enable signal of TIMER2.................. 302
Figure 15-31. Pause mode of TIMER0 controlled by O0CPREF signal of TIMER2............ 302
Figure 15-32. Trigger TIMER0 and TIMER2 by the CI0 signal of TIMER2 ........................... 303
Figure 15-33. General Level 0 timer block diagram .............................................................. 333
Figure 15-34. Normal mode, internal clock divided by 1...................................................... 334
Figure 15-35. Timing chart of PSC value change from 0 to 2 .............................................. 335
Figure 15-36. Timing chart of up counting mode, PSC=0/2 ................................................. 336
Figure 15-37. Timing chart of up counting mode, change TIMERx_CAR ongoing............ 336
Figure 15-38. Timing chart of down counting mode,PSC=0/2 ............................................. 337
Figure 15-39. Timing chart of down counting mode, change TIMERx_CAR ongoing....... 338
Figure 15-40. Timing chart of center-aligned counting mode.............................................. 339

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Figure 15-41. Channel input capture principle ...................................................................... 340
Figure 15-42. Channel output compare principle (x=0,1,2,3)............................................... 341
Figure 15-43. Output-compare in three modes...................................................................... 342
Figure 15-44. Timing chart of EAPWM.................................................................................... 343
Figure 15-45. Timing chart of CAPWM.................................................................................... 343
Figure 15-46. Restart mode...................................................................................................... 345
Figure 15-47. Pause mode........................................................................................................ 346
Figure 15-48. Event mode ........................................................................................................ 346
Figure 15-49. Single pulse mode, TIMERx_CHxCV = 4, TIMERx_CAR=99 ......................... 347
Figure 15-50. General level4 timer block diagram................................................................. 373
Figure 15-51. Timing chart of internal clock divided by 1.................................................... 374
Figure 15-52. Timing chart of PSC value change from 0 to 2 .............................................. 374
Figure 15-53. Up-counter timechart, PSC=0/2 ....................................................................... 375
Figure 15-54. Up-counter timechart, change TIMERx_CAR on the go................................ 376
Figure 15-55. Repetition timechart for up-counter................................................................ 377
Figure 15-56. Channel input capture principle ...................................................................... 378
Figure 15-57. Channel output compare principle (with complementary output, x=0)....... 379
Figure 15-58. Output-compare under three modes............................................................... 380
Figure 15-59. PWM mode timechart........................................................................................ 381
Figure 15-60. Complementary output with dead-time insertion. ......................................... 383
Figure 15-61. Output behavior in response to a break(The break high active) ................. 384
Figure 15-62. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x99 ................. 385
Figure 15-63. Basic timer block diagram................................................................................ 403
Figure 15-64. Timing chart of internal clock divided by 1.................................................... 404
Figure 15-65. Timing chart of PSC value change from 0 to 2 .............................................. 404
Figure 15-66. Timing chart of up counting mode, PSC=0/2 ................................................. 405
Figure 15-67. Timing chart of up counting mode, change TIMERx_CAR ongoing............ 406
Figure 16-1. USART module block diagram........................................................................... 414
Figure 16-2. USART character frame (8 bits data and 1 stop bit) ........................................ 414
Figure 16-3. USART transmit procedure ................................................................................ 417
Figure 16-4. Oversampling method of a receive frame bit (OSB=0).................................... 418
Figure 16-5. Configuration step when using DMA for USART transmission ..................... 419
Figure 16-6. Configuration step when using DMA for USART reception............................ 420
Figure 16-7. Hardware flow control between two USARTs................................................... 420
Figure 16-8. Hardware flow control......................................................................................... 421
Figure 16-9. Break frame occurs during idle state................................................................ 423
Figure 16-10. Break frame occurs during a frame................................................................. 423
Figure 16-11. Example of USART in synchronous mode ..................................................... 424
Figure 16-12. 8-bit format USART synchronous waveform (CLEN=1)................................ 424
Figure 16-13. IrDA SIR ENDEC module................................................................................... 425
Figure 16-14. IrDA data modulation ........................................................................................ 425
Figure 16-15. ISO7816-3 frame format .................................................................................... 426
Figure 16-16. USART receive FIFO structure......................................................................... 429
Figure 16-17. USART interrupt mapping diagram ................................................................. 431

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Figure 17-1. I2C module block diagram.................................................................................. 452
Figure 17-2. Data validation ..................................................................................................... 453
Figure 17-3. START and STOP condition ............................................................................... 454
Figure 17-4. I2C communication flow with 10-bit address (Master Transmit).................... 454
Figure 17-5. I2C communication flow with 7-bit address (Master Transmit)...................... 455
Figure 17-6. I2C communication flow with 7-bit address (Master Receive) ....................... 455
Figure 17-7. I2C communication flow with 10-bit address (Master Receive when HEAD10R=0)
............................................................................................................................................. 455
Figure 17-8. I2C communication flow with 10-bit address (Master Receive when HEAD10R=1)
............................................................................................................................................. 455
Figure 17-9. Data hold time...................................................................................................... 456
Figure 17-10. Data setup time.................................................................................................. 457
Figure 17-11. Data transmission.............................................................................................. 459
Figure 17-12. Data reception.................................................................................................... 459
Figure 17-13. I2C initialization in slave mode ........................................................................ 463
Figure 17-14. Programming model for slave transmitting when SS=0 ............................... 464
Figure 17-15. Programming model for slave transmitting when SS=1 ............................... 465
Figure 17-16. Programming model for slave receiving......................................................... 466
Figure 17-17. I2C initialization in master mode ..................................................................... 467
Figure 17-18. Programming model for master transmitting (N<=255) ................................ 468
Figure 17-19. Programming model for master transmitting (N>255) .................................. 469
Figure 17-20. Programming model for master receiving (N<=255) ..................................... 470
Figure 17-21. Programming model for master receiving (N>255) ....................................... 471
Figure 17-22. SMBus Master Transmitter and Slave Receiver communication flow......... 475
Figure 17-23. SMBus Master Receiver and Slave Transmitter communication flow......... 476
Figure 18-1. Block diagram of SPI........................................................................................... 492
Figure 18-2. SPI timing diagram in normal mode.................................................................. 494
Figure 18-3. A typical full-duplex connection........................................................................ 497
Figure 18-4. A typical simplex connection (Master: Receive, Slave: Transmit) ................ 497
Figure 18-5. A typical simplex connection (Master: Transmit only, Slave: Receive)........ 497
Figure 18-6. A typical bidirectional connection..................................................................... 497
Figure 18-7. Timing diagram of TI master mode with discontinuous transfer................... 499
Figure 18-8. Timing diagram of TI master mode with continuous transfer........................ 499
Figure 18-9. Timing diagram of TI slave mode ...................................................................... 500
Figure 19-1 QSPI diagram........................................................................................................ 512
Figure 19-2 QSPI command format......................................................................................... 513
Figure 20-1. DATAM No swapping and Half-word swapping............................................... 533
Figure 20-2. DATAM Byte swapping and Bit swapping........................................................ 534
Figure 20-3. CAU diagram........................................................................................................ 534
Figure 20-4. DES / TDES ECB encryption .............................................................................. 536
Figure 20-5. DES / TDES ECB decryption .............................................................................. 537
Figure 20-6. DES / TDES CBC encryption .............................................................................. 538
Figure 20-7. DES / TDES CBC decryption .............................................................................. 539
Figure 20-8. AES ECB encryption ........................................................................................... 540

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Figure 20-9. AES ECB decryption ........................................................................................... 540
Figure 20-10. AES CBC encryption......................................................................................... 541
Figure 20-11. AES CBC decryption......................................................................................... 542
Figure 20-12. Counter block structure.................................................................................... 542
Figure 20-13. AES CTR encryption / decryption.................................................................... 543
Figure 21-1. DATAM No swapping and Half-word swapping............................................... 562
Figure 21-2. DATAM Byte swapping and Bit swapping........................................................ 562
Figure 21-3. HAU block diagram ............................................................................................. 563
Figure 22-1. PKCAU module block diagram .......................................................................... 576
Figure 22-2. Flow chart of RSA algorithm .............................................................................. 577
Figure 22-3. Flow chart of ECDSA sign .................................................................................. 578
Figure 22-4. Flow chart of ECDSA verification ...................................................................... 579
Figure 22-5. Arithmetic addition.............................................................................................. 580
Figure 22-6. Arithmetic subtraction ........................................................................................ 581
Figure 22-7. Arithmetic multiplication .................................................................................... 581
Figure 22-8. Arithmetic comparison........................................................................................ 582
Figure 22-9. Modular reduction ............................................................................................... 582
Figure 22-10. Modular addition................................................................................................ 583
Figure 22-11. Modular subtraction .......................................................................................... 584
Figure 22-12. Montgomery parameter calculation ................................................................ 584
Figure 22-13. Mutual mapping between Montgomery domain and natural domain.......... 585
Figure 22-14. Montgomery multiplication .............................................................................. 586
Figure 22-15. Modular exponentiation of normal mode........................................................ 586
Figure 22-16. Modular exponentiation of fast mode ............................................................. 587
Figure 22-17. Modular inversion.............................................................................................. 587
Figure 22-18. RSA CRT exponentiation .................................................................................. 588
Figure 22-19. Point on elliptic curve Fp check ...................................................................... 590
Figure 22-20. ECC scalar multiplication of normal mode..................................................... 591
Figure 22-21. ECC scalar multiplication of fast mode .......................................................... 591
Figure 22-22. ECDSA sign........................................................................................................ 593
Figure 22-23. ECDSA verification............................................................................................ 594
Figure 23-1. IFRP output timechart 1...................................................................................... 603
Figure 23-2. IFRP output timechart 2...................................................................................... 604
Figure 23-3. IFRP output timechart 3...................................................................................... 604