Goodix Gr551 series Instruction Manual

GR551x Hardware Design Guidelines

Version: 2.5

Release Date: 2023-04-20

Shenzhen Goodix Technology Co., Ltd.

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Preface

Purpose

This document is to present the necessary circuit required for proper operation of GR551x Bluetooth System-on-Chips

(SoCs). Recommended schematic, chip interfaces, peripherals, schematic diagram, and PCB layout guidelines of the

GR551x SoC family are provided.

This Hardware Design Guidelines intends to help system designers build minimal Bluetooth Low Energy (Bluetooth LE)

hardware circuits and develop products.

Audience

This document is intended for:

• GR551x user

• GR551x tester

• Bluetooth product engineer

• Bluetooth LE system designer

Release Notes

This document is the thirteenth release of GR551x Hardware Design Guidelines, corresponding to GR551x SoC series.

Revision History

Version Date Description

1.0 2019-12-08 Initial release

1.3 2020-03-16 Updated the package pinout diagrams to the top views in “Pinout”.

1.5 2020-05-30

• Updated chip model numbers and pinout diagrams, package size diagrams, and reference

schematic diagrams;

• Changed power supplies and RF and explained by taking a QFN56 circuit as an example;

• Added “PCB Layout Reference Design”; updated “ESD Considerations”.

1.6 2020-06-30

• Updated the package layouts and data in the Appendix;

• Changed the maximum supply voltage from 4.38 V to 3.8 V; changed I/O voltage from 3.6 V

to 3.3 V (typical value).

• Added “Solutions for Improving ESD Protection Level on Products” by introducing the

hardware watchdog timer; added “Two-layer PCBs in QFN56”.

1.7 2020-08-30

Introduced the GR5515I0ND SoC:

• Added “GR5515I0ND” for pinout details;

• Added “External Flash” for recommended external Flash for GR5515I0ND;

• Added the reference schematic for GR5515I0ND in “Reference Design”;

Preface

Version Date Description

• Added “External Flash Connection for GR5515I0ND” as reference design.

1.8 2020-11-27 Polished descriptions in "GR551x Overview" and "Pinout".

1.9 2021-03-03

• Updated description on the TEST_MODE pin; introduced the number of I/O pins in “GR551x

Overview”;

• Added description on PWM configuration in "I/O Pins";

• Updated the recommended Flash models for GR5515I0ND in "External Flash";

• Updated description on I/O voltage of GR5515I0ND;

• Changed the previous “ESD Considerations” into “ESD Protection Design” and updated

contents in this section.

2.0 2021-04-29

• Updated description on I/O voltage of GR5515I0ND in “Power Supply”.

• Updated descriptions in “Power Supply Scheme”, “Power Supply”, “Clock”, “ESD Schematic

Design”, “PCB Layout Design” and “Two-layer PCBs in QFN Packages”.

2.1 2021-06-15

• Added a note for classifying GR5515RGBD as NRND.

• Updated the recommended Flash models for GR5515I0ND series in "External Flash".

2.2 2021-08-20

• Introduced GR5515IENDU and GR5515I0NDA and updated relevant chapters/sections

(“GR551x Overview”, “Features”, “Pinout”, “Reference Schematic Diagram”, and “Package

Information”).

• Changed the pins RTC_N, RTC_P, XON, and XOP to RTC_IN, RTC_OUT, XO_OUT, and XO_IN in

“Pinout” and “Reference Schematic Design”.

• Updated description about sleep mode in “Features”.

• Updated the section “External Flash”.

2.3 2022-02-20 Introduced GR5513BENDU, a wide-voltage SoC.

2.4 2023-01-19

• Deleted the GR5515I0ND SoC.

• Updated the GR5515RGBD status from "NRND" to "Active".

• Added a note for classifying GR5513BEND as "NRND".

2.5 2023-04-20

• Updated “Features” of GR551x overview and “Introduction” of power supply.

• Added “Power-on Sequence”.

Contents

Preface.................................................................................................................................................................... I

1 GR551x Overview................................................................................................................................................1

1.1 Features............................................................................................................................................................... 1

1.2 Block Diagram......................................................................................................................................................4

2 Pinout................................................................................................................................................................. 5

2.1 GR5515IGND/GR5515IENDU QFN56................................................................................................................... 5

2.2 GR5515I0NDA QFN56.......................................................................................................................................... 8

2.3 GR5515RGBD BGA68......................................................................................................................................... 12

2.4 GR5515GGBD BGA55.........................................................................................................................................16

2.5 GR5513BEND (NRND)/GR5513BENDU QFN40.................................................................................................. 20

3 Minimal Design for GR551x SoC........................................................................................................................23

3.1 Schematic Design Guideline.............................................................................................................................. 23

3.1.1 Power Supply............................................................................................................................................ 23

3.1.1.1 Introduction......................................................................................................................................23

3.1.1.2 Power-on Sequence......................................................................................................................... 24

3.1.1.3 Power Supply Scheme......................................................................................................................26

3.1.1.4 I/O LDO.............................................................................................................................................29

3.1.2 Clock..........................................................................................................................................................31

3.1.2.1 Introduction......................................................................................................................................31

3.1.2.2 32 MHz Clock (XO)........................................................................................................................... 31

3.1.2.3 32.768 kHz Clock..............................................................................................................................32

3.1.3 RF.............................................................................................................................................................. 33

3.1.3.1 Introduction......................................................................................................................................33

3.1.3.2 RF Scheme........................................................................................................................................34

3.1.4 I/O Pins..................................................................................................................................................... 34

3.1.5 SWD Interfaces..........................................................................................................................................35

3.1.6 External Flash............................................................................................................................................35

3.2 PCB Design and Layout Guideline..................................................................................................................... 36

3.2.1 PCB Layer Stackup.................................................................................................................................... 36

3.2.2 Components Layout.................................................................................................................................. 37

3.2.3 Power Supply............................................................................................................................................ 37

3.2.3.1 DC-DC Switching Regulator.............................................................................................................. 37

3.2.3.2 RF Input Power Supply.....................................................................................................................38

3.2.4 Clock..........................................................................................................................................................39

3.2.5 RFIO Port...................................................................................................................................................40

3.2.6 Grounding................................................................................................................................................. 41

3.2.7 ESD Protection Design.............................................................................................................................. 42

3.2.7.1 System-level ESD Design.................................................................................................................. 42

Contents

3.2.7.1.1 ESD Schematic Design............................................................................................................. 42

3.2.7.1.2 PCB Layout Design...................................................................................................................44

3.2.7.1.3 Product Structural Design........................................................................................................47

3.2.7.2 ESD Considerations in Production, Transport, and Debugging........................................................ 47

4 Reference Design...............................................................................................................................................48

4.1 Reference Schematic Diagram...........................................................................................................................48

4.2 PCB Layout Reference Design............................................................................................................................54

4.2.1 Four-layer PCBs in QFN56 Package...........................................................................................................54

4.2.2 Two-layer PCBs in QFN Packages..............................................................................................................57

4.2.3 External Flash Connection for GR5515I0NDA...........................................................................................58

4.2.4 Four-layer PCBs in BGA68 Package...........................................................................................................59

5 FAQ................................................................................................................................................................... 62

5.1 Why Is the Power Consumption in GR551x Sleep Modes High?...................................................................... 62

5.2 Can the RF PI Circuits Be Simplified or Removed?........................................................................................... 62

6 Glossary............................................................................................................................................................ 63

7 Appendix: QFN and BGA Assembly Guideline................................................................................................... 64

7.1 Package Information..........................................................................................................................................65

7.1.1 QFN56....................................................................................................................................................... 65

7.1.2 BGA68....................................................................................................................................................... 67

7.1.3 BGA55....................................................................................................................................................... 69

7.1.4 QFN40....................................................................................................................................................... 71

7.2 Board Mounting Guideline................................................................................................................................ 73

7.2.1 Stencil Design for Perimeter Pads............................................................................................................ 73

7.2.2 Via Types and Solder Voiding................................................................................................................... 74

7.2.2.1 Stencil Thickness and Solder Paste.................................................................................................. 74

7.2.2.2 PCB Materials................................................................................................................................... 74

7.2.3 SMT Printing Process................................................................................................................................ 75

7.3 SMT Reflow Process.......................................................................................................................................... 75

7.4 Rework Guideline.............................................................................................................................................. 77

7.4.1 Component Removal................................................................................................................................ 78

7.4.2 Site Redress...............................................................................................................................................78

7.4.3 Solder Paste Printing.................................................................................................................................78

7.4.4 Component Placement............................................................................................................................. 79

7.4.5 Component Attachment........................................................................................................................... 79

7.5 RoHS Compliant.................................................................................................................................................79

7.6 SVHC Materials (REACH)....................................................................................................................................79

7.7 Halogen Free......................................................................................................................................................79

GR551x Overview

1 GR551x Overview

The Goodix GR551x family is a single-mode, low-power Bluetooth 5.1 System-on-Chip (SoC). It can be configured as a

Broadcaster, an Observer, a Central, or a Peripheral and supports the combination of all the above roles, making it an

ideal choice for Internet of Things (IoT) and smart wearable devices.

Based on ARM® Cortex®-M4F CPU core, the GR551x series integrates Bluetooth 5.1 Protocol Stack, a 2.4 GHz RF

transceiver, on-chip programmable Flash memory, RAM, and multiple peripherals.

GR551x SoCs are available in multiple packages (see Table 1-1) that meet your diverse project demands.

Table 1-1 GR551x series

Features GR5515IGND GR5515IENDU GR5515I0NDA GR5515RGBD GR5515GGBD GR5513BEND GR5513BENDU

CPU Cortex®-M4F Cortex®-M4F Cortex®-M4F Cortex®-M4F Cortex®-M4F Cortex®-M4F Cortex®-M4F

RAM 256 KB 256 KB 256 KB 256 KB 256 KB 128 KB 128 KB

SiP Flash 1 MB 512 KB N/A 1 MB 1 MB 512 KB 512 KB

I/O

Number

39 39 39 39 29 22 22

Package

(mm)

QFN56 (7 x 7 x

0.75)

QFN56 (7 x 7 x

0.75)

QFN56 (7 x 7 x

0.75)

BGA68 (5.3 x

5.3 x 0.88)

BGA55 (3.5 x

3.5 x 0.60)

QFN40 (5 x 5 x

0.75)

QFN40 (5 x 5 x

0.75)

Note:

GR5515IENDU and GR5513BENDU are embedded with wide-voltage Flash, with Flash power supply from 1.65 V to 3.6

1.1 Features

• A Bluetooth Low Energy (Bluetooth LE) 5.1 transceiver integrates Controller and Host layers

◦ Supported data rates: 1 Mbps, 2 Mbps, and Long Range (500 kbps, 125kbps)

◦ TX power: -20 dBm to +7 dBm

◦ -96 dBm sensitivity (in 1 Mbps mode)

◦ -93 dBm sensitivity (in 2 Mbps mode)

◦ -99 dBm sensitivity (in Long Range 500 kbps mode)

◦ -102 dBm sensitivity (in Long Range 125 kbps mode)

◦ TX current: 5.6 mA @ 0 dBm, 1 Mbps

◦ RX current: 4.8 mA @ 1 Mbps

•ARM® Cortex®-M4F 32-bit micro-processor with floating point support

◦ Up to 64 MHz clock frequency

GR551x Overview

◦ Built-in Memory Protection Unit (MPU) supporting eight programmable regions

◦ Hardware Floating Point Unit (FPU)

◦ Built-in Nested Vectored Interrupt Controller (NVIC)

◦ Non-maskable Interrupt (NMI) input

◦ Serial Wire Debug (SWD) with 6 breakpoints, two watchpoints, and a debug timestamp counter

◦ 51 µA/MHz execution from Flash @ 3.3 V, 64 MHz

• On-chip memory

◦ 256 KB SRAM with retention capabilities (four 8 KB SRAM blocks and seven 32 KB SRAM blocks) for GR5515

series SoCs, and 128 KB SRAM with retention capabilities (four 8 KB SRAM blocks and three 32 KB SRAM

blocks) for the GR5513 SoC

◦ 8 KB cache SRAM with retention capabilities

◦ Stack ROM (including boot ROM and Bluetooth LE Stack)

◦ 1 MB internal QSPI Flash for GR5515 series SoCs and 512 KB internal QSPI Flash for the GR5513 SoC

(exceptions: GR5515I0NDA requiring external QSPI Flash and GR5515IENDU requiring 512 KB embedded

Flash)

• Digital peripherals

◦ One general-purpose DMA engine with 8 channels and 16 handshaking interfaces

• Analog peripherals

◦ One 13-bit Sense ADC with the sampling rate of 1 Msps. It supports up to five external I/O channels and

three internal signal channels

◦ Built-in temperature and voltage sensors

◦ Low-power comparator, supporting wakeup from deep sleep mode

• Flexible serial peripherals

◦ 2 x QSPI interfaces, up to 32 MHz

◦ 2 x UART modules up to 4 Mbps, with all modules supporting flow control and only UART0 supporting DMA

◦ 2 x I2C modules for peripheral communication, up to 2 MHz

◦ 1x SPI master interface and 1 x SPI slave interface for host communication, up to 32 MHz

◦ 2 x I2S interfaces (1 I2S master interface + 1 I2S slave interface)

◦ ISO 7816 interface

• Security

◦ Complete secure computing engine:

- AES 128-bit/192-bit/256-bit symmetric encryption (ECB, CBC)

GR551x Overview

- Hash-based Message Authentication Code (HMAC-SHA256)

- Public key cryptography (PKC)

- True random number generator (TRNG)

◦ Comprehensive security operation mechanism:

- Secure boot

- Encrypted firmware running directly from Flash

- eFuse for encrypted key storage

- Differentiate application data key and firmware key, supporting one data key per device/product

• I/O peripherals

◦ 39 I/O pins in total

- 26 general-purpose I/O (GPIO) pins

- 8 always-on I/O (AON IO) pins, supporting wakeup from deep sleep mode

- 5 mixed signal I/O (MSIO) pins, configurable to be digital/analog signal interface

• Timer

◦ Two general-purpose, 32-bit timer modules

◦ A timer module composed of two programmable 32-bit or 16-bit down counters

◦ An internal sleep timer that can be used to wake the device up from deep sleep mode

◦ Two PWM modules with edge alignment mode and center alignment mode, each with 3 channels

◦ 1 x real-time counter (RTC), can be used as Calendar

◦ 1 x AON watchdog timer, working in both system sleep and active status

• Power management

◦ On-chip DC-DC to provide RF Analog voltage and supply core LDO

◦ On-chip I/O LDO to provide I/O voltage and supply external components, maximum I/O LDO drive strength:

30 mA

◦ Programmable thresholds for brownout detection (BoD reset and BoD interrupt)

◦ Supply voltage: 2.2 V to 3.8 V. The supply voltage of GR5515I0NDA (when the external Flash of

GR5515I0NDA is supplied by high voltage) shall equal the working voltage of the external QSPI Flash

◦ I/O voltage: 1.8 V to 3.3 V (Typical) (for GR5515I0NDA/GR5515IENDU/GR5513BENDU Flash using high

voltage, the VIO_LDO_OUT shall be connected to VBATL in schematic circuit.)

• Low-power consumption modes

◦ Deep sleep mode: 2.7 µA (Typical), with full 256 KB SRAM retention

GR551x Overview

◦ Ultra deep sleep mode: 1.8 µA (Typical), no SRAM retention

◦ Off mode: 0.15 uA (Typical), nothing on except VBAT, and chip in reset mode

• Packages

◦ QFN56: 7 mm x 7 mm, 0.40 mm pitch

◦ BGA68: 5.3 mm x 5.3 mm, 0.50 mm pitch

◦ BGA55: 3.5 mm x 3.5 mm, 0.40 mm pitch

◦ QFN40: 5 mm x 5 mm, 0.40 mm pitch

• Operating temperature range: -40°C to +85°C

1.2 Block Diagram

The block diagram of GR551x is shown in the figure below.

PMU Subsystem

Bluetooth Subsystem

RF Transceiver Communicaon Core

HFXO_32M

SX PLL

Mixer

CLK

Gen.

Digital Front End Bluetooth LE

Modem

Bluetooth LE

MAC Packet Buﬀer

DC/DC

LP LDO

LFXO_32K

LFRC_32K

MCU Subsystem

Flash

Cache Ctrl

ROM

Flash & XIP Ctrl

eFuse

Cache

SRAM

ARM®Cortex®-M4F

BB ADC

Voltage

sensor

SPI Master

ISO7816MSIO

I2CUART

AON I/O

I2S

GPIO

QSPI

SPI Slave

LNA

DIGCORE LDO

CPLL_192M

PWMTimerComparator

Temperature

sensor

Crypto

DMA

Sense

ADC

BOD

POR

IO LDO

HFXO_32M

RNG_OSC

Power

Sequencer

Always-on

Domain

Memory/State Retenon

Wake up

LP Comp. AON RTC

AON SLP

Timer

AON

WDT

Dual

Timer

Figure 1-1 GR551x block diagram

Note:

For more details of each module in this block diagram, see GR551x Datasheet.

Pinout

2 Pinout

This chapter introduces GR551x pinout available in multiple packages and provides detailed descriptions.

2.1 GR5515IGND/GR5515IENDU QFN56

Figure 2-1 shows the pin assignments of GR5515IGND/GR5515IENDU QFN56 package (top view).

VDD_VCO/VDD_RF

TRX

GPIO_0

XO_OUT

GPIO_26

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_30

GPIO_31

GPIO_17

GPIO_16

GPIO_25

GPIO_24

XO_IN

VDD_AMS

GPIO_28

GPIO_27

VBATT_RF

GPIO_8

VIO_LDO_OUT

GPIO_12

VDDIO_1

VBATL

VSS_BUCK

VSW

VREG

VDD_DIGCORE_1V

CHIP_EN

RF pin Digital I/O & supplies pin Analog pin

GPIO_13

GPIO_14

AON_GPIO_5

MSIO0

AON_GPIO_4

AON_GPIO_3

AON_GPIO_2

AON_GPIO_1

AON_GPIO_0

TEST_MODE

MSIO1

MSIO2

29 RTC_OUT

GR5515IGND QFN56

GPIO_9

GPIO_10

GPIO_11

GPIO_15

RTC_IN

GPIO_29

AON_GPIO_7

AON_GPIO_6

MSIO3

MSIO4

GR5515IGND/GR5515IENDU

QFN56

Figure 2-1 GR5515IGND/GR5515IENDU QFN56 package pinout

Table 2-1 shows pin descriptions of GR5515IGND/GR5515IENDU QFN56 package.

Pinout

Table 2-1 GR5515IGND/GR5515IENDU QFN56 pin descriptions

Pin # Pin Name Pin Type Description/Default Function Voltage Domain

1 VDD_VCO/VDD_RF Analog/RF supply

Synthesizer VCO supply/RF supply: 1.1 V;

connect to VREG.

2 TRX Analog/RF RX input and TX output

3 VBATT_RF Analog/RF Supply Connect to VBATL.

4 GPIO_0 Digital I/O

General purpose I/O; default: SWD_CLK; pad

drive level is 2 mA.

VDDIO1

5 GPIO_1 Digital I/O

General purpose I/O; default: SWD_IO; pad

drive level is 2 mA.

VDDIO1

6 GPIO_2 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

7 GPIO_3 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

8 GPIO_4 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

9 GPIO_5 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

10 GPIO_6 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

11 GPIO_7 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

12 GPIO_8 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

13 GPIO_9 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

14 GPIO_10 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

15 GPIO_11 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

16 GPIO_12 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

17 VDDIO_1 Digital I/O supply

I/O supply voltage. Support external 1.8 V–3.3 V

input voltage.

VDDIO1

18 GPIO_13 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

19 GPIO_14 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

20 GPIO_15 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO1

21 CHIP_EN Mixed Signal IN

Master Enable for chip reset pin.

The high value of CHIP_EN equals VBATL.

Minimum value of high level for CHIP_EN is 1 V.

22 VIO_LDO_OUT PMU

Output of on-chip I/O supply regulator

When GR5515IENDU is used and the Flash is

supplied at a high voltage, the pin is used as the

power input pin of VDDIO0 digital I/O domain

by being connected to VBATL

Connected internally

to VDDIO0

Pinout

Pin # Pin Name Pin Type Description/Default Function Voltage Domain

23 VDD_DIGCORE_1V PMU

On-chip LDO output for digital core. Connect to

a 1 µF capacitor.

24 VREG PMU Feedback pin from switching regulator

25 VSW PMU DC-DC converter switching node

26 VSS_BUCK PMU

DC-DC converter supply and general battery

GND

27 VBATL PMU Power supply: 2.2 V to 3.8 V

28 RTC_IN Analog/PMU

Input of inverting amplifier connected to 32.768

kHz crystal

29 RTC_OUT Analog/PMU

Output of inverting amplifier connected to

32.768 kHz crystal

30 MSIO4 Mixed Signal I/O

Configurable to be a GPIO mixed signal (SNSADC

interface); pad drive level is 2 mA.

VBATL

31 MSIO3 Mixed Signal I/O

Configurable to be a GPIO mixed signal (SNSADC

interface); pad drive level is 2 mA.

VBATL

32 MSIO2 Mixed Signal I/O

Configurable to be a GPIO mixed signal (SNSADC

interface); pad drive level is 2 mA.

VBATL

33 MSIO1 Mixed Signal I/O

Configurable to be a GPIO mixed signal (SNSADC

interface); pad drive level is 2 mA.

VBATL

34 MSIO0 Mixed Signal I/O

Configurable to be a GPIO mixed signal (SNSADC

interface); pad drive level is 2 mA.

VBATL

35 TEST_MODE Digital I/O

Factory test mode selection pin

• 1: test mode

• 0: normal operation mode

VDDIO0

36 AON_GPIO_0 Digital I/O Always-on GPIO VDDIO0

37 AON_GPIO_1 Digital I/O Always-on GPIO VDDIO0

38 AON_GPIO_2 Digital I/O Always-on GPIO VDDIO0

39 AON_GPIO_3 Digital I/O Always-on GPIO VDDIO0

40 AON_GPIO_4 Digital I/O Always-on GPIO VDDIO0

41 AON_GPIO_5 Digital I/O Always-on GPIO VDDIO0

42 AON_GPIO_6 Digital I/O Always-on GPIO VDDIO0

43 AON_GPIO_7 Digital I/O Always-on GPIO VDDIO0

44 GPIO_24 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

45 GPIO_25 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

Pinout

Pin # Pin Name Pin Type Description/Default Function Voltage Domain

46 GPIO_16 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

47 GPIO_17 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

48 GPIO_31 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

49 GPIO_30 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

50 GPIO_26 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

51 GPIO_27 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

52 GPIO_28 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

53 GPIO_29 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0

54 VDD_AMS Analog/RF Supply AMS supply 1.1 V; connect to VREG.

55 XO_OUT Analog/RF

Output of inverting amplifier connected to 32

MHz crystal

56 XO_IN Analog/RF

Input of inverting amplifier connected to 32

MHz crystal

2.2 GR5515I0NDA QFN56

Figure 2-2 shows the pin assignments of GR5515I0NDA QFN56 package (top view).

The pins (Pin 43 to Pin 53) of GR5515I0NDA QFN56 package are different from those of GR5515IGND/GR5515IENDU

QFN56 package.

Pinout

VDD_VCO/VDD_RF

TRX

GPIO_0

XO_OUT

GPIO_25

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_24

GPIO_23

GPIO_22

GPIO_21

GPIO_20

GPIO_19

GR5515IGND

QFN56

XO_IN

VDD_AMS

GPIO_30

GPIO_16

VBATT_RF

GPIO_8

VIO_LDO_OUT

GPIO_12

VDDIO_1

VBATL

VSS_BUCK

VSW

VREG

VDD_DIGCORE_1V

CHIP_EN

RF pin Digital I/O & supplies pin Analog pin

GPIO_13

GPIO_14

AON_GPIO_5

MSIO0

AON_GPIO_4

AON_GPIO_3

AON_GPIO_2

AON_GPIO_1

AON_GPIO_0

TEST_MODE

MSIO1

MSIO2

29 RTC_OUT

GPIO_9

GPIO_10

GPIO_11

GPIO_15

RTC_IN

GPIO_26

GPIO_18

AON_GPIO_6

MSIO3

MSIO4

GR5515I0NDA QFN56

External Flash pin

Figure 2-2 GR5515I0NDA QFN56 package pinout

Table 2-2 shows pin descriptions of GR5515I0NDA QFN56 package.

Table 2-2 GR5515I0NDA QFN56 pin descriptions

Pin # Pin Name Pin Type Description/Default Function Voltage Domain

1 VDD_VCO/VDD_RF Analog/RF supply

Synthesizer VCO supply/RF supply: 1.1 V; connect to

VREG.

2 TRX Analog/RF RX input and TX output

3 VBATT_RF Analog/RF Supply Connect to VBATL.

Pinout

Pin # Pin Name Pin Type Description/Default Function Voltage Domain

4 GPIO_0 Digital I/O

General purpose I/O; default: SWD_CLK; pad drive

level is 2 mA.

VDDIO1

5 GPIO_1 Digital I/O

General purpose I/O; default: SWD_IO; pad drive level

is 2 mA.