QSG-15850
4 Holt Integrated Circuits
controlled using DIP switches labeled RXENA and RXENB on switch package SW1. By default, receive
signal pairs for both buses are enabled by these two SW1DIP switches set for logic-1.
The RX and nRX receive outputs have an option to stretch minimum output pulse width. When receiving
differential signals near the MIL-STD-1553 minimum amplitude specification (860 mVpp or less when
transformer-coupled), traditional transceivers produce narrow output pulses at RX and nRX because the
time that analog bus voltage exceeds the receiver threshold is much shorter than for a nominal or large
amplitude bus voltage. Short HI-15850 RX and nRX receiver pulse outputs can optionally be stretched to
have a minimum pulse width of 180ns. This function is enabled by strapping the RXWIDENA
configuration pin high. When RXWIDENA is low, the comparator output is conventional.
For Bus A, RXWIDENA on the break-out board is controlled by the DIP switch labeled RXWIDENA on
switch package SW1. For Bus B, RXWIDENB on the break-out board is controlled by the DIP switch
labeled RXWIDENB on switch package SW1. Note that receiver pulse stretching may cause issues with
noise rejection, especially when noise pulses are stretched in the intermessage gap just before or during
command sync rising edge. For this reason, use of receiver pulse width stretching should be weighed
carefully against noise immunity considerations.
The HI-15850 has weak pull-up resistors on RXWIDENA and RXWIDENAB inputs. By default, the
RXWIDENA and RXWIDENB DIP switches on package SW1 are set for logic-0 state, so neither bus has this
option enabled on the HI-15850 Signal Break-Out Board.
Bus Transmit Signal Path
A pair of CMOS logic-level inputs accepts bipolar serial signals for driving each bus from an external user-
provided Manchester encoder. Transmit for each bus can be enabled or inhibited using the
corresponding TXINH transmit inhibit signal. For Bus A, the DIP switch labeled TXINHA on package SW3
controls transmit inhibit. For Bus B, the DIP switch labeled TXINHB on package SW2 controls transmit
inhibit. By default, neither bus has transmit inhibited on the HI-15850 signal break-out board.
The transmit signal path for each bus includes the bipolar TX and nTX signals generated by the external
Manchester encoder. Signal quality concerns dictate that the TX/nTX signals for each bus have matched
characteristics. This includes matched conductor length and impedance, matched layer-to-layer vias (or
even better, no vias). It is not always possible to achieve good matching on the board layout. The result:
TX and nTX switching transitions are not quite simultaneous; the TX/nTX crossover occurs early or late.
Crossover should occur mid-way between ground and the 3.3V supply rail to assure acceptable “output
symmetry” or “tail-off” occurring at the end of long transmit messages. This effect is discussed at length
in Holt application note AN-550.
Transmit Signal Sync Option
To accurately synchronize TX and nTX inputs, the HI-15850 offers the option to simultaneously clock
transmit input signals for each bus with a clock pulse input pin. When high, the ENCLKA input enables
