HOLT ADK-15850 User manual

QSG-15850 Rev. New Holt Integrated Circuits
ADK-15850 Quick Start Guide –
HI-15850 Transceiver
Demonstration Board
June 2020

QSG-15850
2 Holt Integrated Circuits
REVISION HISTORY
Revision
Date
Description of Change
QSG-15850 Rev. New
06/12/2020
Initial Release

QSG-15850
3 Holt Integrated Circuits
Introduction
The Holt HI-15850 is a MIL-STD-1553 transceiver with a unique range of hardware configuration options.
The ADK-15850 Demo Board provides a convenient way to evaluate the various features.
HI-15850PC Signal Break-Out Board
Set Up
To demonstrate the board, an external power supply providing 3.3VDC at 800mA is needed. Connect the
power supply to test points 3V3 and GND along the top edge of the board.
Bus Receive Signal Path
A pair of CMOS logic-levels depending on the voltage selected by J7 (1.8V, 2.5V or 3.3V) provides bipolar
serial signals for connecting each bus to an external user-provided Manchester decoder. RXA and nRXA
are the non-inverted and inverted receiver outputs for Bus A; RXB and nRXB are the receiver outputs for
Bus B. The logic-level Bus A and Bus B receiver outputs can be enabled/disabled using the transceiver
RXENA and RXENB inputs. On the HI-15850 Signal Break-Out Board, the receiver enable signals are

QSG-15850
4 Holt Integrated Circuits
controlled using DIP switches labeled RXENA and RXENB on switch package SW1. By default, receive
signal pairs for both buses are enabled by these two SW1DIP switches set for logic-1.
The RX and nRX receive outputs have an option to stretch minimum output pulse width. When receiving
differential signals near the MIL-STD-1553 minimum amplitude specification (860 mVpp or less when
transformer-coupled), traditional transceivers produce narrow output pulses at RX and nRX because the
time that analog bus voltage exceeds the receiver threshold is much shorter than for a nominal or large
amplitude bus voltage. Short HI-15850 RX and nRX receiver pulse outputs can optionally be stretched to
have a minimum pulse width of 180ns. This function is enabled by strapping the RXWIDENA
configuration pin high. When RXWIDENA is low, the comparator output is conventional.
For Bus A, RXWIDENA on the break-out board is controlled by the DIP switch labeled RXWIDENA on
switch package SW1. For Bus B, RXWIDENB on the break-out board is controlled by the DIP switch
labeled RXWIDENB on switch package SW1. Note that receiver pulse stretching may cause issues with
noise rejection, especially when noise pulses are stretched in the intermessage gap just before or during
command sync rising edge. For this reason, use of receiver pulse width stretching should be weighed
carefully against noise immunity considerations.
The HI-15850 has weak pull-up resistors on RXWIDENA and RXWIDENAB inputs. By default, the
RXWIDENA and RXWIDENB DIP switches on package SW1 are set for logic-0 state, so neither bus has this
option enabled on the HI-15850 Signal Break-Out Board.
Bus Transmit Signal Path
A pair of CMOS logic-level inputs accepts bipolar serial signals for driving each bus from an external user-
provided Manchester encoder. Transmit for each bus can be enabled or inhibited using the
corresponding TXINH transmit inhibit signal. For Bus A, the DIP switch labeled TXINHA on package SW3
controls transmit inhibit. For Bus B, the DIP switch labeled TXINHB on package SW2 controls transmit
inhibit. By default, neither bus has transmit inhibited on the HI-15850 signal break-out board.
The transmit signal path for each bus includes the bipolar TX and nTX signals generated by the external
Manchester encoder. Signal quality concerns dictate that the TX/nTX signals for each bus have matched
characteristics. This includes matched conductor length and impedance, matched layer-to-layer vias (or
even better, no vias). It is not always possible to achieve good matching on the board layout. The result:
TX and nTX switching transitions are not quite simultaneous; the TX/nTX crossover occurs early or late.
Crossover should occur mid-way between ground and the 3.3V supply rail to assure acceptable “output
symmetry” or “tail-off” occurring at the end of long transmit messages. This effect is discussed at length
in Holt application note AN-550.
Transmit Signal Sync Option
To accurately synchronize TX and nTX inputs, the HI-15850 offers the option to simultaneously clock
transmit input signals for each bus with a clock pulse input pin. When high, the ENCLKA input enables

QSG-15850
5 Holt Integrated Circuits
synchronized TX and nTX inputs for bus A. The DIP switch labeled CLKENA on switch package SW3
controls CLKENA.
With synchronization enabled (CLKENA = 1), the CLKA input pin synchronizes TXA and nTXA for bus A
transmit. If using an FPGA encoder, the user must provide a brief positive clock pulse every time the TXA
and nTXA signals change state. Logic levels present at the TXA and nTXA inputs are latched by CLKA
rising edge. If CLKENA is held low, the clocked input latches are bypassed and the CLKA input has no
effect.
Similarly, the DIP switch labeled CLKENB on switch package SW2 controls CLKENB to enable or disable
synchronized operation for bus B, accomplished using the TXB, nTXB and CLKB inputs. The CLKENA and
CLKENBA input pins have weak pull-down resistors.
Bus Tail-Off Trim
On DIP switch package SW3, switches labeled TOC0A, TOC1A and TOC2A are used in combination to
provide up to +150mV or -150mV DC tail-off adjustment on Bus A, to compensate for a board layout
deficiency that causes chronic, consistent tail-off which would benefit from an across-the-board fixed
amplitude adjustment. The TOC switch settings select one of six correction levels. There are two “no
correction” TOC combinations. Table 2 on page 7 in the HI-15850 data sheet summarizes the TOC switch
combinations. Figures 4 and 5 in the data sheet show examples of various applied correction levels.
Tail-off trim for Bus B works similarly using switches labeled TOC0B, TOC1B and TOC2B on DIP switch
package SW2. All TOC input pins have weak pull-down resistors that present logic-0 when the
corresponding DIP switches are open.
Flexible Bus Interface Configuration
The HI-15850 Signal Break-Out Board has several options for configuring both MIL-STD-1553 bus
interfaces. The options are listed here and then fully described below:
Direct-coupled or transformer-coupled bus interface
On-board resistive dummy bus load or off-board conventional bus connection
Optional ground connections for negative side of Buses A and B so that single conventional
oscilloscope probes conveniently provide differential “Bus-Positive minus Bus-Negative” signal
viewing.
Direct- or Transformer-Coupled Operation
The HI-15850 Signal Break-Out Board provides 12 solder jumpers for selecting direct- or transformer-
coupled operation.
Direct-coupled 1553 bus interface is also known as a “short stub” connection because the terminal’s
stub cable cannot exceed 12 inches (31 mm) in length. Direct-coupled bus interface requires a pair of

QSG-15850
6 Holt Integrated Circuits
current-limiting resistors in series with the bus connection. When configuration jumpers are set for
direct-coupled operation, current-limiting resistors are provided on the break-out board.
Transformer-coupled 1553 bus interface is the predominant configuration used for terminal connection.
This diagram shows a network comprised of three transformer-coupled terminals: a Bus Controller (BC)
and two Remote Terminals (RTs). Stub cables must be < 20 feet (6.1 meters).
The HI-15850 Signal Break-Out Board (and user-provided protocol logic) takes the place of the BC or one
of the RTs in the above diagram.
As seen above, each terminal’s stub cable connects to the 1553 bus through a “bus coupler,” which is
typically an off-the-shelf hardware component comprised of coupling transformer(s) for one or more
terminal stubs (each with its own pair of internal current-limiting resistors). Two bus couplers are shown
above. The bus couplers have a bus connection jack at each end for serial connection into the 1553 bus
structure. Each end of the bus has a 78Ω terminator. Holt application note AN-550 provides additional
information about the direct- and transformer-coupled configurations.
Dummy Resistor Bus Load Option
The HI-15850 Signal Break-Out Board provides 12 solder jumper or shunt locations for selection of
direct- or transformer-coupled operation. The jumpers also select on-board resistor dummy bus load or
off-board conventional 1553 bus connection, shown above. When enabled, the on-board dummy load
replaces the stub cable assembly in the diagram and everything above it; the resistor load appears

QSG-15850
7 Holt Integrated Circuits
directly at the terminal bus interface. The load is 70Ω for transformer-coupled operation, or 35Ω for
direct-coupled operation (using two parallel 70Ω resistors).
The twelve configuration jumpers are designated JP1 –JP10, J2 and J4. A connection table printed on
the HI-15850 schematic shows how to set the jumpers to closed position, all others open by default for
the four combinations of direct- vs. transformer-coupled operation and on-board dummy bus load vs.
external conventional 1553 bus connection.
Single Scope Probe “Faux Differential” Viewing Option
When characterizing a 1553 terminal, most bus measurements are the differential line-to-line stub
voltage measured across the bus side of the terminal’s isolation transformer. For the HI-15850 signal
break-out board, the transformer is the PM-DB2779 rectangular black cube, and the red and black
differential test point pairs are labeled BUSA/nBUSA and BUSB/nBUSB for the two buses.
Differential line-to-line voltage measurement for Bus A can be accomplished by connecting oscilloscope
probes for channel 1 and channel 2 to the BUSA and nBUSA test points respectively, and using scope
built-in math function to observe “channel 1 minus channel 2”. R14 must be “open circuit” for this
configuration.
If R14 is shorted, the minus side of buses A and B are grounded. The user can forgo the channel 2
oscilloscope connection to nBUSA; the single channel 1 probe connection to BUSA provides true
differential viewing of Bus A stub voltage. This is strictly a convenience measure to be used when
evaluating HI-15850 transceiver performance; the minus side of the 1553 bus stub would never be left
grounded under normal circumstances for production hardware.
The above comments for configuring Bus A also apply for Bus B, substituting test points BUSB and
nBUSB for test points BUSA and nBUSA respectively.
Board Schematic Diagram
The schematic diagram for the HI-15850 Signal Break-Out Board is on the following page.

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLOSE
BLK
RED
BLK
RED
FOR ALL DIP SWITCHES
UP = LOGIC-1
XFMR
XFMR
DIRECT
DIRECT
BusA
COUPLING
70 External
70 On PCB
35 External
35 On PCB
BUS LOAD
JP2,JP4
JP2, JP4, JP3 or J2
JP2 -JP4
JP1, JP5, JP3, J2
Timing Control B
Timing Control A
3V3
GND
1 : 2.65
1 : 2.07
1
3
2
1
3
2
GND
Tab is GND
DPAK
1.8V
Digital I/O Voltage Select
Tab is GND
DPAK
2.5V
3.3V
2.5V
1.8V
FPGA 10 ohm
protection resistors
CAUTION: ENSURE VDDIO VOLTAGE
SELECTION MATCHES FPGA VOLTAGE
CLOSE
70 External
70 On PCB
35 External
35 On PCB
BusB
COUPLING
XFMR
XFMR
DIRECT
DIRECT
JP7,JP9
JP7, JP9, JP8 or J4
JP6 -JP10
JP6, JP10, JP8, J4
BUS LOAD
nABUS
RXENA
RXWENA
RXENB
RXWENB
ABUS
3V3
nBBUS
BBUS
nTXB
CLKB
RXA
nRXA
RXB
nRXB
TXA
nTXA
CLKA
TXB
VDDIO
VDDIO
3V3
1V8
2V5
VDDIO
GND GND
TXA
nTXA
3V3 3V3
TXB
nTXB
3V3
3V3
3V3
3V3
Title
Size Document Number Rev
Date: Sheet of
HI1585PC Break Out Board NEW
HI-15850PC Signal Break-Out Board
Custom
11Thursday, June 04, 2020
Title
Size Document Number Rev
Date: Sheet of
HI1585PC Break Out Board NEW
HI-15850PC Signal Break-Out Board
Custom
11Thursday, June 04, 2020
Title
Size Document Number Rev
Date: Sheet of
HI1585PC Break Out Board NEW
HI-15850PC Signal Break-Out Board
Custom
11Thursday, June 04, 2020
TP12
R8
70 1W
D1
Green LED
TP3
JP1
R7
70 1W
J6
CON2
1
2
J2
12
TP5
U3
LF25CDT
IN
1OUT 3
TAB
4
R13
330
C7
.1uF
J5
BJ77
J3
VERT RIGHT-ANGE MALE 2x6
1 2
3 4
5 6
7 8
9 10
11 12
3214
ON (CLOSED)
SW1
4-Pos DIP Switch
R1
55 1/2W
TP11
TP14
TP7
J4
12
R14
Shunt
JP9
T1B
PM-DB2779
6
7
89 10
11
12
U1
HI-15850 6x6mm 48-QFN
33 TXA
34 TXA
30 RXA
29 RXA
31 RXENA
27 RXWIDENA
32 TXINHA
37 TOC2A
20 TOC1A
19 TOC0A
22 CLKENA
21 CLKA
16 CLKB
3TXB
4TXB
7RXB
8RXB
6RXENB
10 RXWIDENB
5TXINHB
48 TOC2B
17 TOC1B
18 TOC0B
38
BUSOUTA 39
BUSOUTA 25
BUSINA
41
BUSOUTA 42
BUSOUTA 24
BUSINA
VDDIO 23
26
VDDA 35
VDDA 40
VDDA
28
GND 36
GND
43
BUSOUTB 44
BUSOUTB 13
BUSINB
46
BUSOUTB 47
BUSOUTB 12
BUSINB
2
VDDB 11
VDDB
VDDIO 14
45
VDDB
1
GND 9
GND
15 CLKENB
J7
CON 2X3
4
5 6
1 2
3
C9
.1uF
C2
.1uF
C8
10uF 10V ceramic
TP1
TP6
TP8
R10 10 ohm TP9
R9 10 ohm
JP3
R11 10 ohm
R12 10 ohm
TP10
TP4
TP15
JP10
+
C4
47uF
R3
70 1W
C5
.1uF
JP6
JP2
TP2
R6
55 1/2W
C3
.1uF
R2
70 1W
R5
55 1/2W
+
C1
47uF
JP5
C12
10uF 10V ceramic
JP8
+
C6
47uF
T1A
PM-DB2779
1
2
313 14
15
16
R4
55 1/2W
32145
ON (CLOSED)
SW3
32145
ON (CLOSED)
SW2
JP4
TP13
J1BJ77
JP7
C11
.1uF
U2
LF18CDT
IN
1OUT 3
TAB
4
C10
10uF 10V ceramic

Holt Integrated Circuits, Inc.
PCB P/N: HV052
Bill of Materials
HI-15850 Signal Breakout Board
Item Qty Description Reference Digikey P/N Mfg P/N
1 1 PCB, Bare, Evaluation Board N/A N/A NewTek 14012
2 3 Capacitor, 47uF 20% 16V Tant SMD 6032 C1,C4,C6 399-9739-1-ND Kemet T491C476M016AT
3 6 Capacitor, Cer 0.1uF 20% 50V Y5V 0805
C2,C3,C5,C7,C9,C11 399-9157-1-ND Kemet C0805C104M5VACTU
4 3 Capacitor, Cer 10uF 10% 10V X7R 0805
C8,C10,C12 399-15687-1-ND Kemet C0805C106K8RACAUTO
5 2
Connector 3-Lug Triax Jack, TRB BJ77 J1,J5 1097-1030-ND Cinch BJ77
6 3 Header, Male 1x2, .1" Pitch J2,J4,J6 S1011E-02-ND Sullins PBC02SAAN
7 1 Header, Male 2x3, .1" Pitch J7 S2011E-03-ND Sullins PBC03DAAN
8 1 Header, Male 2X6, .1" Pitch R/A J3 3M156383-12-ND 3M 929745-02-06-EU
9 4 Shunt, 2 pin, 0.1" for J2,J4,J6,J7 S9000-ND Sullins STC02SYAN
10 10 Conn solder jumper JP1-JP10 - Open N/A
11 1 Led Green SMD 0805 D1 160-1179-1-ND LiteOn LTST-C170GKT
12 4 Res 54.9 Ohm 1/2W 1% 1210 SMD R1,R4,R5,R6 P54.9AACT-ND Panasonic ERJ-14NF54R9U
13 4 Res 69.8 Ohm 1W 1% 2512 SMD R2,R3,R7,R8
Mouser 667-ERJ-
1TNF69R8U
Panasonic ERJ-1TNF69R8U
14 4 Res 10, 1/8W 5% 0805 SMD R9,R10,R11,R12 P10ACT-ND Panasonic ERJ-6GEYJ100V
15 1 Res 330, 1/8W 5% 0805 SMD R13 P330ACT-ND Panasonic ERJ-6GEYJ330V
16 1 Solder Jumper R14 - Link GND_CHSGND - Open Soldered Link GND_CHSGND
17 1 Switch Slide Dip 4-SPST 100MA 20V
SW1 CT2194MST-ND CTS 219-4MST
18 2 Switch Slide Dip 5-SPST 100MA 20V
SW2,SW3 CT2195MST-ND CTS 219-5MST
19 4 Test Point, 0.040" TP5,TP6,TP9,TP10 - DNI 36-5002-ND Keystone 5002
20 1 Test Point, Orange Insulator, 0.062" TP11 36-5013-ND Keystone 5013
21 3 Test Point, Red Insulator, 0.062" TP1,TP4,TP8 36-5010-ND Keystone 5010
22 5 Test Point, Black Insulator, 0.062" TP2,TP3,TP7,TP14,TP15 36-5011-ND Keystone 5011
23 2 Test Point, White Insulator, 0.062" TP12,TP13 36-5012-ND Keystone 5012
24 1 HI-15850PC 48-QFN 6X6mm U1 N/A Holt HI-15850PC
25 1 Isolation Transformer PM-DB2779 T1 N/A Holt-Premiers Magnetics DB2779
26 1 IC Reg Linear 2.5V 500mA DPAK U3 497-6449-1-ND STM LF25CDT-TR
27 1 IC Reg Linear 1.8V 500mA DPAK U2 497-5222-1-ND STM LF18CDT-TR
28 4 Hookup Solid wire - 20AWG - Black - 1" Long Triax wiring C2028B-XX-ND General Cable C2028A.12.01
29 4 Stand-off, Threaded #4-40F, 3/4" Long Round n/a 36-3481-ND Keystone 3481
30 4 Machine Screw, #4-40 x 5/16" n/a H343-ND B&F Supply PMS 440 0025 PH
31 4 Lock Washer, Int.Tooth #4-40 n/a H236-ND B&F Supply INTLWZ 004
32
33
34
** Remark: Mounting J1 and J5 with its GND
tab is on Top.