HP Net Vectra Product manual

Technical Reference Manual
Hardware and BIOS
HP Net Vectra PC
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Notice
The information contained in this document is subject to change without notice.
Hewlett-Packard makes no warranty of any kind with regard to this
material, including, but not limited to, the implied warranties of
merchantability and fitness for a particular purpose.
Hewlett-Packard shall not be liable for errors contained herein or for incidental
or consequential damages in connection with the furnishing, performance, or use
of this material.
Hewlett-Packard assumes no responsibility for the use or reliability of its
software on equipment that is not furnished by Hewlett-Packard.
This document contains proprietary information that is protected by copyright.
All rights are reserved. No part of this document may be photocopied,
reproduced, or translated to another language without the prior written consent
of Hewlett-Packard Company.
AdobeTM is a trademark of Adobe Systems Incorporated which may be registered
in certain jurisdictions.
Microsoft®, Windows® and MS-DOS® are U.S. registered trademarks of
Microsoft Corporation.
Pentium® is a U.S. registered trademark of Intel Corporation.
Hewlett-Packard France
Commercial Desktop Computing Division
38053 Grenoble Cedex 9
France
1997 Hewlett-Packard Company
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iii
Preface
This manual is a technical reference and BIOS document for engineers and
technicians providing system level support. It is assumed that the reader
possesses a detailed understanding of AT-compatible microprocessor
functions and digital addressing techniques.
Technical information that is readily available from other sources, such as
manufacturer’s proprietary publications, has not been reproduced.
This manual contains summary information only. For additional reference
material, refer to the bibliography, on the next page.
Conventions
The following conventions are used throughout this manual to identify
specific numeric elements:
❒Hexadecimal numbers are identified by a lower case h.
For example, 0FFFFFFFh or 32F5h
❒Binary numbers and bit patterns are identified by a lower case b.
For example, 1101b or 10011011b
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iv
Bibliography
❒HP Net Vectra User’s Guide (D5470-90001).
❒HP Net Vectra Upgrading and Maintaining the PC (available on
WWW).
❒HP Net Vectra Recovery Guide (available on WWW).
❒HP Net Vectra Familiarization Guide (D5470-90901).
❒HP Net Vectra Online User’s Guide (online).
❒Exploring your HP Net Vectra PC (online).
❒HP Network Administrator’s Guide (online).
❒HP Vectra Accessories Service Handbook - 7th edition
(5965-4074).
❒HP Vectra PC Service Handbook (Volume 1) - 12th edition
(to be announced).
❒HP Support Assistant CD-ROM (by subscription).
The following Intel®publication provides more detailed information:
❒Pentium Microprocessor Data Sheet (241595-002)
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Contents
v
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
1 System Overview
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Where to Find the Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 System Board
System Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Architectural View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chip-Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bridge Chip (SiS5581) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Super I/O Chip (NS87317) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Devices on the Processor-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 24
The Intel Pentium Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cache Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Main Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Devices on the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Integrated Drive Electronics (IDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Universal Serial Bus (USB) Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Devices on the ISA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Super I/O Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Contents
vi
X-Ben . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3 Interface Devices and Mass-Storage Drives
S3 Trio 64V2 Graphics Controller Chip. . . . . . . . . . . . . . . . . . . . . . . . 34
Video Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Available Video Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Mass-Storage Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Connectors and Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 Summary of the HP/Phoenix BIOS
HP/Phoenix BIOS Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Setup Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Configuration Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Security Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power Saving and Ergonometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Desktop Management Interface (DMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
HP Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power-On from Space-Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Soft Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HP Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Remote Power-On (RPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Advanced Power Management (APM) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
BIOS Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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Contents
vii
Product Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HP I/O Port Map (I/O Addresses Used by the System). . . . . . . . . . . . . . 56
5 Power-On Self-Test and Error Messages
Order in Which the Tests are Performed . . . . . . . . . . . . . . . . . . . . . . 62
Error Message Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Beep Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Lights on the Status Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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Contents
viii
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9
1
System Overview
This manual describes the HP Net Vectra PC, and provides detailed system
specifications.
This chapter introduces the external features, and summarizes the
documentation which is available.
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10
1 System Overview
Package
Package
(All icons shown here are for information, and do not necessarily appear on
the PC).
Activity light
Status light
Front view
Activity light
On/off button
Pause button
Cover lock
System board switches
Processor
Heat-pipe and Heat-sink
Main memory
Hard disk drive
Front view with cover
removed
USB
Serial
Parallel Mouse
Keyboard
Display
Rear view
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11
1 System Overview
Documentation
Documentation
The table below summarizes the availability of documentation that is
appropriate to the HP Net Vectra PC. Most are available as viewable files
(which can also be printed) from the HP division support servers, and on
the HP Support Assistant CD-ROM.
Each PDF file (portable document format) can be viewed on the screen by
opening it with Acrobat Reader. To print the document, press Ctrl+P whilst
you have the document on the screen. You can use the page-up, page-down,
goto page, search string functions to read the document on the screen.
(Note, though, that for some documents there is difference between the
page number that is printed on the page, and the page number that Acrobat
Reader indicates, because of the presence of the front matter pages).
Preloaded on Hard
Disk
Division Support
Server
Support Assistant CD-
ROM Paper-based
HP Net Vectra User’s Guide no PDF file PDF file D5470-90901
HP Net Vectra: Upgrading and
Maintaining the PC
no PDF file PDF file no
HP Net Vectra Recovery Guide no PDF file PDF file no
HP Net Vectra
Familiarization Guide
no PDF file PDF file D5470-90901
HP Net Vectra
Technical Reference Manual
no PDF file PDF file no
HP Vectra PC Service
Handbook (Vol 1, 12th Edition)
no PDF file PDF file To be announced
HP Vectra Accessory Service
Handbook (7th Edition)
no PDF file PDF file 5965-4074
HP Net Vectra
Online User’s Guide
HTML file PDF file PDF file no
Exploring your HP Net Vectra PC no PDF file PDF file no
Network Administrators Guide no PDF file PDF file no
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12
1 System Overview
Documentation
Where to Find the Information
The following table summarizes the availability of information within the
HP Net Vectra PC documentation set. The user is supplied with the online
documentation preloaded on the PC, and the User’s Guide (in paper form).
The remaining documents are available as an MIS kit, and can be
downloaded from the HP WWW site.
User Documentation Online Documentation Support Documentation
User’s
Guide
Upgrade
Guide
Recovery
Guide
User
Online
Exploring
Your PC
Network
Admin.
Guide
Familiar-
ization
Guide
Service
Hand-
book
Tech
Ref
Manual
Introducing the computer
Product features
Key features
Exploring
New features
Exploded view
Parts list
xx
xx
x
x
x
x
Product model numbers
Product range
CPL dates
x
x
Using the computer
Setting Up the PC
Connecting cables
Turning on
x
x
Finding information
READ.MEs
On-line documentation
Environmental
System overview
Working in comfort x x
x
Formal documents
Sw license agreement
Warranty information
x
x
xx
Upgrading the computer
Opening the computer x
Supported accessories
Full PN details
Selected PN details
x
Replacing accessories
Complete procedures
Selected procedures x x
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13
1 System Overview
Documentation
Configuring devices
Peripherals
Network
Problem fixes
xx
x
x
The Setup program
Key fields x
Repairing the computer
Troubleshooting
Basic
Advanced
New symptoms
Service notes
xx
x
x
x
Technical information
Basic
Detailed
Advanced
x
xx
x
System board
Jumpers & Switches
Connectors
Replacement
Chip-set
x
x
x
x
x
x
x
x
x
x
BIOS
Basic details
Technical details
Memory maps
Upgrading
x
x
x
x
x
Power-On Self-Test
Key error conditions
Order of tests
xx
x
User Documentation Online Documentation Support Documentation
User’s
Guide
Upgrade
Guide
Recovery
Guide
User
Online
Exploring
Your PC
Network
Admin.
Guide
Familiar-
ization
Guide
Service
Hand-
book
Tech
Ref
Manual
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14
1 System Overview
Documentation
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15
2
System Board
The next chapter describes the graphics, disk and network devices which
are supplied with the computer.
This chapter describes the components of the system board, taking in turn
the components of the Processor-Local Bus, the Peripheral Component
Interconnect (PCI) bus and the Industry Standard Architecture (ISA) bus.
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16
2 System Board
System Board
System Board
CBA
DIMM Memory Slots
Flexible Disk Connector
Primary IDE Connector
Secondary IDE Connector
Power Connector
Status Panel Voltage Regulator
System Board Switches
Video Memory
Parallel Port Serial Port Display Kbd Mou
VESA Connector
Graphics
Controller
Chip
Ext. Start
External Speaker Connector
Internal Speaker
PCI wake-up
3.3 V Conn
2✕
USB
1 2 3 4 5 6 7 8 9 10
Connector
Pentium Processor
Heat Pipe
Socket 7
SiS 5581
NS87317
PL/PCI bridge,
PCI/ISA bridge,
DRAM controller,
IDE+USB cntlr
Super I/O
controller
CR2032
System ROM
Ext. Batt.
210 mm
280 mm
L2 cache L2 cache
connector
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17
2 System Board
Architectural View
Architectural View
Level-2
cache
Main
memory
Hard
disk
Pentium
processor
Processor-Local Bus
(64 bit, 66 MHz)
PCI Bus
(32 bit, 33 MHz)
ISA Bus
(16 bit, 8.25 MHz)
Interrupt
controller
Graphics
controller
System
ROM
Serial
EEPROM
X Ben
(HP ASIC)
DMA
controller
ISA bus
interface
2✕USB
controller
NS87317
Super I/O
FDD
controller
Keyboard
controller
Parallel
controller
Mouse
controller
ISA bus
interface
2✕serial
controller
SiS5581
PL/PCI bridge
PCI/ISA bridge
Memory
controller
Data path
PCI bus
interface
Cache
controller
2✕IDE
controller
PL bus
interface
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18
2 System Board
Chip-Set
Chip-Set
The chip-set comprises two chips. These interface between the three main
buses (the Processor-Local bus, the PCI bus and the ISA bus).
• The Bridge chip (SiS5581) is a combined PL/PCI bridge and cache
controller and main memory controller and PCI/ISA bridge and IDE
controller and USB controller.
• The Super I/O chip (NS87317) is a combined serial interface and paral-
lel interface and keyboard controller and mouse controller and flexible
disk drive controller.
Bridge Chip (SiS5581)
The bridges between the Processor Local Bus (PL Bus) and the PCI Bus,
and between the PCI Bus and the ISA Bus, are encapsulated in a 553-pin ball
grid array (BGA) package.
PL Bus Interface The chip monitors each cycle that is initiated by the processor, and forwards
those to the PCI bus that are not targeted at the local memory. It translates
PL bus cycles into PCI bus cycles.
The chip supports the SMM mode of the Pentium processor, the CPU stop
clock hardware function, and the keyboard lock function. These are used by
the X-Ben chip, as described on page 51.
PCI Bus Interface The chip is PCI 2.1 compliant, and provides for PCI Concurrency.
Concurrent data transfers that do not contest for the same resources (such
as processor to memory concurrent with PCI peer to peer, or processor to
ISA device concurrent with PCI device to memory) are allowed to interleave
their transfers.
The PCI arbiter supports PCI bus arbitration for up to four masters using a
rotating priority mechanism. Its hidden arbitration scheme minimizes
arbitration overhead.
ISA Bus Interface As well as accepting cycles from the PCI bus interface, and translating them
for the ISA bus, the ISA bus interface also requests the PCI master bridge to
generate PCI cycles on behalf of a DMA or ISA master. The ISA bus interface
contains a standard ISA bus controller and data buffering logic, and can
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19
2 System Board
Chip-Set
support up to four ISA slots without any external buffering.
Data Path Storage elements are provided for bidirectional data buffering among the
64-bit PL data bus, the 64-bit memory data bus, and the 32-bit PCI address/
data bus. This buffering is used, partly, to smooth the differences in
bandwidths between the three buses, thereby improving the overall system
performance.
Level-2 Cache Memory
Controller
The Level-2 cache memory controller supports either write through or
write back direct mapped pipelined burst static RAM. On the HP Net Vectra
PC, 256KB of write back cache memory is implemented as two 32K ✕32-bit
chips soldered on the system board. An 8-bit tag is implemented in a
separate 32K ✕8-bit, 15 ns static RAM, and allows the lowermost 64 MB of
main memory to be cached (if more than 64 MB of main memory is installed,
accesses to the uppermost regions will be made directly to the main memory
modules, and not via the cache memory mechanism).
The cache memory line width is 32-bytes (256-bits), four times the width of
the Processor-Local data bus. Reads and writes always involve a full cache
line, and so require four back-to-back cycles on the bus. Since they involve
accesses to related addresses, they do not need four independent accesses
to main memory, but can be organized as a pipelined burst. The second,
third and fourth cycles in each burst require less time to complete than the
first, the first cycle having included the addressing phase and memory pre-
charge timing. The read and write access timing has the pattern 3-1-1-1.
However, the timing for 64-byte burst reads can be even better than this (3-
1-1-1,1-1-1-1 for a back-to-back burst read) provided that the main memory
banks have been filled contiguously.
There are two programmable non-cacheable regions, with an option to
disable local memory in these regions. A 64 KB to 1 MB cache summary is
provided.
Main Memory Controller The main memory controller supports up to 384 MB of EDO, FPM or
SDRAM double interline memory modules (DIMMs). The HP Net Vectra PC
supports three modules of SDRAM (synchronous dynamic random access
memory). With the 64 MB module from HP, this gives a maximum total
capacity of 192 MB.
In the case of 66 MHz PL bus operation, memory accesses have a timing
pattern of 5-2-2-2 for a page-hit. This degrades to 8-2-2-2 for a row-miss,
and to 11-2-2-2 for a page-miss. When the banks have been filled in an
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20
2 System Board
Chip-Set
arbitrary order, back-to-back burst reads keep to the 5-2-2-2,5-2-2-2 timing
pattern. When the banks have been filled contiguously (bank A, then bank
B, then bank C), back-to-back burst reads are improved to a 5-2-2-2,3-2-2-2
timing pattern.
IDE Controller The PCI master/slave IDE controller, supporting four devices, two on each of
two channels, is described on page 26. As well as the traditional five PIO
modes (0 to 4) and three DMA modes (0 to 2), this controller also supports
three Ultra ATA/33, or Ultra DMA, modes (0 to 2), allowing peak transfer
rates up to 33 MB per second.
USB Controller The PCI USB controller, supporting two connectors, is described on page 28.
DMA Controller The seven channel DMA controller incorporates the functionality of two
82C37 DMA controllers. Channels 0 to 3 are for 8-bit DMA devices, while
channels 5 to 7 are for 16-bit devices (as described on page 57). The
channels can be programmed for any of the four transfer modes: the three
active modes (single, demand, block), can perform three different types of
transfer: read, write and verify. The address generation circuitry can only
support a 24-bit address for DMA devices.
Interrupt Controller The sixteen channel interrupt controller incorporates the functionality of
two 82C59 interrupt controllers. The two controllers are cascaded, giving 14
external and two internal interrupt sources (as described on page 58).
Counter / Timer The chip contains a three-channel 82C54 counter/timer. The counters use a
division of the 14.318 MHz OSC input as the clock source.
Super I/O Chip (NS87317)
The Super I/O chip is contained within a 160-pin PQFP package. It includes
the following features:
• ACPI register set
• Five Power-On/SCI/SMI channels
• Two SMI channels
• Signal line to an external light
• Power-State bit for PIIX4-based designs.
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