HP 1660E Series User manual

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Service Guide
(
HP 1660EIESIEP-Series
Logic Analyzers

Service Guide
Publication munber 01660-97030
First edition, November 1998
For Safety information, Warranties, and Regulatory
information, see the pages at the end of the book.
©Copyright Hewlett-Packard Company 1987-1998
All Rights Reserved.
HP 1660E/ESIEP-Series
Logic Analyzers

" l ...
HP 1660E-Series, HP 1660ES-Series, and
HP 1660EP-Series Logic Analyzers
The HP 1660E-series are 100-MHz State/500 MHz Timing logic analyzers.
The
HP 1660ES-series includes all the features of the HP 1660E-series, as well as a
2-channel, 2GSa/s oscilloscope.
The
HP 1660EP-series includes all the features of the HP 1660E-series, as well as a
32-channel
pattern generator.
Features
Some of the main features of the HP 1660E-series logic analyzers are as follows:
•130
data channels and 6 clock/data channels in the HP 1660E
•96
data channels and 6 clock/data channels in the HP 1661E
•64
data channels and 4 clock/data channels in the HP 1662E
•32
data channels and 2 clock/data channels in the HP 1663E
•3.5-inchflexible
disk drive
•2.3 GB hard disk drive
•HP-IE, R8-232-C,
and Centronics printer interfaces
•Variable setuplhold time
• 4k memory on all channels with 8k in half channel mode
• Marker measurements
•12 levels of trigger sequencing for state and 10 levels of sequential triggering for
timing
•100 MHz
time and number-of-states tagging
• . Full programmability
• DINrhouse
•DIN keyboard support
The HP 1660EP-series logic analyzers also include the following features:
•15
output channels at 200 MHz
•32 output channels at 100 MHz
•
Memory depth of 258,048 vectors
• Support for TTL, 3-stateTTU3.3v, 3-state TTUCMOS, ECLterminated, ECL
unterrninated,
and differential ECL (without pod).
ii

The HP 1660ES-series logic analyzers also include the following features:
• 2 GSa/s digitizing
for 500 MHz bandwidth single shot oscilloscope
•32768
samples per channel
• Automatic pulse parameters
displays time between markers, acquires until specified time between markers is
captured, performs statistical analysis on time between markers
•Lightweight miniprobes
Service Strategy
The service strategy for this instrument is the replacement of defective assemblies.
This service guide contains information for finding adefective assembly by testing
and servicing the HP 1660EIESIEP-series logic analyzers.
This logic analyzer
can be returned to Hewlett-Packardfor all service work, including
troubleshooting.
Contact your nearest Hewlett-Packard Sales Office for more details.
01660E24
The HP 1660-series logic analyzer
"
. :.i\ ;
iii

In This Book
This book is the service guide for the HP 1660EIESIEP-series logic analyzers and is divided
into eight chapters.
Chapter 1contains information about
the logic analyzer and includes accessories,
specifications
and characteristics, and equipment required for servicing.
Chapter 2tells how to prepare
the logic analyzer for use.
Chapter 3gives instructions on how to
test the performance of the logic analyzer.
Chapter 4contains calibration instructions for the logic analyzer.
Chapter 5contains self-tests and flowcharts for troubleshooting the logic analyzer.
Chapter 6tells how to replace assemblies of
the logic analyzer and how to return them to
Hewlett-Packard.
Chapter 7lists replaceable parts, shows an explodedview,
and gives ordering information.
Chapter 8explains how
the logic analyzer works and what the self-tests are checking.
iv

Table of Contents
1General Information
Accessories 1-2
Specifications (logic analyzer) 1-3
Specifications (oscilloscope) 1-4
Specifications (pattern generator) 1-4
Characteristics (logic analyzer) 1-5
Characteristics (oscilloscope) 1-5
Characteristics (pattern generator) 1-6
Recommended test equipment (logic analyzer) 1-9
Recommended
test equipment (oscilloscope) 1-10
Recommended
test equipment (pattern generator) 1-11
2Preparing for Use
To inspect the logic analyzer 2-2
To apply power 2-3
To operate the user interface 2-3
To set the line voltage 2-3
To clean the logic analyzer 2-4
To test the logic analyzer 2-4
3 Testing Performance
To perform the self-tests 3-2
To make the test connectors (logic analyzer) 3-7
To test the threshold accuracy (logic analyzer) 3-9
Set up the equipment 3-9
Set up the logic analyzer 3-10
Connect the logic analyzer 3-10
Test the TTL threshold
3-11
Test the ECL threshold 3-13
Test the-User threshold 3-14
Test the +User threshold 3-15
Test the 0 VUser threshold 3-16
Test the next pod 3-17
To test the glitch capture (logic analyzer) 3-18
Setup the equipment 3-18
Set up the logic analyzer 3-19
Connect the logic analyzer
3-19
Testthe glitch capture on the connected channels 3-21
Testthe next channels 3-23
To
test the single-clock, single-edge, state acquisition (logic analyzer) 3-24
Set up the equipment 3-24
Set up the logic analyzer 3-25
v

Contents
Connect the logic analyzer 3-27
Verify the test signal 3-29
Check the setup/hold combination 3-31
Test
the next channels 3-36
To
test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 3-37
Set up the equipment 3-37
Set up the logic analyzer 3-38
Connect the logic analyzer 3-40
Verify the test signal 3-42
Check
the setup/hold with single clock edges, multiple clocks 3-44
Test the next channels 3-48
To test the single-clock, multiple-edge, state acquisition (logic analyzer) 3-49
Set up the equipment 3-49
Set up the logic analyzer 3-50
Connect the logic analyzer 3-52
Verify the test signal 3-54
Check the setup/hold with single clock, multiple clock edges
3-56
Test the next channels 3-59
To
test the time interval accuracy (logic analyzer) 3-60
Set up the equipment 3-60
Set up the logic analyzer 3-61
Connect the logic analyzer 3-64
Acquire the data 3-64
To test the CAL OUTPUT ports ( oscilloscope) 3-65
Set up the equipment 3-65
Set up the logic analyzer 3-66
Verify the
DC CAL OUTPUT port 3-67
Set up the logic analyzer 3-68
Verify the AC CAL OUTPUT port 3-68
To test the input resistance (oscilloscope) 3-69
Set up the equipment 3-69
Set up the logic analyzer 3-70
Connect the logic analyzer 3-71
Acquire the data 3-72
Perform an operational accuracy calibration 3-72
To test the voltage measurement accuracy (oscilloscope) 3-73
Set up the equipment 3-73
Set up the logic analyzer 3-74
Connect the logic analyzer 3-75
Acquire the data 3-76
vi

To test the offset accuracy (oscilloscope) 3-77
Set up the equipment 3-77
Set up the logic analyzer 3-78
Connect the logic analyzer 3-79
Acquire the zero input data 3-80
Acquire the DC input data 3-81
To test the bandwidth (oscilloscope) 3-82
Set up the equipment 3-82
Set up the logic analyzer 3-83
Connect the logic analyzer 3-85
Acquire the data 3-86
To test the time measurement accuracy (oscilloscope) 3-87
Set up the equipment 3-87
Set up the logic analyzer 3-88
Connect the logic analyzer 3-90
Acquire the data 3-90
To test the trigger sensitivity (oscilloscope) 3-91
Set up the equipment 3-91
Set up the logic analyzer 3-92
Connect the logic analyzer 3-94
Acquire the data 3-94
Performance Test Record (logic analyzer) 3-95
Performance Test Record (oscilloscope) 3-101
Performance Test Record (pattern generator) 3-104
4 Calibrating and Adjusting
Logic analyzer calibration 4-2
To calibrate the oscilloscope 4-3
Set up the equipment 4-3
Load the Default Calibration Factors 4-4
Self Cal menu calibrations 4-5
5 Troubleshooting
To use the flowcharts 5-2
To check the power-up tests 5-17
To nm the self-tests 5-18
To test the power supply voltages 5-24
To test the LCD display signals 5-26
To test the keyboard signals 5-27
To test the flexible disk drive voltages 5-28
To test the hard disk drive voltages 5-30
Contents
vii

Contents
To perform the BNC test 5-31
To test the logic analyzer probe cables 5-32
To verify pattern output (HP 1660EP-series only) 5-36
The
Ether address 5-38
To test the auxiliary power 5-39
6 Replacing Assemblies
To remove and replace the handle 6-5
To remove and replace the feet and tilt stand 6-5
To remove and replace the cover 6-5
To remove and replace the disk drive assembly 6-6
To remove and replace the power supply 6-7
To remove and replace the CPU board 6-7
To remove and replace SIMM memory 6-9
To remove and replace the switch actuator assembly 6-10
To remove and replace the rear panel assembly 6-11
To remove and replace the HP 1660E-series acquisition board 6-12
To remove and replace the HP 1660ES-series oscilloscope board 6-13
To remove and replace the HP 1660EP-series pattern generatorboard 6-14
To remove and replace the front panel and keyboard 6-15
To remove and replace the LCD display 6-16
To remove and replace the handle plate 6-17
To remove and replace the fan 6-18
To remove and replace the line filter 6-18
To remove and replace the HP 1660EP-series pattern generator cables 6-19
To remove and replace the HP-IB and RS-232-C cables 6-19
To remove and replace the JlO board 6-20
To return assemblies 6-20
7 Replaceable Parts
Replaceable Parts Ordering 7-2
Replaceable
Parts List 7-3
Exploded View
7-4
Power Cables and Plug Configurations 7-8
8 Theory of Operation
Block-Level Theory 8-3
The HP 1660EIESIEP-Series Logic Analyzer 8-3
The Logic Acquisition Board 8-7
The Oscilloscope Board 8-10
The
Pattern Generator Board 8-13
Self-Tests Description 8-15
Power-up Self-Tests 8-15
System Tests (System PV) 8-16
Analyzer Tests (Analy PV) 8-20
Oscilloscope
tests (Scope PV) 8-22
Pattern Generator tests (Patt Gen) 8-23
viii

HP-IE 8-27
RS-232-C 8-28
Contents
ix

1
Accessories 1-2
Specifications
Oogic analyzer) 1-3
Specifications (oscilloscope) 1-4
Specifications (pattern generator) 1-4
Characteristics Oogic analyzer) 1-5
Characteristics (oscilloscope) 1-5
Characteristics (pattern generator) 1-6
Recommended test equipment
Oogic analyzer) 1-9
Recommended test equipment (oscilloscope) 1-10
Recommended test equipment (patterngenerator) 1-11
General Information

General Information
This chapter lists the accessories, the specifications and characteristics, and the
recommended test equipment.
Accessories
The following accessories are suppliedwith the HP 1660EIESIEP-series logic analyzers.
Accessories Supplied
Probe tip assemblies
Probe cables
Grabbers (20
per pack)
Probe ground (5 per pack)
PS2Mouse
HP Part Number
01650-61608
01660-61605
5090-4356
5959-9334
C3751-60201
Qty
Note 1
Note 2
Note 1
Note 1
1
Note 1Quantities: 8 - 1660ElES/EP
6-1661ElES/EP
4-1662ElES/EP
2-1663ElESIEP
Note 2Quantities: 4 - 1660ElES/EP
3 - 1661ElES/EP
2 - 1662ElES/EP
I - 1663ElES/EP
EP-Series Additional Accessories
Accessories
Supplied
Data Output Cable
Clock Output Cable
User's Guide
HP Part Number
16522-61601
16522-61602
01660-97028
Qty
4
1
1
ES-Series Additional Accessories
Accessories Supplied
10:1 probes
BNC miniprobe adapter
User's Guide
HP Part Number
10430A
1250-1454
01660-97028
Qty
2
1
1
Accessories Available
Other accessories available for the HP 1660EIESIEP-serieslogic analyzer are listed in the
Accessoriesjor HP Logic Analyzers brochure.
1-2

General Information
Specifications (logic analyzer)
Specifications Oogic analyzer)
The specifications are the perfonnance standards againstwhich the product is tested.
Maximum State Speed 100
MHz
Minimum State Clock Pulse Width*3.5 ns
*
Minimum Master to Master Clock Time 10.0 ns
Minimum Glitch Width* 3.5 ns
Threshold Accuracy ±(100 mV+ 3% ofthreshold setting)
. *
SetuplHold Tnne:
Single Clock, Single Edge
Single Clock, Multiple Edges
Multiple Clocks, Multiple Edges
0.0/3.5
ns through 3.5/0.0 ns,
adjustable in 500-ps increments
0.0/4.0
ns through 4.0/0.0 ns,
adjustable in 500-ps increments
0.0/4.5
ns through 4.5/0.0 ns,
adjustable in 500-ps increments
* Specified for an input signal VH =-0.9 V, VL =-1.7 V, slew rate =1 V/ns, and threshold =-1.3 V.
1-3

Trigger SensitivityC*)
Input R(selectable) (*)
DC Offset AccuracyC*)
Voltage Measurement Accuracy(*' 3)
General Information
Specifications (oscilloscope)
Specifications (oscilloscope)
The HP 1660ES logic analyzers also include the following specifications:
Bandwidth (*,1) DC to 500 MHz (real time, dc-coupled)
Time Interval Measurement Accuracy(*' 2) ±[ (0. 005% X Dot) +
(2 x10-6xdelay setting)+150 ps]
±(1.0% ofchannel offset +2.0% of full scale)
±[(1.5% of full scale +offset accuracy)
+(0.008xVldiv)]
DC to 50 MHz: 0.063 xfull scale,
50 to 500 MHz: 0.125 x full scale
1 MQ: ±1%, 50 Q: ±1%
* Specifications (valid within ± 10" C of auto-calibration temperature, excluding bandwidth-see note 1 for bandwidth specification.)
1. Upper bandwidth reduces by 2.5 MHz for every degree C above 35° C.
2. Specification applies to the maximum sampling rate. At lower rates, the specification is:± [(0.005% x .6.t)+12 x 10.
6x
delay setting) +
(0.15 x sample interval)] for bandwidth limited signals It = 1.4 x sample interval). Sample interval is defined as samp~e rate
3. Digitizing level = {#Vertical divisions)(~l( L~Bl. where lSB=2ibitsinAOC
Specifications (pattern generator)
There are no specifications for the pattern generator portion of the HI' 1660EP-series logic
analyzers.
1-4

Maximum State Clock Rate
Maximum Conventional Timing Rate
Maximum Transitional Timing Rate
Maximum Timing with Glitch Rate
Memory Depth
Channel Count:
General Information
Characteristics (logic analyzer)
Characteristics (logic analyzer)
These characteristics are not specifications, but are included as additional information.
Full Channel Half Channel
100 MHz 100 MHz
250 MHz 500 MHz
125 MHz 250 MHz
N/A 125 MHz
4K 8K'
HP 1660E,EP,ES
HP 1661E,EP, ES
HP 1662E,EP,ES
HP 1663E,EP,ES
*For all modes exceptglitch.
Characteristics (oscilloscope)
136
102
68
34
68
51
34
17
The HP 1660ES logic analyzers also include the following characteristics:
Maximum Sample Rate 2Gigasample per second
Number of Channels 2
Rise Time()) 0.7 ns
ADC 8-bit real time
Vertical Resolution 8bits over 4vertical divisions (± 0.4%)
Waveform Record Length 8000 points
Vertical (DC) Gain AccuracyC2) ±1.25% offull scale
Input Coupling 1 MQ: ac and DC, 50 Q: DC only
Input CApproximately 7 pF
1. Rise time is calculated from the formula: tr= ba~d~/dth
2. Vertical gain accuracy decreases 0.08% per degree C from software calibration temperature.
1-5

General Information
Characteristics (pattern generator)
Characteristics (pattern generator)
The HP 1660EP logic analyzers also include the following characteristics:
Output channels
Memory depth
Logic levels (data pods)
Data inputs
Clock outputs
Clock input
Internal clock period
External clock period (user supplied)
External clock duty cycle
Maximum number of "IF condition"
blocks at 50 MHz clock
Maximum number ofdifferent macros
Maximum number oflines in amacro
Maximum number ofmacro invocations
Maximum number ofRepeat loop
invocations
Maximum number of Wait event patterns
1-6
16 channels
at 200 MHz clock; 32 channels at
100 MHz clock
258,048 vectors
TTL, 3-state TTlJ3.3v, 3-stateTTUCMOS,
ECL terminated, ECL unterminated, and differential
ECL (without
pod)
3-bit pattern -level sensing (clock pod)
Synchronized
to output data, delay of 11 ns in 9steps
(clock
pod)
DC to 200 MHz (clock pod)
Progranunable from 5
ns to 250 Ils in a1, 2, 2.5, 4, 5, 8
sequence
DC to 200 MHz
2 ns minimum high time
1
100
1024
1,000
1,000
4

AuxiliaryPower
Power through cables
General Information
Characteristics (pattern generator)
1/3 amp at 5 Vmaximum per cable, CAT I, Pollution degree 2.
Operating Environment (for indoor use only)
Temperature Instrument, 0 °C to 55 °C (+32 OF to 131 OF).
Probe lead sets and cables,
o °C to 65 °C (+32 OF to 149 oF).
Humidity Instrument, probe lead sets, and cables, up to
80% relative humidity at +40 °C (+122 OF).
Altitude To 3067 m(l0,000 ft).
Vibration Operating: Random vibration 5 to 500 Hz,
10 minutes per axis, ~0.3 g(rms).
Non-operating: Random vibration 5
to 500 Hz,
10 minutes per axis, ~ 2.41 g(rms);
and
swept sine resonant search, 5 to 500 Hz,
0.75 g(O-peak), 5minute resonant dwell
at 4resonances per axis.
Dimensions
1\r
----I
, I
'"
Cl&7m
13 O·
133001,"1
I
111."
OI(,6U~3'
m'
1-7

General Information
Characteristics (paltern generator)
CE:
ISM I-A
Product Regulatious
Safety IEC 101O-1:1990+Al / EN 61010-1:1993
UL31Il
CSA-C22.2 No. 1010.1:1993
Notes2
Codel
1
1
1
This product meets the requirement of the European
Communities (EC)
EMC Directive 89/336/EEC.
EN5501I/CSIPR
11 (ISM, Groupl,Class Aequipment)
IEC 555-2
and IEC 555-3
EN50082-l
IEC 801-2 (ESD)4kV
CD, 8kV AD
IEC 801-3 (Rad.) 3V/m
IEC 801-4 (EFT) lkV
lperformance Codes:
1PASS -Normal operations, no effect.
2PASS -
Temporary degradation, self recoverable.
3PASS -
Temporary degradation, operator intervention required.
4
FAIL -Not recoverable, component damage.
Emissions
lmmunity
EMC
ON279
1-8

General Information
Recommended
test equipment (logic analyzer)
Recommended test equipment (logic analyzer)
Equipment Required
Equipment Critical Specifications Recommended
Use
•
ModeljPart
Pulse Generator 100 MHz, 3.5 ns pulse width, HP 8133A Option 003
P,T
< 600 ps rise time
Digitizing Oscilloscope ;,6 GHz bandwidth, < 58 ps rise time
HP 54750A, with P
Accuracy" 15l110-') x frequency,
HP 54751A plugin
Function Generator HP 3325B Option 002
P
DC offset voltage ±6.3 V
Digital Multimeter
0.1 mV resolution, 0.005% accuracy HP 3458A P
BNC-Banana Cable HP 11001-60001
P
BNC Tee
BNC (mlitHf) HP 1250-0781 P
Cable BNC Imllm) 48 inch HP 8120-1840 P,T
SMA Coax Cable IUly 3)
18 GHz bandwidth
HP 8120-4948 P
Adapter
IUly 4) SMAlm)-BNC(f) HP 1250-1200 P, T
Adapter
SMAlf)-BNC(m) HP 1250-2015
P
Coupler (Uly 4)
BNC(mllm) HP 1250-0216 P, T
20:1 Probes (Uly 2) HP 54006A P
BNC Test Connector, 17x2
P
IUly 1)"
BNCTestConnector,6x2
P,T
IUly 4('
Digitizing Oscilloscope >
100 MHz Bandwidth HP 54600B T
BNC Shorting Cap HP 1250-0774
T
BNC-Banana Adapter
HP 1251-2277 T
*A = Adjustment P= Performance Tests T= Troubleshooting
**lnstructions for making these test connectors are in chapter 3, "Testing Performance.'
1-9